ORDERING INFORMATION # of Ports Pressure Type Device Name Case No.
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1 Freescale Semiconductor 50 kpa On-Chip Temperature Compensated and Calibrated Silicon Pressure The series devices are silicon piezoresistive pressure sensors that provide a highly accurate and linear voltage output directly proportional to the applied pressure. A single, monolithic silicon diaphragm with the strain gauge and an integrated thin-film resistor network. Precise span and offset calibration with temperature compensation are achieved by laser trimming. Features Temperature Compensated Over 0 C to +85 C Easy-to-Use Chip Carrier Package Options Ratiometric to Supply Voltage Gauge Ported and Non Ported Options Available in Easy-to-Use Tape & Reel Differential and Gauge Pressure Options Series Pressure Rev 8, 02/ to 50 kpa (0 to 7.25 psi) 40 mv Full Scale (Typical) Application Examples Pump/Motor Control Robotics Level Detectors Medical Diagnostics Pressure Switching Blood Pressure Measurement ORDERING INFORMATION # of Ports Pressure Type Device Name Case No. Device Marking None Single Dual Gauge Differential Absolute Small Outline Package (MPXV2053G Series) MPXV2053GP 1369 MPXV2053GP MPXV2053DP 1351 MPXV2053DP MPXV2053GVP 1368 MPXV2053GV Unibody Package ( Series) D 344 D DP 344C DP GP 344B GP MPAK Package (MPXM2053 Series) MPXM2053D 1320 MPXM2053D MPXM2053DT MPXM2053D MPXM2053GS 1320A MPXM2053GS MPXM2053GST1 1320A MPXM2053GS Freescale Semiconductor, Inc., All rights reserved.
2 Pressure UNIBODY PACKAGES D CASE GP CASE 344B-01 DP CASE 344C-01 SMALL OUTLINE PACKAGES MPXV2053GVP CASE MPXV2053GP CASE MPXV2053DP CASE MPAK PACKAGES MPXM2053D/DT1 CASE MPXM2053GS/GST1 CASE 1320A-02 Freescale Semiconductor 2
3 Operating Characteristics Table 1. Operating Characteristics (V S = 10 V DC, T A = 25 C unless otherwise noted, P1 > P2) Pressure Characteristic Symbol Min Typ Max Units Pressure Range (1) Supply Voltage (2) P OP 0 50 kpa V S V DC Supply Current I O 6.0 madc Full Scale Span (3) Offset (4) V FS mv mv Sensitivity ΔV/ΔP 0.8 Non-Linearity %V FS Pressure Hysteresis (0 to 50 kpa) ±0.1 %V FS Temperature Hysteresis (-40 to 125 C) ±0.5 %V FS Temperature Coefficient of Full Scale TCV FS %V FS Temperature Coefficient of Offset TCV OFF mv Input Impedance Z IN Ω Output Impedance Z OUT Ω Response Time (5) (10% to 90%) t R 1.0 ms Warm-Up Time 20 ms Offset Stability (6) ±0.5 %V FS kpa (kilopascal) equals psi. 2. Device is ratiometric within this specified excitation range. Operating the device above the specified excitation range may induce additional error due to device self-heating. 3. Full Scale Span (V FSS ) is defined as the algebraic difference between the output voltage at full rated pressure and the output voltage at the minimum rated pressure. 4. Offset (V off ) is defined as the output voltage at the minimum rated pressure. 5. Response Time is defined as the time for the incremental change in the output to go from 10% to 90% of its final value when subjected to a specified step change in pressure. 6. Offset stability is the product's output deviation when subjected to 1000 hours of Pulsed Pressure, Temperature Cycling with Bias Test. Maximum Ratings Table 2. Maximum Ratings (1) Rating Max Value Unit Supply Voltage 16 V Pressure (P1 > P2) 200 kpa Storage Temperature 40 to +125 C Operating Temperature Range 40 to +125 C 1. Exposure beyond the specified limits may cause permanent damage or degradation to the device. Freescale Semiconductor 3
4 Figure 1 shows a block diagram of the internal circuitry integrated on a pressure sensor chip. Pressure V S 3 X-ducer Sensing Element Thin Film Temperature Compensation and Calibration 2 4 V out+ V out- 1 GND Figure 1. Temperature Compensated Pressure Sensor Schematic Voltage Output versus Applied Differential Pressure The differential voltage output of the sensor is directly proportional to the differential pressure applied. The output voltage of the differential or gauge sensor increases with increasing pressure applied to the pressure side relative to the vacuum side. Similarly, output voltage increases as increasing vacuum is applied to the vacuum side relative to the pressure side. On-Chip Temperature Compensation and Calibration Figure 2 shows the minimum, maximum and typical output characteristics of the series at 25 C. The output is directly proportional to the differential pressure and is essentially a straight line. A silicone gel isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the silicon diaphragm. 40 V S = 10 Vdc 35 T A = 25 C MAX kpa PSI 1.8 Output (mvdc) TYP MIN SPAN RANGE (TYP) OFFSET (TYP) Figure 2. Output vs. Pressure Differential Freescale Semiconductor 4
5 LINEARITY Linearity refers to how well a transducer's output follows the equation: V out = V off + sensitivity x P over the operating pressure range. There are two basic methods for calculating nonlinearity: (1) end point straight line fit (see Figure 3) or (2) a least squares best line fit. While a least squares fit gives the best case linearity error (lower numerical value), the calculations required are burdensome. Pressure Conversely, an end point fit will give the worst case error (often more desirable in error budget calculations) and the calculations are more straightforward for the user. The specified pressure sensor linearities are based on the end point straight line method measured at the midrange pressure. Least Squares Fit Exaggerated Performance Least Square Deviation Relative Voltage Output End Point Straight Line Fit Straight Line OFFSET Pressure (% Full scale) Figure 3. Linearity Specification Comparison Figure 4 illustrates the differential or gauge configuration in the basic chip carrier (Case 344). A silicone gel isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the silicon diaphragm. The series pressure sensor operating characteristics and internal reliability and qualification tests are based on use of dry air as the pressure media. Media other than dry air may have adverse effects on sensor performance and long term reliability. Contact the factory for information regarding media compatibility in your application. Refer to application note AN3728, for more information regarding media compatibility. Wire Bond Silicone Die Coat Die P1 Stainless Steel Metal Cover Epoxy Case Lead Frame P2 RTV Die Bond Figure 4. Unibody Package Cross-Sectional Diagram (Not to Scale) Freescale Semiconductor 5
6 B J C M -T- SEATING PLANE -A- PIN 1 F D 4 PL R (0.005) M T G N A M L 1 F 2 3 Y DAMBAR TRIM ZONE: THIS IS INCLUDED WITHIN DIM. "F" 8 PL 4 Z NOTES: DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: INCH. DIMENSION -A- IS INCLUSIVE OF THE MOLD STOP RING. MOLD STOP RING NOT TO EXCEED (0.630). INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC J L M 30 NOM 30 NOM N R Y Z STYLE 1: PIN 1. GROUND 2. + OUTPUT 3. + SUPPLY 4. - OUTPUT STYLE 2: PIN 1. VCC 2. - SUPPLY 3. + SUPPLY 4. GROUND STYLE 3: PIN 1. GND 2. -VOUT 3. VS 4. +VOUT CASE ISSUE AA UNIBODY PACKAGE SEATING PLANE -P- -T- J R C N B -Q- PORT #1 POSITIVE PRESSURE (P1) 0.25 (0.010) M T Q PIN 1 S F G H D 4 PL L S K 0.13 (0.005) M S Q S T S -A- U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC H J K L N P Q R S U BSC BSC STYLE 1: PIN 1. GROUND 2. + OUTPUT 3. + SUPPLY 4. - OUTPUT CASE 344B-01 ISSUE B UNIBODY PACKAGE 6 Freescale Semiconductor
7 R PORT #2 SEATING PLANE PORT #1 SEATING PLANE PORT #2 VACUUM (P2) J V C B N W F G D 4 PL -Q- PIN 1 -P- -T- -T (0.010) M T Q S -A- U (0.005) M T S S Q S S L H PORT #1 POSITIVE PRESSURE (P1) K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC H J K L N P Q R S U BSC BSC V W STYLE 1: PIN 1. GROUND 2. + OUTPUT 3. + SUPPLY 4. - OUTPUT CASE 344C-01 ISSUE B UNIBODY PACKAGE Freescale Semiconductor 7
8 PAGE 1 OF 2 CASE ISSUE A SMALL OUTLINE PACKAGE Freescale Semiconductor 8
9 PAGE 2 OF 2 CASE ISSUE A SMALL OUTLINE PACKAGE 9 Freescale Semiconductor
10 PAGE 1 OF 2 CASE ISSUE B SMALL OUTLINE PACKAGE Freescale Semiconductor 10
11 PAGE 2 OF 2 CASE ISSUE B SMALL OUTLINE PACKAGE 11 Freescale Semiconductor
12 CASE ISSUE B PAGE 1 OF 2 Freescale Semiconductor 12
13 PAGE 2 OF 2 CASE ISSUE B Freescale Semiconductor 13
14 PIN 4 PIN 1 CASE 1320A-02 ISSUE A PAGE 1 OF 2 Freescale Semiconductor 14
15 PAGE 2 OF 2 CASE 1320A-02 ISSUE A Freescale Semiconductor 15
16 CASE ISSUE B SMALL OUTLINE PACKAGE SURFACE MOUNT Freescale Semiconductor 16
17 CASE ISSUE B SMALL OUTLINE PACKAGE SURFACE MOUNT Freescale Semiconductor 17
18 CASE ISSUE B SMALL OUTLINE PACKAGE SURFACE MOUNT Freescale Semiconductor 18
19 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc All rights reserved. Rev. 8 02/2009
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Freescale Semiconductor Application Note AN3052 Rev. 0, 11/2005 Implementing PFC Average Current Mode Control using the MC9S12E128 Addendum to Reference Design Manual DRM064 by: Pavel Grasblum Freescale
2 Receiver Tests Packet Error Rate (PER), Reported Energy Value, and Clear Channel Assessment (CCA) are used to assess and characterize the receiver.
Freescale Semiconductor Application Note Document Number: AN2985 Rev. 1.1, 08/2005 MC1319x Physical Layer Lab Test Description By: R. Rodriguez 1 Introduction The MC1319x device is a ZigBee and IEEE 802.15.4
RF LDMOS Wideband Integrated Power Amplifiers
Technical Data RF LDMOS Wideband Integrated Power Amplifiers The MW4IC00 wideband integrated circuit is designed for use as a distortion signature device in analog predistortion systems. It uses Freescale
NTNUS3171PZ. Small Signal MOSFET. 20 V, 200 ma, Single P Channel, 1.0 x 0.6 mm SOT 1123 Package
NTNUS7PZ Small Signal MOSFET V, ma, Single P Channel,. x.6 mm SOT Package Features Single P Channel MOSFET Offers a Low R DS(on) Solution in the Ultra Small. x.6 mm Package. V Gate Voltage Rating Ultra
MJD44H11 (NPN) MJD45H11 (PNP)
MJDH (NPN) MJD5H (PNP) Preferred Device Complementary Power Transistors For Surface Mount Applications Designed for general purpose power and switching such as output or driver stages in applications such
UMC2NT1, UMC3NT1, UMC5NT1
UMCNT, UMC3NT, UMC5NT Preferred Devices Dual Common BaseCollector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The Bias Resistor Transistor
ARCHIVE INFORMATION MW4IC2230MBR1 MW4IC2230GMBR1. Freescale Semiconductor. Technical Data. Document Number: MW4IC2230 Rev.
Technical Data Replaced by MW4IC2230NBR1(GNBR1). There are no form, fit or function changes with this part replacement. N suffix added to part number to indicate transition to lead- free terminations.
EMC, ESD and Fast Transient Pulses Performances
Freescale Semiconductor Application Note AN3569 Rev. 1.0, 10/2008 EMC, ESD and Fast Transient Pulses Performances (MC10XS3412) 1 Introduction This application note relates the EMC, fast transient pulses
MMUN2211LT1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
MMUNLT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NVLJD4007NZTBG. Small Signal MOSFET. 30 V, 245 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package
NVLJD7NZ Small Signal MOSFET V, 2 ma, Dual, N Channel, Gate ESD Protection, 2x2 WDFN Package Features Optimized Layout for Excellent High Speed Signal Integrity Low Gate Charge for Fast Switching Small
Low Capacitance Transient Voltage Suppressors / ESD Protectors CM QG/D. Features
Low Capacitance Transient Voltage Suppressors / ESD Protectors CM1250-04QG Features Low I/O capacitance at 5pF at 0V In-system ESD protection to ±8kV contact discharge, per the IEC 61000-4-2 international
NSVEMD4DXV6T5G. Dual Bias Resistor Transistors. NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias
MUN5211DW1T1 Series. NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
MUNDWT Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor
SN74LS122, SN74LS123. Retriggerable Monostable Multivibrators LOW POWER SCHOTTKY
Retriggerable Monostable Multivibrators These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance
RF Power Field Effect Transistors N- Channel Enhancement- Mode Lateral MOSFETs
Technical Data RF Power Field Effect Transistors N- Channel Enhancement- Mode Lateral MOSFETs Designed for GSM and GSM EDGE base station applications with frequencies from 18 to 2 MHz. Suitable for TDMA,
NTTFS5116PLTWG. Power MOSFET 60 V, 20 A, 52 m. Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant
Power MOSFET 6 V, 2 A, 52 m Features Low R DS(on) Fast Switching These Devices are Pb Free and are RoHS Compliant Applications Load Switches DC Motor Control DC DC Conversion MAXIMUM RATINGS ( unless otherwise
MC10H352. Quad CMOS to PECL* Translator
Quad CMOS to PECL* Translator Description The MC10H352 is a quad translator for interfacing data between a CMOS logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is
BAV70DXV6T1, BAV70DXV6T5 Preferred Device. Monolithic Dual Switching Diode Common Cathode. Lead-Free Solder Plating.
BAV70DXV6T1, BAV70DXV6T5 Preferred Device Monolithic Dual Switching Diode Common Cathode LeadFree Solder Plating MAXIMUM RATINGS (EACH DIODE) Rating Symbol Value Unit Reverse Voltage V R 70 Vdc Forward
MMBZxxVAWT1G Series, SZMMBZxxVAWT1G Series. 40 Watt Peak Power Zener Transient Voltage Suppressors. SC 70 Dual Common Anode Zeners for ESD Protection
MMBZxxVAWTG Series, SZMMBZxxVAWTG Series 4 Watt Peak Power Zener Transient Voltage Suppressors SC 7 Dual Common Anode Zeners for ESD Protection These dual monolithic silicon Zener diodes are designed for
LM339S, LM2901S. Single Supply Quad Comparators
LM339S, LM290S Single Supply Quad Comparators These comparators are designed for use in level detection, low level sensing and memory applications in consumer and industrial electronic applications. Features
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Preferred Device Small Signal MOSFET 500 ma, 60 Volts N Channel Features
BD809 (NPN), BD810 (PNP) Plastic High Power Silicon Transistor 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS
BD89 (NPN), BD8 (PNP) Plastic High Power Silicon Transistor These devices are designed for use in high power audio amplifiers utilizing complementary or quasi complementary circuits. Features DC Current
EMC5DXV5T1, EMC5DXV5T5
EMC5DXV5T, EMC5DXV5T5 Preferred Devices Dual Common Base Collector Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor)
MUN5211T1 Series. NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network NPN SILICON BIAS RESISTOR TRANSISTORS
MUNT Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single
NSV2029M3T5G. PNP Silicon General Purpose Amplifier Transistor PNP GENERAL PURPOSE AMPLIFIER TRANSISTORS SURFACE MOUNT
PNP Silicon General Purpose Amplifier Transistor This PNP transistor is designed for general purpose amplifier applications. This device is housed in the package which is designed for low power surface
NB2879A. Low Power, Reduced EMI Clock Synthesizer
Low Power, Reduced EMI Clock Synthesizer The NB2879A is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. The NB2879A reduces ElectroMagnetic
MMSD301T1G SMMSD301T1G, MMSD701T1G SMMSD701T1G, SOD-123 Schottky Barrier Diodes
MMSD3TG, SMMSD3TG, MMSD7TG, SMMSD7TG, SOD-3 Schottky Barrier Diodes The MMSD3T, and MMSD7T devices are spinoffs of our popular MMBD3LT, and MMBD7LT SOT3 devices. They are designed for highefficiency UHF
NTMD4840NR2G. Power MOSFET 30 V, 7.5 A, Dual N Channel, SOIC 8
NTMDN Power MOSFET 3 V, 7. A, Dual N Channel, SOIC Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual
P2I2305NZ. 3.3V 1:5 Clock Buffer
3.3V :5 Clock Buffer Functional Description P2I2305NZ is a low cost high speed buffer designed to accept one clock input and distribute up to five clocks in mobile PC systems and desktop PC systems. The
P D Storage Temperature Range T stg - 65 to +175 C Operating Junction Temperature T J 200 C
Technical Data Document Number: MRF6S186 Rev. 2, 5/26 Replaced by MRF6S186NR1/NBR1. There are no form, fit or function changes with this part replacement. N suffix added to part number to indicate transition
NTMS5835NL. Power MOSFET 40 V, 12 A, 10 m
Power MOSFET V, 2 A, m Features Low R DS(on) Low Capacitance Optimized Gate Charge These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise stated) Parameter