Introduction. design. The converte protection. mode active. the current. absent. As shown in. critical. Page 1 of Rev. 1.0.

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1 February 03 Deign of ritical onduction AOZ7 Mode (RM) PF ircuit with the Introduction Thi application note introduce the practical deign procedure. It include how to deign the inductor, elect the bulk capacitor, MOSFET, boot diode, current ene reitance, t capacitor, the control loop compenation network and o on. We implement a 395, 60W, RM PF converter uing the AOZ7 to verify the deign. The converte exhibit feature uch a high PF, low tandby power diipation, high efficiency, and a robut protection. The AOZ7 i a voltage mode active power factor correction controller deigned for cot-effective boot PF application that operate in critical conduction mode (RM). It voltage mode cheme doe not need an A input line-ening network, which i uually neceary for a current mode RM PF controller. Alo, it receive a ZD ignal pule from the current ene reitor; therefore, ZD auxiliary winding i not needed. The AOZ7 i available in a SO-8 package. It provide put over-voltage protection, over-current protection, open-feedback protection, and under-voltage lock protection. The unique A input fault detection circuit make the ytem more robut during A abent tet. The additional OP pin can be ued to double check the put voltage if the feedback reitor get damaged. The controller implement comprehenivee afety feature for robut deign. Baic Principle of RM PF onverter IL Id Iin A POWER DM APAITOR AOZ 7 BULK APITOR Id Rene Figure. PF onverter with AOZ7 A hown in Figure, the PF boot converterr require a coil, a diode and a power witch. In critical conduction mode, the inductor current I L tart from zero up to peak current. If the turn-onn time (t on ) i contant for a fixed time, the peak current will be proportional to the input voltage a hown in Figure. The averaged triangular current in each witching period i alo proportional to the input voltage, thu the input current drawn from the ource follow the input voltage waveform with very highh accuracy. Page of

2 IL Peak Inductor current Input average current GS TON Figure. Waveform of Inductor urrent and Driver Deign Procedure A 60W PF application with univeral input range i elected a a deign example; it how uer the deign procedure tep by tep. D D o L R R9 BD R3 R0 X M cc cc I OUT R8 R6 D3 Q R4 R5 R6 R R R3 N D OUTPUT R8 t IN AOZ7 OMP OP X FL 5 6 R9 7 S R 8 GND ZD3 D7 R7 0 R7 R4 R8 9 R5 R5 R R R3 FU AR NT N A INPUT Figure 3. AOZ7 Evaluation Board Schematic Page of

3 STEP-Define the Specification The pec of the converter i hown in the table below. Minimum Input oltage Maximumm Input oltage Minimum Line Frequency Maximum Line Frequency Nominal Output oltage Output Ripple oltage Hold Up Time Maximum Output oltage Minimum Switching Frequency Full Load Output urrent Full Load Output Power Target Full Load Efficiency Minimum Full Load Power Factor ac(min) = 90 ac(max) = 64 f l line(min) = 47Hz f l ine(max) = 63Hz = 395 (ripple) = 0 t hold = 0m (max) = 440 f w(min) = 57kHz I = 0.405A P = 60W η = 95% PF = 0.95 STEP-Power Stage omponent Selection. Power Inductor Selection The boot inductor value i determined by the put power and the minimum witching frequency. It i calculated by the equation below: Where L i the boot inductance. The minimumm frequency occur at maximum input voltage ( ac(m max) = 64) and full load condition a hown in Figure 4. According to eq-, the inductor value i calculated a: We elect the value a 00µH. ac L fw(min) ) P L ac 64 89H 395 (eq-) Page 3 of

4 Figure 4. Switch Frequency v. Input RMS oltage (at inuoid top) At minimum input voltage and maximum put power, the inductor peak current reache the maximum, which caue the greatet tre to the power component. The inductor peak current i calculated by: P 60 ILpk 5. 9A (eq-) ac Auming EER309NA core i elected and etting B (max) a 0.3T, the primary winding hould be: ILpk L Ninductror A e B(max) H 30.7mm 39T (eq-3) 0. The number of turn of the boot inductor i determined a 39. Figure 5 how the appearance of ER309N core and bobbin (A e = 30.7mm, A w = 8.8mm ). According to the typical B-H characteritic of ferrite core from SAMWHA (PL-7), the aturation flux denity decreae a the temperature increae, o the high temperature characteritic hould be conidered c (aturation flux B (max) = 00deg). Figure 5. EER309N Ferrite Specification When Φ0.0mm 50 (litz wire) i ued, the RMS current of inductor coil, current denity and the window coefficient are: P ILrm L 60 3 ac(min) A (eq-4) ILdenity L A mm (eq-5) Page 4 of

5 0. 50 Np 0.3 N aux A co Aw Figure 6 how the winding of the inductor: EER309N, Np, Np 3,4 3,4 Figure 6. Winding the Inductor Winding pecification Np Inulation tape Pin 3,4, Diameter Φ0.0mm 50 (litz wire) 0.05mm Turn 39 3 Tet condition: Inductance Pin 3,4, Spec. 00µH (5%) Tet condition 00KHz,. Bulk apacitor Selection According to the ripple pecification of 0 p-p, the capacitor hould be: bulk According to the minimumm allowable put voltage 35 (0.8 ) during one cycle line (0m drop-, the capacitor hould be: bulk I F (eq-6) fline(min) ( ripple) P t hold (min) 60 0 m 35 3 F (eq-7) 395 The put capacitor mut be larger than 9µF, o the two electrical capacitor (68µ/450) parallel are elected. 3. MOSFET and Output Diode Selection To begin, we need to know the voltage tre of the MOSFET: d(max) (max) d (max) (eq-8) Where d(ma x) i the maximum voltage tre of MOSFET. Page 5 of

6 The d(max) i the maximum forward voltage drop of put diode. We can elect AOS AOTF60 MOSFET, it maximum R d(on) i 0.4Ω, maximum o (energy related) i 90pF at drain-ource voltage i 480, ex xt i zero. The put diode BY9X i elected, f(max) i.6 at 5, 8A. The MOSFET and Output Diode RMS current are calculated a: 8 ac(min) Id( rm ) IL( rm A (eq-9) I I d ( ave) A (eq-0) The MOSFET lo can bee divided into three part: conduction lo, turn-off lo, and turn-on lo. onduction lo can be obtained a: P d ( con) Id( rm ) R d( on ) W (eq-) Turn-off lo can be calculated a: P d ( off ) Where I in(rm i the input RMS current, t off i the turn-off time and f w(min) i the minimum witch frequency. Turn-on lo can be calculated a: P d ( on ) Iin( rm toff f w(min) 395 o ext fw(min).87 50n 57k. 05WW (eq-) 90 p W (eq-3) o i the put capacitance of the MOSFET. ext i an externally addedd capacitor at drain and ource of MOSFET. The total lo of o MOSFET i: P d ( total ) Pd ( con ) P d( off ) P d ( on ).89W (eq-4) The power lo of the put diode i calculated a: P d ( lo Id( av e ) f (max) W (eq-5) 4. urrent-sene Reitor Selection and S ircuit Deign The firt role of R c i to et hut down mode over current protection level. According to the eq-, the maximum inductor current i I Lpk, andd ening reitor i calculated a: ocp Rc ILpk hooing 0.Ω a R c, power lo i calculated a: (eq-6) P r ( lo IL( rm ) R c. 6 0.W 0.47W (eq-7) Recommended power rating of ening reitor i W. Page 6 of

7 STEP3-The S pin delay time contant election The econd role of R c i detecting the zero current point of the boot inductor. The negative ignal c i applied to the current ene pin. When c i higher than the threhold (-5m), it mean the inductor current i nearly zero. In order to minimize the contantt turn-on time deterioration and turn-on lo, we hould trigger the gate at the drain ource voltage valley point, which may need additional delay by the external reitor and capacitor. The required delay time i one-half of the reonant period; approximately: Rzcd zcd 650n eff L (eq-8) Where eff i the effective capacitor hown at the MOSFET drain to ource; zcd and R zcd are the capacitance and reitor at S pin; "650n" i the I internal et delay time. external H: Driverr oltage H: d (MOSFET Drain and Dource oltage) H3: Inductor urrent Figure 7. Realitic RM Waveform with R zc cd and Load The time between both dotted line i the delay time. We can elect the appropriated R zc cd and zcd to achieve minimum drain voltage turn-on. Thee value are found experimentally. STEP4-The t capacitor election When the PF operate in critical conduction mode, a boot converter preent two phae. During the power witch conduction time, the current ramp-up from zero to the envelope level. At that moment, the power witch turn off and the current ramp-down to zero. The maximum on-time of the controller occur when comp i at the maximum. The t capacitor i ized to enure thatt the required on-time i reached at maximum put power and the minimum input voltage condition: ton L ILpk ( t ) L Iin in( t ) ac in( t ) ac in( t ) L I in ac P L ac (eq-9) In regard to the AOZ7; the on time wa controlled with the capacitor connected to the t pin. A current ource charge the t capacitor to a voltage ( ct(off) ) derived from OMP pin voltage. t ct( off ) ton (eq-0) Ichargerr Page 7 of

8 From the dataheet of AOZ7, we have: ct(m max) = 8 (typical); ct(offe et) = (typical), I charger (maximum), then: P L Icharger t(m in) pf (eq-) 8 ac A value of 470p/50 provide ufficient margin. P L Icharger ct( off ) comp ct( offet ) ac t comp ct( offet ) (eq-) = 50µA STEP5-FB, OP, and UP Divider Reitor Selection R fb and R fb form a reitor divider that cale down beforee it i applied to the IN pin. The error amplifier adjut the on-time of the drive to maintain the FB pin voltage equal to the error amplifier referencee voltage ( ref ). The divider network bia current (I bia ) election i the firt tep in the calculation. The divider network bia current i elected to optimize the trade-off of noie immunity and power diipation. R fb i calculated a: R 395 fb 4.9M (eq-3) I bia 80A A bia current of 80µA provide an acceptable trade-off of power diipation to noie immunity. A erie of five reitor of MΩ/0805 are elected. R ref Rfb.5 5M fb 3.85 k (eq-4) ref R fb i elected by a reitor of 30K/0805 and a reitor of.8k/0805 which are in erie. R fb R fb 5 M 3.8k ref R fb 3.8k The AOZ7 include two integrated OP circuit to prevent the put from exceeding a afe voltage. The firt OP circuit compare FB to the internal comparator reference ( ref =..685) to determine if an OP fault occur. R R ovp 5M 3.8k ref (eq-6) R 3.8k The econd OP circuit compare the external new reitor divider (R 3 and R 4 ) applied to pin 4 reference ( ref =.75) to double check the put voltage. R ovp i the ame a the R fb. The R ovp i reelected a 4.9k/0805 and 5.9k/08055 which are in erie. R 3 R ovp 4 5M 30.8k ref R k (eq-7) (eq-5) STEP6-ompenation Network Selection After deigning the power component, we will help the uer deign the control loop compenation network. To find a compenation network, it i neceary to get the control loop model of thi converter. Thi can be yntheized a hown in Figure 8. Page 8 of

9 inrm ref( + - Error amplifier Gcomp( comp( Ramp ontrol G3( ton( PWM modulator G( Ilpk( Power tage G( ( ZD Feedback H( Figure 8. ontrol Loop of PF. Power Stage We aume that the control action take place on the peak amplitude of variou quantitie inide the loop. The firt tep i to determine the tranfer function of power tage, defined a: G ( d di Lpk d di di di Lpk (eq-8) Where i the D put voltage, I Lp pk i the peak value of inductor current, I i D put current. The power tage can be modeled: a control current ource (with hunt reitance R e ) that drive the put bulk capacitor o and the load reitancee R L (= /I). The zero due to ESR aociated with o i far from croover frequency thu it i neglected. The current ource can be characterized with the following conideration: the low frequency component of the boot diode current i found by averaging the dicharge portion of inductor current over a given witch cycle. Id_ave Re RL Figure 9. Power Stage Model and Boot PF urrent Page 9 of

10 The low frequency currentt averaged over a half-cycle yield the D put current I d(ave): I d ( ave) T T in in(t ) ILpk in(t ) dt in I 0 Lpk 4 (e Where I Lpk i the peak inductor current at ωt = π /. in i effective (RMS) input voltage. Therefore, we can obtain the t tranfer function G ( of -to-i Lpk : eq-9) ( I d ( ave)( R ( R G ( in L ILpk( 4 RL o The tranfer function G ( of I Lpk -to-t on i: R L in 4 L o ILpk( R L RL o (eq-30) (eq-3) ILpk G ( ) ( ) ton( in L (eq-3) The tranfer function G 3( of t on -to- com p i: ton( ) G 3( t comp( Icharger Finally, we can obtain the whole tranfer function G power( of -to- comp : G pow wer ( Where t i 470pF, I charger i 00µA, ou ut i 395, R L i full load (975Ω), o i 36µF, G pow wer ( ( ( comp ( G GG alculated bode plot of tranfer function G power( : ( G3( I charger in t R L 4 L p (eq-33) (eq-34) p. RLo (eq-35) Page 0 of

11 . ompenation E/AA Tranfer Function The tranfer function of E/ /A: comp( G comp( ( Go fcz fcp (eq-36) We can obtain that the zero i fcz G.5 R The G m i the tranconductance (00µS) of the E/A.. o G m, the pole i fcp fcr fz fcr fp R, the D gain i calculated a: (eq-37) 3. The Whole Open Loop Tranfer Function G who ole( G t powerr ( Icharger in 4 L R L L R o Go fz (eq-38) fp 4. Feedback Network implementation Deired croover c frequency: Zero: Pole: fcr = 5Hz fcz = 4.6Hz fcp = 7Hz We know that when f fcr, the function G whole ( j) equal to, then G whole ( j), fcr, p G RL o we can obtain: whole( j) t Icharger ini RL 4 L fcr fz G o fcr fc fcr p fp (eq-39) We know p obtain a: fcr,, o fcr p fcr, ubtitute the numerical value, we can p G whole( j) Serie compenation capacitor: fcr nFF fcr( real ) (eq-40) (eq-4) Page of

12 0.33µF/50 i elected. Serie compenation reitor: R f cz( real ) K (eq-4) 33K/0805 i elected. Parallel compenation capacitor: p p // R f cp nf (eq-43) 7 p p p 0.33F 4nF 0.33F 4nF 46.8 nf (eq-44) 47nF/50 i elected. 5. alculated Overall Loop Bode Plot G whole( G power ( ) G comp( I t charger 4 in R L L R L o G o fz fp (eq-45) alculated bode plot: ro frequency: Phae Margin: f cr( real ) rootg whole ( f ), f 5.944Hz arg G whole( fcr ) deg (eq-47) (eq-46) Page of

13 Appendix Experimental erification The table i the experimental reult of the converter. in 90 ac 5 ac 30 ac 64 ac P(W) Pin(W) ŋ (%) PF THD Start-up waveform of put voltage: Figure 0 and how the tart-up time for 5 ac full load and no load. The inductor current increae moothly due to keep in the cloed loop oft-tart. H: D Output oltage H4: Inductor urrent Figure 0. Start-Up Waveform of ou ut at 5 ac Full Load H: D Output oltage H4: Inductor urrent Figure. Start-Up Waveform of ou ut at 5 ac No Load Page 3 of

14 Figure and 3 how the put voltage repone when the A input i omitted for 0m and 40m. A Figure oberved that comp increaed when the A input i abent for 0m, the peak inductor current i limited cycle-by-cyclto zero rapidly and retart moothly when A i applied again a Figure 3 hown. by OP comparator. But when the A input i abent for over 0m, the comp i reduced H: comp H: D Output oltage H3: Sene Reitor oltage H4: A Input urrent Figure. A-Abent for 0m Detection Operation H: com p H: D Output oltage H3: Sene Reitor oltage H4: A Input urrent Figure 3. A-Abent for 40m Detection Operation Page 4 of

15 Figure 4 and 5 how the put repone and inductor current for 5 ac full load and 5 ac no load. H: D Output oltage H4: Inductor urrent Figure 4. Output Repone of Dynamic Load (60W 60W@30 a ac) H: D Output oltage H4: Inductor urrent Figure 5. Output Repone of Dynamic Load (60W 60W@30 a ac) Page 5 of

16 Loop gain. The frequency repone i meaured at four condition. Figure 6 how that at 64 ac input voltage the croover frequency i 0.44Hz and the phae margin i 57..0deg. Figure 7 how 30 ac input voltage, the croover frequency i 8.44Hz and the phae margin i 54.7deg. Figure 8 how 5 ac input voltage, the croover frequency i 6.9Hz and the phae margin i 5.7deg. Figure 9 how 90 ac input voltage, the croover frequency i 5.Hz and the phae margin i 5.deg. Figure 6. Phae a ac-50hz Full Load Figure 7. Phae a ac-50hz Full Load Page 6 of

17 Figure 8. Phae ac -50Hz Full Load Figure 9. Phae ac c-50hz Full Load Page 7 of

18 Appendix : PB LAYOUT Figure 0. Recommended PB Lay PB Lay Guide The following point are good PB lay guild-line for a PF tage.. To keep the I GND pin a clean a poible, the power tage ground and the ignal ground mut be eparated. Then both ground are connected by a eparated ignal line. At the ame time, the ignal ground end of thi line hould be connect to the end of current ene reitor which i connected to power ground a hown in Figure 0. Figure how that if the ignal ground end connect directly to the power tage ground, the S pin i eaily interrupted. Figure how, the inductor current ramp-up to a higher level and become ditorted ince the ignal ground i interrupted by noie and the I cannot detect the zero current ignal. Page 8 of

19 Break-off thi line which connect from the end of ignal ground pin (pin 6) to the current ene reitor end which join the power ground. onnect thi end directly to the power tage ground. Figure. Bad Lay ( The Signal Ground onnect Directly to Power Ground) H: Inductor urrent H4: Input urrent Figure. Interrupted Input urrent Waveform and Inductor urrent Page 9 of

20 . The PF MOSFET gate drive loop path hould be minimized 3. Minimize the trace length to IN pin. Since the feedback node i high impedance, the trace from the pu reitor divider to IN pin hould be a hort a poible. 4. Switching current ene (S pin) i very important for the table operation of PF tage. Normally, a R filter i recommended to reduce the noie applied to S pin. 5. The cc decoupling capacitor vcc need to be placed a cloed a poible to I cc and GND pin. Appendix : BILL OF MATERIALS (BOM) Ref Deignation FU NT AR X FL X BD M L Q D, R5 D R~ ~R6, R9~R3 R7 R8 R4 R5 0 9 R 8 R7 R6 R8 D3,D7 ZD3(optional) R R9 4 3 I alue Decription 5A/50 Fue, 5A/50 SK-044K NT, SK-044K 0D-47 AR, 0D-47 0.µ/75A X AP, 0.µ µf/75a 5mH ommon mode EMI filter, 5mH 0.33µF/75A X AP, 0.33µ µf/75a D5XB60 A Bridge rectifier, D5XB µF/630 DM filter cap, 0.68µF/630 00µH PF chock, 00µH AOTF60 AOTF60 BY9X PF boot diode, BY9X 68µF/450 Bulk cap, KMF 450/68µF 0.Ω/5W Rene reitor, 0.Ω/5W N5408 Diode, N5408 MΩ 7KΩ 4.KΩΩ 7KΩ 3.9KΩ nf/50 0nF/50 40Ω 00pF/50 0KΩ 0Ω.4Ω LL Zener 0Ω 470pF/50 0.uF/50 47nF/50 0KΩ 0.µF/50 µf/50 AOZ7 Thick Film Re, % Thick Film Re, % 0603 Thick Film Re, % 0603 Thick Film Re, % 0603 Thick Film Re, % 0603 eramic ap, 50, X5R/X7RR 0603 eramic ap, 50, X5R/X7RR 0603 Thick Film Re, % 0603 eramic ap, 50, X5R/X7RR 0603 Thick Film Re, % Thick Film Re, % Thick Film Re, % Package EER309 TO-0F TO-0F DO Zener 0.5W Thick Film Re, % 0603 eramic ap, 50, X5R/X7RR 0603 eramic ap, 50, X5R/X7RR 0603 eramic ap, 50, X5R/X7RR 0603 Thick Film Re, % 0603 eramic ap, 50, X5R/X7RR 0603 E ap, 50 5* RM PF ontroller SO-8 Manufacturer AOS NXP Samyoung AOS Page 0 of

21 LEGAL DISLAIMER Alpha and Omega Semiconductor make no repreentation or warrantie with repect to the accuracy or completene of the informationn provided herein and take no liabilitie for the conequence of ue of uch information or any product decribed herein. Alpha and Omega Semiconductor reerve the right to make change to uch information at any time with furtherr notice. Thi document doe not contitute the grant of any intellectual property right or repreentation of noninfringement of any third party intellectual property right. LIFE SUPPORT POLIY ALPHA AND OMEGA SEMIONDUTOR PRODUTS ARE NOT AUTHORIZED FOR USE AS RITIAL OMPONENTS IN LIFE SUPPORT DEIES OR SYSTEMS. A ued herein:. Life upport device or ytem are device or ytem which, (a) are intended for urgical implant into the body or (b) upport or utain life, and (c) whoe failure to perform when properly ued in accordance with intruction for ue provided in the labeling, can be reaonably expected to reult in a ignificant injury of the uer.. A critical component in any component of a life upport, device, or ytem whoe failure to perform can be reaonably expected to caue the failure of the life upport device or ytem, or to affect it afety or effectivene. Page of