AREA EFFICIENT CODE CONVERTERS BASED ON QUANTUM-DOT CELLULAR AUTOMATA

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1 International Journal of Civil Engineering and Technology (IJCIET) Volume 10, Issue 02, February 2019, pp , Article ID: IJCIET_10_02_067 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed AREA EFFICIENT CODE CONVERTERS BASED ON QUANTUM-DOT CELLULAR AUTOMATA Department of Computer Engineering, Kumoh National Institute of Technology, Gumi, Gyeongbuk, South Korea. ABSTRACT Quantum-dot Cellular Automata (QCA) is an alternative innovation to the Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling limitations that lead to high leakage power. QCA is structured on quantum cells, whose sizes are on the nanoscale. This component causes faults in QCA circuits. Converting a code into another that is programmed in logic arrays becomes important in the physical realization of the circuits. There are many methods to resolve this problem in circuits. A code converter is a solution to convert one code into another. In this paper, QCA-based 4-bit binary-to-gray and 4-bit gray-to-binary code converters are suggested. The offered layout prospects to a decrease in energy expenditure and can be utilized in many fields for shielding data from outsiders and increasing information flexibility. We executed a relative analysis of the suggested design with present earlier designs and turned out that the suggested layout is productive on condition that complexity, cell count, area intake, and clocking. This paper offers a streamlined design and layout concerning code converters depending on QCA. These structures are designed with the QCADesigner, simulator and the simulation results are examined. Key words: Quantum-dot cellular automata, binary code, gray code, converter, power consumption. Cite this Article:, Area Efficient Code Converters Based on Quantum- Dot Cellular Automata, International Journal of Civil Engineering and Technology, 10(02), 2019, pp INTRODUCTION Low-power and efficient technologies are the prime concerns for very-large-scale integration (VLSI) system creators. In addition, high-speed binary-to-gray code converters with low power consumption have undeniably turned out to be stand-outs among the most crucial components of a processor be-cause they are generally utilized in the arithmetic logic unit. Another consideration in the design of a low-power area-effective binary-to-gray code converter is the delay that influences the general execution of the circuit. Extensive improvements in the editor@iaeme.com

2 field of compact systems and cellular networks have escalated research efforts in low-power microelectronics. In VLSI implementation, the significant issues are heat dissemination and power utilization. In order to manage among regarding concerns it is essential to decrease the power provide voltage, changing frequency, and capacitance of the transistor. Area, delay, and energy dispersion have surfaced as the priceless problems for designers [1-5]. Being little assembling innovation in CMOS circuits enabled designers to consider CMOS as a strategy for success. There has been good progress, for example, with the leakage current and power utilization in CMOS circuits. Thus, it is critical that a revolution occurs in CMOS technology. CMOS technology, in view of today's conventional transistors, follows Moore's Law. Expanding transistors inside a chip is not acceptable in CMOS technology. However, a solution at the nanoscale level demonstrates the likelihood of changing Moore's Law: QCA innovation have violated Moore's Law by effectively replacing CMOS technology. QCA technology can produce circuits with faster speed and lower latency than CMOS technology. Recent advances in QCA have enabled the construction of diverse digital segments, for example, XOR gates with minimal occupation areas. The XOR gate has wide applications in digital circuit usage, for example, in code converters. The XOR gate is the primary segment for con-figuring code converters and is especially valuable in arithmetic operations, error detection, and correction circuits [6-8]. Several structures of code converters are being investigated by researchers [13-16]. We propose an ideal outline of a novel code converter that uses smaller area and a compact circuit. The purpose of our suggested configuration was to augment the circuit thickness and aim on a design that is reduced in its usage of cell numbers. Around that paper, we offer two unique achievements of QCA 4-bit binary-to-gray and 4-bit gray-to-binary code converters established on the XOR gates, and introduce simulation benefits of these unique creations. A depth assessment with respect to the separate characteristics of these types of forms is furthermore guided. The suggested QCA circuits were planned and simulated utilizing the QCADesigner appliance. On remainder of the paper is planned as accepts: the foundation of QCA innovation is discussed in Section 2. A brief introduction to binary-to-gray and gray-to-binary converters is given in Section 3, and Section 4 introduces the QCA implementation of a proposed circuit. Simulation results and comparison analyses are discussed in Section 5. Subsequently, this particular paper is actually determined as part of Section BACKGROUND QCA is a promising successor to CMOS technology. QCA offers the unique approach to the transistor worldview. QCA, projected by Lent et al., is a developing innovation that provides an imaginative method of processing on the nano-scale through keeping track of the place of a single electron. This innovation permits the execution concerning logic products utilizing quantum dots as an alternative of transistors or diodes. The fundamental component of QCA is the quantum cell. QCA is imagined as a coupled spot framework with four quantum specks at the edges of a rectangular construction. Quantum dots are nanostructures made through ordinary semiconductive components, for example, Si/SiO2 [7] editor@iaeme.com

3 Area Efficient Code Converters Based on Quantum-Dot Cellular Automata Quantum-dot Electron Quantum-dot A P = +1 ( Binary 1 ) Tunnel junction P = -1 ( Binary ) 0 B C M(A,B,C) (a) (d) Input = 1 (b) Output = 1 Input=1 Output= 0 Input=1 Output=0 Input = 1 Output = 0 (c) (f) (g) Figure 1 (a) QCA cells with two different polarizations, (b) 90 QCA wire, (c) 45 QCA wire, (d) Three-input majority gate, (f) robust inverter, and (g) simple inverter QCA achieves logic procedures, and the information stream occurs in the circuit by methods that use the Columbic connection of the electrons of neighboring cells. It is clear that the dots tend to be the locations wherein the demand can easily be restricted. That a couple of electrons have a tendency to reside antipodal places while a consequences of their particular shared electrostatic repulsive force. Nevertheless, they could adjust their opportunities inside cells causing a tunneling impact. This occurrence provides position after the potential boundary isolating the two quantum dots is minimal. However, a tunneling procedure inside or possibly out of a cell might become obstructed. Thus, two arrangements are conceivable, which and they can be utilized to encode binary data, as shown in Figure 1(a). Polarization (P), that signifies the dispersion type of electricity demand inside the four dots in each cell, is characterized by Eq. (1), [9] where ρi is the power demand depth at dot i. As a result of Coulombic repulsion, electrons lie upon the two opposites of the diagonals inside every cell [10-11]. = Considering the ρi values in Eq. (1), that it is actually determined which P can take exclusively the principles P =1 and P =-1, that describe the digital principles 1 as well as 0 correspondingly. These kinds of two states were utilized concerning encoding binary information. This produces electrostatic vitality to become reduced in the demand setting regarding the cells. This is the way the state propagates in a range of cells. In view of Coulombic connections around the cells, fundamental QCA appliances are able to produce [7-9]. As part of a QCA wire, the binary data moves starting input towards output due to the fact concerning the Coulombic connections amongst cells. The generation in a 90 QCA wire is appeared in Figure 1(b). A 45 QCA wire, as appeared in Figure 1 (c), is likewise conceivable where the generation of the binary signal switches between the two different polarizations +1 and -1. Majority gate and inverter are essential building parts of this technology. Three input majority gate is conventional majority gate and its equation is M(A,B,C) = AB+AC+BC. The function of the majority gate is to generate three inputs and eventually to get desired output. It is consisting of five QCA cells: three input cells (A, B and C), one output cell (M(A,B,C)) and one inside cell. It does become executed by five cells organized in a cross as illustrated in Figure 1(d) [5]. Any digital logic circuit is represented by logic AND or OR operation. If one of the inputs is set to polarization minus one, logic AND operation can be constructed in the (1) editor@iaeme.com

4 majority gate. Similarly, one of the inputs is set to polarization plus one, logic operation OR is constructed [20]. Another prevalent QCA gate is the NOT gate or the inverter. One development of a QCA inverter is shown in Figure 1(f). Another development of the NOT gate is appeared in Figure 1(g), where the information is change owing to the different polarizations that are misaligned between the touching corners of the cells [9-11]. Synchronization and control of data flow are provided by QCA clocking in order to supply energy to operate the QCA circuit because here is no outside source for that purpose. QCA clocking is accomplished by dealing with the possible boundaries around surrounding quantum dots. Controlling the possible barrier by increasing or decreasing permits full control of the limitation and polarization of the portable electrons after raising potential force elements to localize. Hence, definite polarization occurs when the lowered potential allows for the delocalizing of electrons and provides no definite cell polarization [17]. The cells can be assembled into four zones to have a similar electric field influence in accomplishing an appropriate clocking scheme. These four zones are as follows: A switch zone occurs after the tunneling boundaries are increased and the electrons are affected through that the Columbic charges regarding nearby areas. That the hold zone has an extreme tunneling boundary and also will not change the state, yet influences neighboring zones. The release and relax zones occur when the tunneling barrier is diminished; in this way, different zones will not be influenced by that zone, as appeared in Figure 2(a) [12]. These gates have unique capacities and applications. They are especially helpful in arithmetic operations and in mistake identification and modification circuits. XOR and XNOR gates are normally discovered like 2-input gates. Basically no multiple-input XOR/XNOR gates are generally accessible because they are specialized towards create alongside equipment [18]. The cellular design of the 3-input XOR gate [20] is demonstrated in Figure 2(b). The exclusive-or (XOR) executes the appropriate logic functioning, as shown in Eq. (2): AB+AB = A B. (2) Clocking field strength C Switch Hold Release Relax Clock phase A XOR 3 B (a) (b) Figure 2 (a) Clocking scheme, (b) QCA implementation of 3-input XOR gate [20] Notwithstanding logic gates are furthermore utilized as part of the outline for computerized circuits. Two-input XOR (exclusive OR), additionally recognized like exclusive disjunction, is a rational perform the fact that provides a significant output exclusively when whatever one of the two inputs, nevertheless certainly not both, are significant. This gate is vital because it is utilized as part of a considerable number of circuits. Two-input XNOR is actually a rational perform that provides a significant output when each inputs are maximum or minimum editor@iaeme.com

5 Area Efficient Code Converters Based on Quantum-Dot Cellular Automata 3. CODE CONVERTERS The enormous accessibility of codes for different corresponding components of data outcomes in the utilization of distinct codes by distinct schemes. In some cases it is required in order to make use of the result regarding one method as the input to different method. Code converters are circuits that change a code into another that is programmed in logic arrays and utilized as a part of many fields, for example, shielding data from outsiders and increasing information flexibility. It is also efficient in the field of security for devising and cracking codes. A code is fundamentally a symbolic representation of discrete data. In advanced gadgets, there exist different types of code such as binary code, binary coded decimal code, gray code [14]. B 1 B 2 B B 3 1 G 0 1 G 1 1 G 2 G D (a) S C B R Q A P Figure 3 Previous designs of code converters: (a) 4-bit binary-to-gray code converter by M. Shafi et al. [17], and (b) 4-bit gray-to-binary code converter by J. Reshi et al. [19] A standout amongst the most widely recognized codes is gray code that is non-weighted. In most codes, especially in binary code, there is a rapid switching of bits from one transition to another. However, in a gray code, there is a single bit change from LSB (a bit of the highest digit) to MSB (a bit of the lowest digit) while traversing between the logical sequences. This element is valuable in reducing the fast switching movement [15]. (b) editor@iaeme.com

6 Table 1 Trust table of 4-bit binary to 4-bit gray code converter. Inputs (4-bit binary code) Outputs (4-bit gray code) B 3 B 2 B 1 B 0 G 3 G 2 G 1 G Table 2 Trust table of 4-bit gray to 4-bit binary code converter. Inputs (4-bit gray code) Outputs (4-bit binary code) G 3 G 2 G 1 G 0 B 3 B 2 B 1 B editor@iaeme.com

7 Area Efficient Code Converters Based on Quantum-Dot Cellular Automata Gray code, furthermore called replicated binary code, conveys each of their beliefs like a sequence of 1 s and 0 s. Unlike binary code, every appeal varies starting the last one by just a single bit. This one offers numerous functional solutions, especially when several simultaneous little modifications happen in mistakes. Gray codes do own any kind of quantity of bits, as well as new gray codes do obtained starting binary codes which have one bit fewer compared to the suggested gray code. Gray codes are broadly applied to enhance mistake correction in computerized connection, for example, in digital terrestrial TV set systems [16]. There are a few 4-bit binary-to-gray and gray-to-binary converters that have been explored by researchers. Table 1 is a truth table for a 4-bit binary-to-gray code converter. To obtain an efficient outcome, in all beforehand structures are required many gates, areas, and delays. For example, A. Shafi et al. [17] in 2016 offered another outline of a 4-bit binary-togray converter, which utilized six inverters, six AND gates and three OR gates. The logical plan for this converter has been appeared in Figure 3(a). This layout is composed of 126 quantum cell and utilizing 3 clock phases. The structure has an area of 0.15 µm 2. In this plan, a single layer wire crossing that depends on QCA timing is utilized. One example of a 4-bit gray-to-binary converter was introduced in 2016 by J. Reshi et al. [19]. The trust table of a 4-bit gray to 4-bit binary code converter is shown in Table 2. This converter is comprised of seven inverters, six AND gates and three OR gates. This converter utilizes 175 quantum cells and three clock phases are required to actualize the capacity of the 4-bit grayto-binary converter. The total occupied area of the circuit is µm 2. The cellular design of this converter has been appeared in Figure 3(b). 4. PROPOSED WORK bit binary-to-gray code converter This code converter combinational circuit is intended to convert binary to gray code. A binaryto-gray converter changes a binary code to its corresponding gray code. Such as a binary code, gray code is additionally indicated in sequences of 0 s and 1 s. Gray code discovers their purposes in cryptography and electronic communicating techniques. The input code of the code converter is binary and output code of code converter is gray code. A binary code (B3, B2, B1, B0) can be changed into gray code (G3, G2, G1, G0) as in Eq. (3). The logic circuit and QCA design of the suggested circuit are demonstrated in Figure 4. The simulation result of the 4-bit binary-to-gray code converter is appeared in Figure 5. Three XOR gates are actually needed in order to produce 4-bit output gray code. The proposed circuit is composed of only three XOR gate. This design comprises 58 quantum cells and utilizes two clock phases. The structure is 0.04 µm2 with low complexity. In this design, a single layer wire crossing that depends on QCA timing is utilized. This can lead to a smaller circuit and application of the design to complex circuit architectures is suitable. In addition, the proposed structure is appropriately designed to connect to different circuits. The simulation results were obtained from the QCADesigner tool, as mentioned earlier. The simulation results are similar to the results acquired coming from the truth table, which shows the logic function of the 4-bit binary-to-gray code converter as illustrated in Figure 7. G 0=B 0 B 1, G 1= B 1 B 2, G 2=B 2 B 3, G 3=B 3. (3) editor@iaeme.com

8 B 3 G 3 B 3 G 3 2-input XOR G 2 G 2 B 2 B 2 2-input XOR G 1 G 1 B 1 B 1 2-input XOR G 0 G 0 B 0 B 0 (a) (b) Figure 4 Logic circuit and QCA implementation of 4-bit binary-to-gray code converter. Figure 5 Simulation result of 4-bit binary-to-gray code converter bit gray-to-binary code converter In this paper, we additionally suggest a QCA circuit in view of the 4-bit gray code to 4-bit binary code. We want the processed data back in a binary representation. Thus, we need a converter that performs a reverse operation to that of the earlier converter. We call this a grayto-binary converter. The conditions of the outputs of the binary code are as in Eq. (4). In a grayto-binary code converter, the input is actually a multiplies gray code and the output is its comparable binary code. The transformation process of gray to binary code also needs an XOR gate. However, in this specific case, bits of gray code are XOR'ed alongside output binary code bits. The logical circuit and QCA outline of this structure have appeared in Figure 6(a) and Figure 6(b), correspondingly. The simulation outcomes of the recommended structure have editor@iaeme.com

9 Area Efficient Code Converters Based on Quantum-Dot Cellular Automata appeared in Figure 7. For a 4 bit gray-to-binary code converter, we consider the input vector I (G0, G1, G2, G3) and an output vector O(B0, B1, B2, B3). The input and output vectors are related with the following equations: B 0=B 1 G 0, B 1=B 2 G 1, B 2= G 3 G 2, B 3=G 3. (4) G3 B3 G3 B3 2-input XOR B2 B2 G2 2-input XOR B1 G2 B1 G1 2-input XOR B0 B0 G0 G1 G0 (a) (b) Figure 6 Logic circuit and QCA implementation of 4-bit gray-to-binary code converter. Figure 7 Simulation result of 4-bit gray-to-binary code converter. Using an efficient XOR gate, the 4-bit gray-to-binary code converter was created. Three XOR gates are involved to establish 4-bit output binary code. The XOR gate is definitely one of the more significant gates in QCA innovation. In addition, XOR gates are the basic elements of all code converters. A 3-input XOR gate is commonly supposed operating 2-input XOR gates. In this technique, the QCA execution of a 2-input XOR gate offers an important role in circuit efficiency. Consequently, we used efficient 2-input XOR gates for our proposed circuit. This results in a compact 4-bit gray-to-binary code converter circuit that is more effective than prior works. It is clearly seen in Figure 4 and Figure 6 that the propose circuits have lower cell count and smaller areas. Furthermore, the simulation result of circuits is stronger, more stable, and similar to the result acquired through the truth table that shows the editor@iaeme.com

10 logic function of code converters. This means that the simulation results for the circuits are correct. The QCA layout of the 4 bit gray-to-binary code converter is demonstrated in Figure 6. The design requires 93 cells and consumes an area of 0.12 µm 2. The proposed circuit considerably alleviates the abovementioned challenges and difficulties. The proposed circuits are the most crucial components of a processor because they are mostly used in the arithmetic logic unit. The simulation results and a variety of details indicate just that these layouts are furthermore region effective, and the quantity of crossovers has been decreased in the layouts. Owing to the lowest quantity of wire crossings these layouts exhibit improve efficiency. The 4-bit binary-to-gray code converter and 4-bit gray-to-binary code converter routine are implemented alongside an efficient pattern of the XOR gate. It is obviously obvious which this strategy could be basic and fine-tuned contrasted with prior layouts in terms and conditions of cell counts, area, and complexity. 5. COMPPARISON AND ANALYSIS Around this part, the suggested layout is contrasted alongside preceding established operates. A comparative analysis between various types of QCA design layouts of 4-bit binary-to-gray code converters and 4-bit gray-to-binary code converters is demonstrated in Table 3. The comparison is based on effective area, delay, and the quantity involving QCA cells utilized, and indicates that the proposed circuit-based 4-bit binary-to-gray code converter and 4-bit gray-to-binary converters are more effective than prior designs in every aspect. From the study, that it is clearly noticed that the suggested models contain considerably fewer cells. Our 4-bit binary-to-gray code converter s cell count is 35% less than the least costly best model, [19] and the area of the proposed 4-bit binary-to-gray code converter is 70% less than the most compact previous one [21]. 4-bit binary-to-gray code converter 4-bit gray-to-binary code converter Table 3 Comparison results for code converters. Circuit Cell count Area(µm 2 ) Latency [13] [14] [15] [16] [19] [21] Proposed [13] [14] [15] [16] [19] Proposed As demonstrated in Table 3, the offered design in Figure 8 does really well over all its alternatives among substantial supremacy. The cell count and circuit latency of the proposed of 4-bit gray-to- binary code converter architecture are 6% and 50% less than those of [16], respectively. It is clear from the bar graph (Figure 8) and Table 3 that compared with ordinary designs, the proposed converter configuration has a compact location and excellent efficiency with editor@iaeme.com

11 Area Efficient Code Converters Based on Quantum-Dot Cellular Automata value to area and circuit dependability. For input/output synchronization, the proposed circuit is straightforward. The simulation results (Figure 5 and Figure 7) demonstrate that the performances of the new designs are better than those of conventional designs. The overall outcomes reveal that the suggested designs are more efficient than prior works Number of cells Number of cells (a) (b) Figure 10 Bar graph of cell count for: (a) 4-bit binary-to-gray code converter, (b) 4-bit gray-tobinary code converter 6. CONCLUSION A novel viable structure concerning developing a QCA circuit was introduced in detail. An outline and simulation of a 4-bit binary-to-gray code converter and a 4-bit gray-to-binary code converter were conducted utilizing the QCADesigner tool. The usefulness of these two circuits was verified. The proposed configuration significantly decreases the quantity of cells and uses a more compact region in compare through previous designs. Utilizing an effective XOR gate, code converters were designed. The simulation results and distinctive parameters demonstrate which these types of models are region productive, and the quantity of crossovers was decreased in the layouts. Moreover, the simulation results indicate that the proposed circuits perform well. The supposed QCA-depending combinational code converter circuit could be utilized in order to portray exclusively four input levels and to create only four output amounts. The designs are effective because they contain fewer cells, use fewer clock phases, and have a significantly smaller maximum wire length. These circuits can be useful in quantum computing, digital signal processing, and nanotechnology. ACKNOWLEDGEMENTS This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(msip) (NO. NRF-2017R1D1A3B ). REFERENCES [1] Lent, C. S., Tougaw, P. D., Porod, W. and Bernstein, G. H. Quantum Cellular Automata, Journal of Nanotechnology, 4(1), 1993, pp [2] Walus, K., Dysart, T. J., Jullien, G. A. and Budiman, R. A. QCADesigner: A Rapid Design and Simulation Tool For Quantum-Dot Cellular Automata, IEEE Transactions on Nanotechnology, 3(1), 2004, pp [3] Jeon, J. C. Fundamental Two-Party Quantum Secret Sharing Protocol without Quantum Entanglement, International Journal of Security and Its Applications, 9(8), 2015, pp [4] Tougaw, P. D. and Lent, C. S. Logical devices implemented using quantum cellular automata. Journal of Applied Physics, 75(3), 1994, pp editor@iaeme.com

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