A NOVEL QUANTUM-DOT CELLULAR AUTOMATA FOR PARITY BIT GENERATOR AND PARITY CHECKER

Transcription

1 A NOVEL QUANTUM-DOT CELLULAR AUTOMATA FOR PARITY BIT GENERATOR AND PARITY CHECKER NANDINI RAO G¹, DR.P.C SRIKANTH², DR.PREETA SHARAN³ ¹Post Graduate Student, Department of Electronics and Communication,MCE,Hassan, Karnataka ²Professor and HOD, Department of Electronics and Communication,MCE,Hassan,Karnataka, ³Professor,Department of Electronics and Communication, TOCE, Bengaluru, Karnataka, Abstract Quantum-dot cellular automata (QCA) is a potentially attractive and novel technology in nanometer scale and a possible alternative for complementary metal oxide semiconductor. QCA technology has great potential in terms of high space density and power dissipation with the development of the high speed computer with low power consumption. This paper presents an efficient design and layout of parity bit generator and checker based on quantum-dot cellular automata using QCADesigner tool. Main aim is to provide evidence that QCA finds potential applications in future computers provided that the underlying technology is made much feasible. The novel design provides the superior performance factors with respect to area, latency, circuit stability and low power dissipation. The paper provides a number of new results on parity bit generator,and parity checker and detailed simulation using QCAD designer tool is presented. Index terms Parity bit generator Quantum-dot cellular automata, QCAD tool. I.INTRODUCTION Trusting on the unique properties of electronic devices at feature size of nano level, nanotechnology unlocks new prospects for computing systems and devices. QCA proposed by Lent [1], is an emerging technology that offers an innovative approach for computing at nano-scale by monitoring the position of a single electron. Quantum cell is the basic element of QCA[2]. Each quantum cell has electrons in them, where electron transmission occurs due to the columbic interaction of electrons[3]-[5].qca is an advanced research program and great efforts are made here to reduce the complexity of the circuits. QCA structures are designed as an array of quantum cells where every cell has electrons in them and electrostatic interaction with its neighboring cells take place[6]. QCA uses a new technique for computation. It uses polarization effect rather than conventional current or charge flow for the transmission of digital information[7],[8]. Thus a cell is responsible for the transfer of information throughout the circuit. II. QCA DESIGNER QCA logic and circuit designers require a rapid and accurate simulation and design layout tool to determine the functionality of QCA circuits. QCADesigner gives the designer with the ability to quickly layout a QCA design by providing an extensive set of CAD tools[9]. As well, several simulation engines facilitate rapid and accurate simulation. It is the first publicly available design and simulation tool for QCA. It was developed at the ATIPS Laboratory, University of Calgary[10]. QCADesigner currently supports three different simulation engines, and many CAD features required for complex circuit design. III.QCA ARCHITECTURE A. Basics of QCA: The basic element of QCA are QCA cell and the basic operators are majority gate and invertor. In QCA each quantum cell has four quantum dots and two free electrons. The location of the electrons determine the binary states. These two arrangements are denoted as cell polarizations P=+1 and P= -1. Here we use cell polarization P =+1 to represent logic 1 and P =-1 to represent logic 0. Binary information is encoded in the charge configuration of the QCA cell. 107

2 layer of cells analogous to multiple metal layers in a conventional IC. Fig.1.QCA cell polarization B.QCA cell: A quantum-dot cellular automata (QCA) is a square nanostructure of electron wells with free electrons. Each cell has four quantum dots [5]. The four dots are located in the four corners. The cell can be charged with two free electrons. By using the clocking mechanism, the electrons tunnel to proper location during the clock transition. The arrangement below gives the realization of majority gate using QCA. QCA cells A, B and C are input cells, and M is the output cell that is polarized depending on the polarization of the majority of the input cells. In this example, since two (out of three) input QCA cells are polarized to +1, the output cell is also polarized to +1. QCA cells can also be used to construct wires. When an input is applied to the left input cell, the binary information propagates from the left to the right[11]. When all cells in a wire settle down to their ground states, they have the same polarization. Fig. 2. Inverter Fig. 3. Majority gate C.Clocking The QCA circuits require a clock, not just to synchronize and control information flow but also to provide the power to run the circuit since there is no external source for powering the cells. With the use of four phase clocking scheme in controlling cells, QCA processes and forwards information within cells in a well arranged timing scheme[7]. Cells are grouped into zones so that the field influencing all the cells in the zones will be the same. A zone cycles through 4 phases. Fig. 4. QCA clock zones and QCA clock with four phases. In the switch phase electron tunneling is stopped as the tunnel barrier between the quantum dots rise and due to the polarization of its input the electron in the cell becomes localized. Switching occurs by refreshing the state. During the hold phase the barrier remains high, no electron tunneling takesplace. The polarized cells are latched. During Release phase the electrons become free and the cell starts to lose its polarization due to the lowering of electron barrier. In the relax phase, the barriers are low, the electrons are free to tunnel and delocalize themselves and the cells have no polarization i.e P=0. Thus to control data flow four identical clock signals shifted in phase by 90 degree will be applied to adjacent groups of cells. D.QCA implementation: The AND and OR gates are realized by fixing the polarization of one of the 3 inputs of a majority gate to either P = 1 (logic 0 ) or P = 1 (logic 1 )[9]. A QCA design provides two options for crossover, coplanar crossover and multilayer crossover. The coplanar crossover uses a single layer but involves usage of two cell types (regular and rotated), the multilayer crossover uses more than one 108

3 extra bit used along with binary message to make the total number of 1 s in the message (including parity bit) either odd or even. Including parity bit, message is transmitted and checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The design layout that generates parity bit at the transmission node is called a parity bit generator and the design layout that checks the parity at the receiver side is called as parity checker. In this proposed design, we considered a three bit message to be transmitted with an even parity bit. The truth table and logic diagram are as shown below. Fig.5.Layouts of AND gate and OR gate IV.IMPLEMENTATION OF PARITY GENERATOR AND PARITY CHECKER: The basic gates like and, or, not and the universal gates nand and nor are required to design digital logic circuits. In addition to these gates exclusive-or (xor) and Exclusive-nor (xnor) gates are also used to design digital circuits. The xor and xnor gates are particularly useful in arithmetic operations as well as error-detection and correction circuits during data transmission. The basic parity bit generator is the XOR gate. The logic operation of XOR gate is given by Out = ab + ba. message Even parity bit A B C P Table I.Truth table of parity bit generator Fig.7. Logic diagram of parity generator Fig.6.a.XOR gate graphical symbol and b.circuit diagram An XOR gate can be trivially constructed from the basic AND, OR and NOT gates. Exclusive-OR circuits are convenient in design of parity bit generator for error-detection. Mainly parity bit is used for detecting errors during transmission of binary information. A parity bit is an The design layout of even parity generator is shown in Fig.8.a, it is implemented by 2 XOR gates and consists of only 51 number of cells and the circuit area is found to be 16524nm 2. Latency of the proposed design layout is 1 clock cycle and the parity bit P generates after one clock interval from the input vectors. Parity generator reported in [13] has 99 no of cells count as compared to proposed implementation with same latency. Thus, the proposed design is simple in implementation, uses lesser number of cell counts, less area usage thereby less power dissipation. 109

4 Fig.9.a. QCA implementation of parity checker and b.simulation result Fig. 8.a.QCA Layout of even parity bit generator and b.simulation result At the receiver side we use parity checker for error detection in the received bit stream. The QCA layout and simulation results for parity checker circuit is shown below. V.COMPARATIVE STUDY OF PROPOSED DESIGN WITH SOME RECENT DESIGN LAYOUTS In this paper we have designed a parity bit generator and checker to enable error detection during data transfer using a novel XOR circuit. The novelty of this design besides the parameters like area, usage efficiency, delay and complexity in terms of number of cells is minimal compared to some recent designs. A comparative study of various parameters of proposed design is performed. Among these proposed design provides minimal complexity and better efficiency. As in[13] As in 12] Proposed design No. of cells Area (nm 2 ) % of usage delay :Parity bit generator :Parity checker Table. II. Comparative study of proposed design with some most recent design layouts VI.CONCLUSION: We have considered primitives in QCA and have presented an efficient QCA design for a parity bit generator and checker. The paper provides the design, QCA layout and simulation results of parity bit generator and checker using novel XOR circuit. 110

5 The proposed design of circuits is implemented and simulated using QCA simulation tools i.e. QCA Designer. The proposed design is found to be efficient in terms of cell count, area usage and clocking. Main advantage is, it requires a small simulation time and device execution time. Using quantum-dot we can achieve miniaturization and high speed processing. REFERENCES [1]. Kunal Das and Debashis De, Characterization, Test and Logic Synthesis of Novel conservative and Reversible Logic Gates for QCA, International Journal of Nanoscience, Vol. 9, No. 3, , [2]. Pallavi A.N, Moorthy Muthukrishnan, Implementation of Code Converters in QCAD,IJSRD, Vol. 2, Issue 06, 2014 [3]. M.Mustafa, M.R Beigh, Indian Journal of pure and applied physics, Vol. 51,PP 60-66,2013 [4]. Bibhash Sen,Ayush Rajoria, Biplab K Sikdar, Design of efficient full adder in Quantum dot cellular automata, The Scientific World Journal,vol.2013, article ID [5]. Lent C.S, Tougaw P.D, Porod W.D, and Bernstein G.H, Quantum cellular automata, Nanotechnology,vol.4, No.1,, pp.49 57, [6]. Bahram Dehghan, Ali Asghar Baziar, Optimized Methodology for Realization of Logic Circuits using QCA Gates,IJARCSSE,vol 3,march 2013 [7]. Kodam. Latha,M. Nanda Maharshi, Design of adders using qca,ijaet, Vol.6, Issue 4, pp ,2013 [8]. Namit Gupta, Shantanu Shrivastava, Nilesh Patidar, Sumant Katiyal, Choudhary K K., Design of One Bit Arithmetic Logic Unit (ALU) in QCA, International Journal of Computer Applications in Engineering Sciences,2012 [9]. S.Karthigai Lakhmi, G.Athisha, International Journal for Computer Application,Vol.3, No-5, June [10]. K.Walus, G.Jullien, Design tools for an emerging soc technology: Quantum-dot cellular automata,ieee proceedings,94(6),pp ,June 2006 [11]. Kyosun Kim, Kaijie Wu, and Ramesh Karri, The Robust QCA Adder Designs Using Composable QCA Building Blocks, IEEE transactions on computer-aided design of integrated circuits and systems, vol. 26, no. 1, pp , [12]. Santanu Santra, Utpal Roy, Design and Optimization of Parity Generator an Parity checker Based On Quantum-dot CellularAutomata, World Academy of Science, Engineering and Technology International Journal of Computer, Information, Systems and Control Engineering Vol:8 No:3, 2014 [13]. A.Anjana, Even and odd parity generator and checker using reversible logic gates,international journal of comuter science and engineering communications-ijcsec.vol.1 Issue.1,December