TIME EFFICIENT PARITY GENERATOR BASED ON QUANTUM-DOT CELLULAR AUTOMATA

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1 International Journal of Civil Engineering and Technology (IJCIET) Volume 10, Issue 02, February 2019, pp , Article ID: IJCIET_10_02_069 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed TIME EFFICIENT PARITY GENERATOR BASED ON QUANTUM-DOT CELLULAR AUTOMATA Department of Computer Engineering, Kumoh National Institute of Technology, Gumi, Gyeongbuk, South Korea. ABSTRACT A parity generator is a circuit that generates redundant bits used for error detection and is used when transmitting binary information. Previous parity generator circuits based on quantum-dot cellular automata (QCA) are designed to reduce the area of the circuit. Input cells of existing circuit are designed inside the circuit and the circuit s signal is not propagated properly due to the influence between adjacent wires. In addition, existing circuits consume many clocks because the XOR gate, which is an essential component of the parity generator circuit, consumes many clocks. In order to solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast operation. The proposed circuit uses an XOR gate that can operate one clock faster than the existing XOR gate to reduce the clock, and by extending this XOR gate, the output value can be obtained faster than the conventional circuit. In the proposed circuit, the result is verified through simulation and the performance is compared with the existing circuit. Key words: Nanotechnology, quantum-dot cellular automata, 3-bit parity generator, XOR gate. Cite this Article:, Time Efficient Parity Generator Based on Quantum- Dot Cellular Automata, International Journal of Civil Engineering and Technology, 10(02), 2019, pp INTRODUCTION Since the introduction of Moore's Law, the degree of integration in semiconductor chips in VLSI has increased nearly twice a year [1], but with the physical limitations of CMOS technology, the need for new alternatives is increasing [2]. Quantum-dot cellular automata (QCA) is a new technology that performs various computations using cells based on nanoscale quantum dots and solves existing limitations [3, 4]. QCA is based on encoding binary information in the charge configuration within quantum dot cells. Since the first introduction editor@iaeme.com

2 by Lent et al., Basic combination and sequential logic circuits have been designed using the basic characteristics of QCA and the clocking technique [5]. An XOR gate in the logic gate is used for error detection and can be extended to the parity bit circuit and is one of the important circuits used for all adders. XOR gates designed in QCA are designed in various ways, including various planar structures, multilayer structures, and universal gates. Among them, the universal gate is a gate that can replace all other basic logic gates by itself, and there are NAND gates and NOR gates representatively [6]. Therefore, in this paper, we propose a new type of QCA universal gate, not a universal gate using majority gate, and design XOR gate used for error detection. The parity generator is used to detect errors that occur when transmitting binary information or exchanging large amounts of information. An extra error detection bit is added and transmitted, and the bit used at this time is referred to as a parity bit. The parity bits are used for the even parity detection method and the odd parity detection method and it is checked whether the number of 1s of the bit information is an even number or an odd number to check whether there is an error. The existing parity generator proposed in the QCA reduces the area of the circuit by designing the input cells in the circuit and connecting the lines in both directions. This structure is efficient in a single structure, but the scalability of the circuit is low. Also, due to the reduced area, the influence between adjacent wirings may be large and signal noise may be generated. In addition, since the XOR gate, which is an essential component of the parity generator, consumes a lot of clock, the clock consumed by the entire circuit increases. In this paper, we design an even parity generator based on XOR gate consuming small clocks in QCA and compare and analyze with existing circuit. We propose a circuit that eliminates the noise of the simulation result that occurred in the existing research and can expand and perform fast operation. The proposed circuit also measures the strength of the signal through simulation and verifies the superiority of the circuit. This paper is divided 5 parts and explained our work. A background research of basic QCA technology, circuits of previous an XOR gates and parity bit generators are described in in section 2. And the design and implementation of proposed XOR gate and 3-bit parity bit generator are explained in section 3. In next section 4, we analyzed and compared with previous circuits. In last section, we made conclusions. 2. BACKGROUND 2.1. QCA Overview QCA circuit composes of quantum cells which consist of four quantum dots. Each cell contains two electrons and the electrons switch position diagonally due to coulomb repulsion [7, 8]. Figure 1 shows the design of the four types of QCA inverters. The inverter can be operated where the cell is only at the corners. The signal on the wire is inverted due to wave interaction. Figure 1(a) inverter is robust inverter and its information is propagated with strong signal [9, 10]. Second inverter is a simple inverter. Its cell is located diagonally each other but has weaker signal than other inverters. Third inverter is used 45 degree cell and last inverter is used the middle of position of wire and make inverter signal editor@iaeme.com

3 Time Efficient Parity Generator Based on Quantum-Dot Cellular Automata Figure 1 Various Types of Inverter Gate: (a) Robust inverter, (b) Simplest inverter, (c) Inverter using 45 degrees rotated cells, and (d) Inverter using three cells Figure 2 QCA 3-input Majority Gates: (a) when two inputs are 1and (b) when two inputs are 0 A majority gate is one of basic building blocks in QCA. Two layouts of a QCA majority gate are shown in Figure 2. A majority gate has three inputs and one output. The output is decided by the majority of the three input values [11]. Figure 2(a) shows a majority gate with output with 1 and the figure shows an output of 0. The polarization of one input cell fix to 0 or 1, then the gate will be as an AND or OR gate [12]. Figure 3 QCA Wire Crossing Using Multilayer Structure Two types of QCA wire-crossing are coplanar and multilayer as shown in Figure 3. In QCA structure, coplanar cross wire need cells with different shape, as a standard cell and rotated cell editor@iaeme.com

4 In multilayer cross wire structure has no rule about cells. It is believed that a single layer design with QCA is possible to date because it can generate a single layer crossover. However, the same plane intersection requires the use of two kinds of cells, normal cells and rotating cells. Since normal cells and rotated cells do not interact when properly aligned, rotated cells can be used at the intersection of coplanar lines. There is a possibility of loose coupling of signals causing discontinuity of signal radio waves at the same plane intersection; there is a possibility of back propagation from constant input at long distance. Therefore, you need to place enough clock regions between common cells of rotated cells. Therefore, the coplanar intersection of complex cells based on two cells is very likely to fail [13]. Also, crossover is very sensitive to manufacturing errors and depends on the ability to manufacture two types of QCA cells. Therefore, a solution to this problem is presented. Multi-layer crossover uses multiple layers of cells like multiple metal layers. On the other hand, it is highly intuitive from the viewpoint of multilayer crossover design, and is more reliable than signal connection. [14, 15] QCA Clocking System Since the QCA circuit requires a clock, there is no external source to supply power to the quantum cell, as well as synchronizing and controlling the flow of information, so it is also possible to supply power to operate the circuit There [16, 17]. QCA timing/synchronization is accomplished with four different periodic phase cascade clocks, as shown in Figure 4[18]. In the first (switch), the tunneling barrier between the two points of the QCA cell starts to rise. [18]. In the first (switch) the tunneling barrier between the two points of the QCA cell begins to rise. This is the stage where the calculation takes place. If the tunneling barrier is high enough to prevent tunneling, the second (retentive) step is reached. Since the barrier at the stage of the third (release) is high, it lowers to low. The last step (relaxation) has no dot barrier, so that the cell does not maintain polarity. Each cell must pass all of these clocking steps [19]. Figure 4 QCA Clock Phases within Clock Zones 2.3. QCA XOR Gate Exclusive-OR (XOR) can be used in error detection and cryptography encryption [20]. A block diagram of proposed XOR gate is shown in Figure 5. The diagram is consisted of AND gate, three OR gates, and four inverter gates. Figure 6 shows the existing QCA XOR gate. Figure 6(a) is proposed by S. Santra and U. Roy and has a small area advantage [21]. However, input cells X and Y are located inside the circuit, making it difficult to connect the input wiring from the previous circuit editor@iaeme.com

5 Time Efficient Parity Generator Based on Quantum-Dot Cellular Automata Figure 5 Block diagram of proposed QCA XOR gate X Y F - - Figure 6 Previous QCA XOR Gates: (a) proposed by S. Santra [21] and (b) proposed by P. Ilanchezhian [22] Extensibility and connectivity are very important because XOR gates are used especially as components of various circuits. This circuit has drawbacks of connectivity and is inefficient because additional wiring to the input cells must be added. Figure 6(b) shows the results of P. Ilanchezhian and R.M.S [22]. It is proposed by Parvathi and is characterized by a multi-layer structure. It is designed based on the basic diagram of XOR gate, and it is composed of three layers in total by designing the wiring intersection with multi-layer structure. Although this circuit considers scalability, it is not suitable for use as a component of other circuits because it has the disadvantage of large area of the whole circuit QCA Parity Bit Generator A parity generator transmits one extra error detection bit when transmitting binary information. In the case of an even parity, the number of 1s in a message including a parity bit is an even number, and in the case of an odd parity, the number of 1s is an odd number. Figure 7 is a block diagram of a 3-input odd parity generator. It is designed using three inputs and two XOR gates. Table 1 shows the truth tables of odd parity generators. Figure 7 Block Diagram of 3-Bit Parity Bit Generator Circuit editor@iaeme.com

6 Table 1 Truth Table of 3-Bit Parity Bit Generator Input Output X Y Z P Figure 8 Santra s QCA 3-Bit Parity Bit Generator [21] Figure 9 Ilanchezhian s QCA 3-Bit Parity Bit Generator [22] Among the three inputs, X and Y are first operated through the XOR gate, and the output value is operated to generate a parity bit. In Table 1, it can be seen that the number of 1 is odd if X, Y, and Z want to transmit a message, for example, P, which is generated parity bit. The 3-bit parity bit generator circuit proposed by Santra et al. and is shown in Figure 8 [21]. It is designed by connecting two XOR gates of Figure 6(a), and has advantages of small cell area and small area. Since it consumes 8 clocks in total and the input cell is located inside the cell, it is difficult to connect two inputs at the same time. In addition, it is difficult to design an efficient design because additional wiring is required. The 3-bit parity bit generator circuit proposed by Ilanchezhian et al. and is shown in Figure 9 [22]. It is designed by connecting two XOR gates of Figure 6(b) and it consumes a total of editor@iaeme.com

7 Time Efficient Parity Generator Based on Quantum-Dot Cellular Automata clocks with many cells. It is designed in a multi-layered structure and consists of three layers. In order to consider the scalability, the positions of the input and output cells are located outside the circuit and the signal is designed to flow in one direction. However, if the number of bits increases because of consuming a lot of cells and area, it may be difficult to design a circuit. Simulation results also show that many noise and error values are found in the circuit. Because the signal was not propagated correctly through the multilayer structure, we could see noise and error. 3. BINARY TO GRAY CODE CONVERTER Figure 10 shows the proposed QCA XOR gate. We designed a NAND gate with two inputs using a new type of universal gate and reduced the area and clock of the circuit by using a small area inverter. The clock of the whole circuit is three clocks, and it is possible to operate faster than the conventional circuit. In the next section, the parity generator circuit designed based on the existing XOR gate is analyzed and the performance of the parity generator circuit designed with the proposed XOR gate is verified. Figure 10 Proposed QCA XOR Gate X - Y Z - P Figure 11 Proposed 3-Bit Parity Bit Generator The proposed 3-bit parity bit generator circuit is designed by connecting two XOR gates of Figure 10 and is shown in Figure 11. Since the proposed circuit is designed with two XOR gates with three clocks, it consumes a total of 6 clocks, and no additional wiring is needed for wiring between circuits. It also has the advantage of being able to extend the circuit as the number of bits increases as it is designed with a small footprint. In Figure 11, the simulated results of the proposed circuit are shown and performed with the QCADesigner tool. For inputs X and Y, the input is on the first clock, but for input Z the input is delivered on the fourth clock editor@iaeme.com

8 Inputs come from different clocks, but there is no need to synchronize the clocks, and there is no additional clock, so fast operation is possible. 4. COMPARISONS Table 2 shows the performance comparison between the existing QCA parity bit generator circuit and the proposed circuit. In the case of the circuit in Figure 8, the cell and area are the best. However, it consumes 8 clocks and has a disadvantage of low scalability. Also, as additional wiring and clocks are needed, more cells and clocks can be consumed when the circuit is further expanded. The circuit in Figure 9 consumes a lot of cells, area, and clock, especially the circuit is not stable and the correct result is not output. The proposed circuit shows lower performance than the Figure 11 in the cell and area, but it can reduce the total 2 clocks and enable faster operation. In addition, the position of the input cell is located on the left side of the circuit, and the position of the output cell is located on the right side of the circuit, making circuit connection and expansion easy. Because the correct result is output and the fast operation is possible, it is possible to design efficiently when it is used as a component of other circuit. Table 2 Comparison of 3-Bit Parity Bit Generator Circuits Circuit Circuit in [21] Circuit in [22] Proposed Circuit Cell count Circuit area (nm ) Clock Scalability Stability 60 83,552 8 Low High ,484 8 High Low ,920 6 High High 5. CONCLUSION In this paper, we designed a QCA 3-bit parity bit generator with fast operation and verified its performance by comparing and analyzing with existing circuits. The proposed circuit is scalable by adjusting the position of the input and output cells and is suitable for use as a component of other circuits. In addition, the stability of the circuit is high and the correct result is output. It has two clocks less than the conventional circuit, and has the advantage that it can be operated directly without the need for clock synchronization of three inputs. Based on this research, we will design a new type of XOR gate that further reduces the cell and area of the circuit, and design the detector circuit as well as the parity bit generator. ACKNOWLEDGEMENTS This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (NO. NRF-2017R1D1A3B ). REFERENCES [1] Moore, G. E. The Microprocessor: Engine of the Technology Revolution, Communications of the ACM, 40(112), 1997, pp [2] Isaac, R. D. The future of CMOS technology, IBM Journal of Research and Development, 44(3), 2000, pp [3] Pagiamtzis, K. and Sheikholeslami, A. Content Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey, IEEE Journal of Solid-State Circuits, 41(3), 2006, pp editor@iaeme.com

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