IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6, JUNE Adder and Multiplier Design in Quantum-Dot Cellular Automata

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1 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6, JUNE Adder and Multiplier Design in Quantum-Dot Cellular Automata Heumpil Cho, Member, IEEE, and Earl E. Swartzlander, Jr., Fellow, IEEE Abstract Quantum-dot cellular automata (QCA) is an emerging nanotechnology, with the potential for faster speed, smaller size, and lower power consumption than transistor-based technology. Quantum-dot cellular automata has a simple cell as the basic element. The cell is used as a building block to construct gates and wires. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. That work demonstrated that the design trade-offs are very different in QCA. This paper utilizes the unique QCA characteristics to design a carry flow adder that is fast and efficient. Simulations indicate very attractive performance (i.e., complexity, area, and delay). This paper also explores the design of serial parallel multipliers. A serial parallel multiplier is designed and simulated with several different operand sizes. Index Terms Adder, multiplier, carry flow adder, carry delay multiplier, quantum-dot cellular automata (QCA). Ç 1 INTRODUCTION CURRENT transistor-based semiconductor devices are becoming resistent to scaling. Due to the decreasing supply voltage, the power consumption from leakage current is a big challenge for transistor circuits. Nanotechnology is a possible alternative to these problems and the ITRS report [1] summarizes several possible technology solutions. Quantum-dot cellular automata (QCA) is an interesting possibility. Since QCAs were introduced in 1993 [2], several experimental devices have been developed [3], [4], [5], [6], [7]. Although they are certainly not ready for prime time, recent papers show that QCAs may eventually achieve high density [8], fast switching speed [9], and room temperature operation [5], [10]. The development of SPICE modeling and verification for QCA [11] indicate continuing interest. Recently several molecular QCA models, implementations, and power analysis have been proposed [12], [13]. Adders are fundamental circuits for most digital systems and several adder designs in QCA have been proposed [14], [15], [16], [17], [18], [19] and a performance comparison was presented [16]. Better adder performance depends on minimizing the carry propagation delay. A wide variety of (often complex) techniques have been used for transistor adder circuits. Conventional adder circuits frequently require many wires which are relatively difficult to realize (and may be slow) in QCA technology. Due to these wire delays, most previous adder designs are limited in speed. This paper presents a new adder design, the carry flow adder that is. H. Cho is with Qualcomm, Incorporated, 5775 Morehouse Drive, San Diego, CA hpcho@qualcomm.com.. E.E. Swartzlander, Jr. is with the Department of Electrical and Computer Engineering, the University of Texas at Austin, 1 University Station C0803, Austin, TX Eswartzla@aol.com. Manuscript received 20 June 2008; revised 12 Nov. 2008; accepted 18 Dec. 2008; published online 15 Jan Recommended for acceptance by F. Lombardi. For information on obtaining reprints of this article, please send to: tc@computer.org, and reference IEEECS Log Number TC Digital Object Identifier no /TC optimized for implementation with QCAs. The carry flow adder design is compared with previous QCA adder designs. On the other hand, multiplier design has not been widely considered by QCA designers. There is a QCA multiplier design in [20], [21], which suggests the importance of design simplicity. Complex designs generally incur long delays in QCA, so a simple structure is a good choice for the starting point. This paper investigates a relatively simple serial parallel multiplier. Based on FIR filter equations, serial parallel multiplication equations are derived. Using QCA characteristics, a new multiplier is presented. The final design shows a simple and regular bit slice structure. Although this paper assumes metal-based QCA implementation, the underlying principles also apply to molecular QCA. There are different clocking schemes such as wave clocking which may be more suitable for molecular QCA. If the manufacturing issues of molecular QCA can be solved, it may be an attractive implementation alternative that mitigates the cryogenic working temperature constraints of metal based QCA. The paper is organized as follows: In Section 2, the background of QCA technology and the design approaches are presented. Section 3 shows the design and implementation of carry flow adders. Simulation results and comparisons follow in Section 4. Section 5 shows the algorithmic design of multiplication networks based on filter networks. Section 6 discusses multiplier implementation for QCA circuits. Simulation results and comparisons follow in Section 7 and conclusions are presented in Section 8. 2 QCA DESIGN SCHEMES 2.1 QCA Cell A QCA is a square nanostructure of electron wells confining free electrons. Each cell has four quantum dots which can hold a single electron per dot. The four dots are located at the corners of the cell and two electrons are injected into the cell. Due to Coulombic repulsion, the two electrons reside in /09/$25.00 ß 2009 IEEE Published by the IEEE Computer Society

2 722 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6, JUNE 2009 Fig. 1. Basic QCA cell and two possible polarizations. Because there are propagation delays between cell-to-cell reactions, there should be a limit on the maximum cell count in a clock zone. This ensures proper propagation and reliable signal transmission. In this paper, a maximum length of 16 cells is used. The minimum separation between two different signal wires is the width of two cells. Multilayer crossovers are used here for wire crossings. They use more than one layer of cells like a bridge. The multilayer crossover design is straightforward although there are questions about its realization, since it requires two overlapping active layers with vertical via connections. Alternatively, coplanar crossovers that may be easier to realize can be used with some modification to the basic designs. For circuit layout and functionality checking, a simulation tool for QCA circuits, QCADesigner [22], is used. This tool allows users to do a custom layout and then verify QCA circuit functionality by simulations. Fig. 2. QCA inverter and majority gate. opposite corners so that two polarizations are possible as seen in Fig. 1. These basic cells can be used to make QCAbased storage elements, logic gates, and wires. 2.2 Signal Flow and Control A series of QCA cells acts like a wire. During each clock cycle, half of the wire is active for signal propagation, while the other half is unpolarized. During the next clock cycle, half of the previous active clock zone is deactivated and the remaining active zone cells trigger the newly activated cells to be polarized. Thus, signals propagate from one clock zone to the next. The circuit area is divided into four sections and they are driven by four phase clock signals. In each zone, the clock signal has four states: high-to-low, low, low-to-high, and high. The cell begins computing during the high-to-low state and holds the value during the low state. The cell is released when the clock is in the low-to-high state and inactive during the high state. 2.3 Logic Gates Logic gates are required to build arithmetic circuits. In QCA, inverters and three-input majority gates serve as the fundamental gates. Inverters are constructed with a fork structure. The governing equation for a majority gate with inputs a, b, and c is Mða; b; cþ ¼ab þ bc þ ca. Fig. 2 shows the gate symbols and their layouts. Two input AND and OR gates can be implemented with three input majority gates by setting one input to a constant. With ANDs, ORs, and inverters, any logic function can be realized: a b ¼ Mða; b; 0Þ; a þ b ¼ Mða; b; 1Þ: 2.4 Design Rules A nominal cell size of 20 nm by 20 nm is assumed. The cell has a width and height of 18- and 5-nm-diameter quantum-dots. The cells are placed on a grid with a cell center-to-center distance of 20 nm. ð1þ 3 CARRY FLOW ADDERS 3.1 Basic Design Approach Previous publications [17], [18], [19] show that interconnections incur significant complexity and wire delay when implemented with QCAs, so transistor circuit designs that assume wires have negligible complexity and delay are not applicable. In QCA, if the complexity increases, the delay may increase because of the increased cell counts and wire connections. In this paper, the adder design follows that of a conventional ripple carry adder, but with a new layout optimized to QCA technology. The proposed adder design shows that a very low delay can be obtained with an optimized layout. This is in contrast to the conventional ripple carry adder. To avoid confusion, the new layout is referred to as the Carry Flow Adder (CFA) here. Equations for a full adder realized with majority gates and inverters are shown in (2). Most adder delays come from carry propagation. For faster calculation, reducing carry propagation delay is most important. The usual approach for fast carry propagation is to add additional logic elements. In this paper, simplification is used instead: s i ¼ a i b i c i þ a ibi c i þ a i b i c i þ a ibi c i ¼ Mð Mða i ;b i ;c i Þ;Mða i ;b i ; c i Þ;c i Þ ¼ Mðc iþ1 ;Mða i ;b i ; c i Þ;c i Þ; c iþ1 ¼ a i b i þ b i c i þ c i a i ; ¼ Mða i ;b i ;c i Þ: In QCA, the path from carry-in to carry-out only uses one majority gate. The majority gate always adds one more clock zone (one quarter clock delay). Thus, each bit in the words to be added requires at least one clock zone which sets the minimum delay. 3.2 Carry Flow Full Adder Design Based on previous approaches, a 1-bit full adder is designed. The input bit streams flow downward and the carry propagates from right to left. Figs. 3a and 3b show the schematic and the layout of the full adder for the carry flow adder. The schematic and layout are optimized to minimize the delay and area. The carry propagation delay for 1-bit is ð2þ

3 CHO AND SWARTZLANDER, JR.: ADDER AND MULTIPLIER DESIGN IN QUANTUM-DOT CELLULAR AUTOMATA 723 Fig. 6. Simulation results for 8-bit CFA. Fig. 3. Full adder for the carry flow adder. (a) Schematic. (b) Layout. a quarter clock and the delay from data inputs to the sum output is three quarter clocks. The wiring channels for the input/output synchronization should be minimized since wire channels add significantly to the circuit area. The carry flow full adder shown in Fig. 3b requires a vertical offset between the carryin and carry-out of only one cell. Figs. 4 and 5 show 4 and 32-bit adders, respectively, realized with carry flow full adders. From the layouts, it is clear that for large adders, much of the area is devoted to skewing the input data and deskewing the outputs. 4 RESULTS 4.1 Simulation Results For clarity, only 8-bit CFA simulation results are shown. The input and output waveforms are shown in Fig. 6. The first meaningful output appears in the third clock period after clock delays. First and last input/output pairs are highlighted. 4.2 Comparisons For design comparisons, QCA carry lookahead adders (CLA) are used since they were smaller and faster than conditional sum and conventional ripple carry adders in a previous study [19]. Fig. 7 shows the layout of a 4-bit CLA. Fig. 7. Layout of a 4-bit carry lookahead adder. It is roughly twice as wide and twice as high as the carry flow adder shown on Fig. 4. Table 1 shows comparisons of the 4, 8, 16, 32, and 64-bit designs for the CLA and CFA. Fig. 8 compares the two types of adders. From the statistics, cell counts for the CFA with n-bit operands are roughly Oðn 1:21 Þ. Areas are Oðn 1:42 Þ. Delay for the CFA-based ripple carry adder is proportional to the word size after a half clock start up delay. From the comparison with the carry lookahead adder, the complexity, area, and delay are much better with the CFA full adder, so the carry flow adder shows the best performance in QCA. 5 MULTIPLIER DESIGN 5.1 Filter Networks To consider the multiplication of two numbers, start with an FIR filter example [23]. The filter output is defined by TABLE 1 Adder Comparisons Fig. 4. Layout of 4-bit carry flow adder. Fig. 5. Layout of 32-bit carry flow adder.

4 724 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6, JUNE 2009 Fig. 8. Comparison of CFA and CLA adders for various operand sizes. y i ¼ b k x i k : Using the one cycle delay operator, Z 1, the equation can be restated as y i ¼ b k x i k ¼ ¼ b k Z k x i b k Z k!x i : Equation (4) can be implemented by the network shown in Fig. 9. The circles in the figure with the b i s represent multiplication by constants and L indicates addition. Data x i ;b i, and y i are words of arbitrary size. To use a pipeline design, both upper and lower signal lines include the same additional delay units. Assume that Z 1 4 is possible and apply the Z 1 2 delay element to each section with upper and lower lines. Equation (5) shows that Fig. 10 gives the correct filter output result with N=2 cycle delays. ð3þ ð4þ 5.2 Multiplication Networks The above relations can be applied to serial parallel multiplication. Assume an unsigned number system. A 1-bit multiplication is performed by an AND gate and a 1-bit addition is performed by a full adder. The main difference between the FIR filter and the multiplication network is the handling of the carry-out from the adder. The filter networks internally use carry flow, but the multiplication network needs distinct signal flows, so the network for multiplication needs to be adjusted accordingly. Let ða i ;b i Þbe the multiplicand and multiplier pair and p i be the product bit for position i. Bits a i and p i correspond to words x i and y i of the filter example. The position i is the input at time i. Define the sum and carry-out of a full adder at the ith time and the jth location as s ij ;c ij when 0 i 2N 1 and 0 j N 1 where larger values of j are to the left. Assume that the sum generation takes at least Z 1 2 and the carry generation takes at least Z 1 4. Even though Figs. 9 and 10 ignored the zeroth full adder, the derivation includes that adder. The implementation can be done as Pipelined FIR filter output ¼ Z 2 1 bn 1 Z 3 2 ðn 1Þ þ Z 1 2 bn 2 Z 3 2 ðn 2Þ þþz 2 1 b0 Z 0 x i ¼ Z N 2 bn 1 Z ðn 1Þ x i þ Z N 2 bn 2 Z ðn 2Þ x i þþz N 2 b0 x i ¼ Z N 2 ¼ Z N 2 yi : b k Z k!x i ð5þ Fig. 9. FIR filter network. Fig. 10. Pipelined FIR filter network.

5 CHO AND SWARTZLANDER, JR.: ADDER AND MULTIPLIER DESIGN IN QUANTUM-DOT CELLULAR AUTOMATA 725 Fig. 11. Redirected FIR filter network. Fig. 14. Redirected FIR filter network for QCA. Fig. 12. Pipelined redirected FIR filter network. ðs ij ;c ij Þ¼Add b j Z 3 2 j a i ; Z 1 2 siðj 1Þ ; Z 1 c ij ¼ Add b j a i 3 2 j; s ði 1 2 Þðj 1Þ; c ði 1Þj : Equation (6) uses a feedback loop to the adder itself using a one clock delay unit. This is denoted as a carry delay multiplier (CDM). It is optimized to minimize the latency of the output. Going to Fig. 9 and redirecting the output to the right side, which is the same side to the input, Fig. 11 shows the redirected graph. For a pipeline design, it can be redrawn as shown in Fig. 12 by using Z 1 2 yi ¼ Z 1 2 ¼ Z 1 2 ¼ Z 1 2 b k Z k!x i b k Z k 2 Z k 2! x i! Z k 2 bk Z k 2 x i : Finally, Fig. 12 is a network design comparable to Fig. 10. The main difference is that there is a much smaller latency from the first input to the first output. Based on Fig. 12, the multiplication network is represented by (8). Fig. 13 shows the network implementation. The CDM design minimizes the latency to the output: s ij ;c ij ¼ Add bj Z 1 2 j a i ; Z 1 2 siðjþ1þ ; Z 1 c ij ð8þ ¼ Add b j a i 1 2 j; s ði 1 2 Þðjþ1Þ; c ði 1Þj : ð6þ ð7þ Fig. 15. CDM network for QCA. 6 MULTIPLIER IMPLEMENTATION 6.1 Multiplication Networks for QCA Based on the QCA circuit characteristics, one clock zone provides a quarter clock delay, which matches the D 1 operation. That is, D 4 ¼ Z 1. Assume a logical AND operation provides one D 1 delay and a full adder sum and carry have D 2 and D 1 delays, respectively. Wires also have some clock cycles of delay based on the wire length. After incorporating these characteristics, the filter network of Fig. 12 is redrawn, as shown in Fig. 14. Delay amounts in upper and lower signal flows are chosen to make a one clock cycle difference between the adjacent paths. From the filter network examples, a multiplier for QCA is developed. Based on (8), (9) reflects the QCA clocking. The previous figure is modified and the serial parallel multiplier can be implemented as shown in Fig. 15 s ij ;c ij ¼ Add bj D 2j 2 a i ; D 2 s iðjþ1þ ; D 4 c ij ð9þ ¼ Add b j a i 2j 2 ; s ði 2Þðjþ1Þ ; c ði 4Þj : 6.2 Multiplier Design The structure shown in Fig. 15 is used for the QCA circuit implementation since it minimizes the latency from the first input to the first output. Fig. 16 shows the block diagram of the optimized design for QCA layout. 6.3 QCA Implementation Bit-serial adders are used to realize the carry delay multiplier. The underlying full adders are based on the CFA that is Fig. 13. Carry delay multiplication network. Fig. 16. Multiplier block diagrams for CDM.

6 726 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6, JUNE 2009 TABLE 2 Multiplier Characteristics Fig. 17. Carry flow bit-serial adder. (a) Schematic. (b) Layout. For N-bit inputs, the multiplier receives N þ 1 inputs (a serial input and N parallel inputs) and produces a serial output. The serial input and output are ordered from LSB to MSB and parallel inputs are repeated whenever a new serial input is provided (N cycles). For initialization of the multiplier, zero bits are input for N clock cycles. Zero bits are provided between successive inputs. The time to complete an N-bit multiplication is 2N cycles. 7.2 Comparisons The complexity, size, and delay of various word size carry delay multipliers are shown in Table 2. Fig. 20 demonstrates the layout of a 32-bit CDM. Fig. 18. Layout of a 4-bit carry delay multiplier. Fig. 19. Simulation of a 4-bit carry delay multiplier. described in Section 3 with the schematic and layout shown in Figs. 3a and 3b, respectively. The bit-serial adder is modified from the full adder so that the carry-in and carry-out are connected internally with a one clock delay. Figs. 17a and 17b show the schematic and layout of the bit-serial adder. Using these adders, a 4-bit CDM multiplier according to Fig. 16 is implemented as shown in Fig. 18. Multipliers for larger word sizes can be implemented easily by adding additional bit slices. 8 CONCLUSIONS QCA circuits have significant wire delays. For a fast design in QCA, it is generally necessary to minimize the complexity. Based on the QCA characteristics, this paper presents a new adder design, the carry flow adder. Carry flow adders use a basic ripple carry propagation scheme that is optimized for layout in the QCA technology. The layouts and functionality checks were done using QCADesigner and the designs are compared to the carry lookahead adder that was the best previous QCA adder design. The CFA adders require less than one-fifth of the area of the CLA and have about half of the delay of the CLA. This paper also presents serial parallel multiplication networks based on filter networks. The networks are derived from multiplication equations and implemented by network graphs. The design uses systolic array structures to produce an output on every clock cycle with low latency to the first output. It also has a regular design for easy word size extension as well as small area and a small number of cells was used. 7 RESULTS 7.1 Simulation Results Simulation of a 4-bit multiplier is shown with the input and output waveforms in Fig. 19. First and last input/output pairs are highlighted. ACKNOWLEDGMENTS Sections 5, 6, and 7 are greatly abbreviated versions of the material in [24]. The authors also thank the reviewers and the attendees of the Symposium for their constructive comments. Fig. 20. Layout of a 32-bit carry delay multiplier.

7 CHO AND SWARTZLANDER, JR.: ADDER AND MULTIPLIER DESIGN IN QUANTUM-DOT CELLULAR AUTOMATA 727 REFERENCES [1] International Technology Roadmap for Semiconductors (ITRS), [2] C.S. Lent, P.D. Tougaw, W. Porod, and G.H. Bernstein, Quantum Cellular Automata, Nanotechnology, vol. 4, no. 1 pp , Jan [3] A. Orlov et al., Experimental Demonstration of a Binary Wire for Quantum-Dot Cellular Automata, Applied Physics Letters, vol. 74, no. 19, pp , May [4] I. Amlani et al., Experimental Demonstration of a Leadless Quantum-Dot Cellular Automata Cell, Applied Physics Letters, vol. 77, no. 5, pp , July [5] R.P. Cowburn and M.E. Welland, Room Temperature Magnetic Quantum Cellular Automata, Science, vol. 287, no. 5457, pp , Feb [6] H. Qi et al., Molecular Quantum Cellular Automata Cells. Electric Field Driven Switching of a Silicon Surface Bound Array of Vertically Oriented Two-Dot Molecular Quantum Cellular Automata, J. Am. Chemical Soc., vol. 125, pp , [7] R.K. Kummamuru et al., Operation of a Quantum-Dot Cellular Automata (QCA) Shift Register and Analysis of Errors, IEEE Trans. Electron Devices, vol. 50, no. 9, pp , Sept [8] A. DeHon and M.J. Wilson, Nanowire-Based Sublithographic Programmable Logic Arrays, Proc. Int l Symp. Field-Programmable Gate Arrays, pp , [9] J.M. Seminario et al., A Molecular Device Operating at Terahertz Frequencies: Theoretical Simulations, IEEE Trans. Nanotechnology, vol. 3, no. 1, pp , Mar [10] Y. Wang and M. Lieberman, Thermodynamic Behavior of Molecular-Scale Quantum-Dot Cellular Automata (QCA) Wires and Logic Devices, IEEE Trans. Nanotechnology, vol. 3, no. 3, pp , Sept [11] R. Tang, F. Zhang, and Y.B. Kim, Quantum-Dot Cellular Automata SPICE Macro Model, Proc. ACM Great Lakes Symp. VLSI, pp , [12] C.S. Lent, M. Liu, and Y. Lu, Bennett Clocking of Quantum-Dot Cellular Automata and the Limits to Binary Logic Scaling, Nanotechnology, vol. 17, no. 16, pp , Aug [13] X. Ma, J. Huang, and F. Lombardi, A Model for Computing and Energy Dissipation of Molecular QCA Devices and Circuits, ACM J. Emerging Technologies in Computing Systems, vol. 3, no. 4, article 18, [14] A. Vetteth et al., Quantum-Dot Cellular Automata Carry-Look- Ahead Adder and Barrel Shifter, Proc. IEEE Emerging Telecomm. Technologies Conf., Sept [15] W. Wang, K. Walus, and G.A. Jullien, Quantum-Dot Cellular Automata Adders, Proc. Third IEEE Conf. Nanotechnology, pp , [16] R. Zhang, K. Walus, W. Wang, and G.A. Jullien, Performance Comparison of Quantum-Dot Cellular Automata Adders, Proc. IEEE Int l Symp. Circuits and Systems, vol. 3, pp , [17] H. Cho and E.E. Swartzlander, Jr., Pipelined Carry Lookahead Adder Design in Quantum-Dot Cellular Automata, Proc. Conf. Record of the 39th Asilomar Conf. Signals, Systems, and Computers, pp , [18] H. Cho and E.E. Swartzlander, Jr., Modular Design of Conditional Sum Adders Using Quantum-Dot Cellular Automata, Proc. Sixth IEEE Conf. Nanotechnology, July [19] H. Cho and E.E. Swartzlander, Jr., Adder Designs and Analyses for Quantum-Dot Cellular Automata, IEEE Trans. Nanotechnology, vol. 6, no. 3, pp , May [20] K. Walus, G.A. Jullien, and V.S. Dimitrov, Computer Arithmetic Structures for Quantum Cellular Automata, Proc. Conf. Record of the 37th Asilomar Conf. Signals, Systems, and Computers, vol. 2, pp , [21] K. Walus and G.A. Jullien, Design Tools for an Emerging SoC Technology: Quantum-Dot Cellular Automata, Proc. IEEE, vol. 94, no. 6, pp , [22] K. Walus, T. Dysart, G. Jullien, and R. Budiman, QCADesigner: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata, IEEE Trans. Nanotechnology, vol. 3, no. 1, pp , Mar [23] D. Cohen, A Mathematical Approach to Computational Network Design, Systolic Signal Processing Systems, E.E. Swartzlander, Jr., ed., Marcel Dekker, Inc., pp. 1-29, [24] H. Cho and E.E. Swartzlander, Jr., Serial Parallel Multiplier Design in Quantum-Dot Cellular Automata, Proc. 18th IEEE Symp. Computer Arithmetic, pp. 7-15, Heumpil Cho received the BS degree in electrical engineering and the MS degree in electrical engineering and computer science from Seoul National University, and the PhD degree in electrical and computer engineering from the University of Texas at Austin, in 1998, 2000, and 2006, respectively. In 2006, he was with Luminary Micro, Inc., Austin, TX, where he was working on I/O circuit characterization and modeling. Since 2007, he has been a senior engineer at Qualcomm, Incorporated, San Diego, CA, where he has been working on various projects including CDMA/WCDMA/LTE/ WiMAX wireless modem chip designs. His research interests include high-speed computer arithmetic algorithms, systolic signal processor and CORDIC processor architectures, VLSI circuit designs, architectures for application-specific signal processing, and applications of arithmetic algorithms on quantum-dot cellular automata. He is a member of the IEEE. Earl E. Swartzlander, Jr. holds degrees in electrical engineering from Purdue University, the University of Colorado, and the University of Southern California. He is a professor of electrical and computer engineering at the University of Texas at Austin. In his current position, he and his students conduct research in computer engineering with emphasis on application specific processor design, including high-speed computer arithmetic, systolic processor architecture, VLSI technology, and rapid prototyping. From 1975 to 1990, he held a variety of positions at TRW including the director of Independent Research & Development in the TRW Defense Systems Group, the manager of the Digital Processing Laboratory in the Electronics and Technology Division, and the manager of the Advanced Development Office in the System Development Division. He was the editor-in-chief of the IEEE Transactions on Computers from 1990 to 1994 and was the founding editor-in-chief of the Journal of VLSI Signal Processing. In addition, he has served as an editor for the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the IEEE Journal of Solid-State Circuits. He has been a member of the Board of Governors of the IEEE Computer Society ( ), the IEEE Signal Processing Society ( ), and the IEEE Solid-State Circuits Council/Society ( ). He has been a member of the IEEE History Committee ( ), the IEEE Fellows Committee ( ), and is currently the chair of the IEEE James H. Mulligan, Jr., Education Medal Committee. He has chaired a number of conferences including the IEEE International Conference on Application-Specific Architectures, and Processors, the 31st Asilomar Conference on Signals, Systems and Computers, the International Conference on Parallel and Distributed Systems, the 11th Symposium on Computer Arithmetic, the International Conference on Wafer Scale Integration, and the fifth IEEE International Conference on Distributed Computing Systems. He is the author of one book, an editor of seven books, and the author or coauthor of 59 refereed journal papers, 33 book chapters, and 254 conference papers. He is a fellow of the IEEE. He has been honored with the IEEE Third Millennium Medal, the Distinguished Engineering Alumnus Award from the University of Colorado, the Outstanding Electrical Engineer and Distinguished Engineering Alumnus awards from Purdue University, and the IEEE Computer Society Golden Core Award.. For more information on this or any other computing topic, please visit our Digital Library at