A Structured Ultra-Dense QCA One-Bit Full-Adder Cell

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1 RESEARCH ARTICLE Copyright 2015 American Scientific Publishers All rights reserved Printed in the United States of America Quantum Matter Vol. 4, 1 6, 2015 A Structured Ultra-Dense QCA One-Bit Full-Adder Cell Soheil Sarmadi 1, Samira Sayedsalehi 2, Mehdi Fartash 1, Shaahin Angizi 3 1 Department of Computer Engineering, Islamic Azad University, Arak Branch, Arak, Iran 2 Faculty of Computer Engineering, Islamic Azad University, South Tehran Branch, Tehran, Iran 3 Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G. C., Tehran, Iran Quantum-dot cellular automata is one of the emerging technologies for designing Nano scale computer circuits. It is not far from mind that one day this technology will be replaced with conventional CMOS circuits. Therefore, in this article, we are going to suggest a novel well-optimized one-bit full-adder cell based on this technology with six active layers. The presented one-bit full-adder cell can dominate all the previous designs in terms of cell counts and area occupation. To verify the correctness of the proposed design, QCADesigner, a well-known QCA simulator is employed. Keywords: Quantum-Dot Cellular Automata, Nanoelectronics, One-Bit Full-Adder Cell, Five-Input Majority cell. 1. INTRODUCTION For many decades, CMOS technology was the dominated technology for a wide variety of devices and circuits. This technology had some limitations in Nano scale designing circuits so investigations regards to an alternative technology have launched. 1 QCA is one of the promising technologies, which is convenient for designing Nano scale circuits with low power and fast switching mechanism. In this technology, digital information is transmitted through polarization instead of current in the last technologies. 2 Basic concept of QCA is summarized in two extra electrons configurations within a four dots square. These electrons can be placed in any of the dots; therefore six different states are gained which just two of them are stabled. These two states are named cell polarization and one of them is recognized 1 as the logic 0 and the other one is recognized +1 as the logic 1, 3 which these two states are shown in Figure 1. One-bit full-adder cell is the core element of arithmetic circuits like addition, division, multiplication, exponentiation, etc., so in QCA domain many efforts have been made regards to designing an efficient full-adder cell Also nowadays, several studies have been performed towards design and verification of various QCA digital logic circuits; such as, multi-input majority gates and complex gates, implementing flip-flops and memory cells and also reliability analysis of QCA structures in Refs. [20, 21]. The general objective of our work is to implement a novel well-organized QCA one-bit full-adder cell with the minimum Author to whom correspondence should be addressed. cell numbers and least possible area occupation. This paper is organized as follows; QCA preliminaries are presented in Section 2. State-of-the-art designs for one-bit full-adder cell are addressed in Section 3 and the proposed structure is presented in Section 4. Verification and simulation result are shown in Section 5 and finally Section 6 concludes the paper. 2. QCA PRELIMINARIES 2.1. Wiring Concepts A QCA 90 degree standard wire can be constructed based on inherent capability of QCA cells. Two juxtaposed cells constantly try to keep their polarizations similar to the other one in order to remain in their least energy sates. 2 As shown in Figure 2(a), by entering an input signal at the first cell, next cell electrons will be affected by electrostatic repulsion of the first cell, so second cell s polarization will be switched and it continues in this way. In another implementation of QCA wire in Figure 2(b), which is gained by placing 45 degree (Rotated) cells side-by-side, input signal can be extracted from the odd cells and inversion of the input signal can be extracted from even cells. 3 Interconnection issues in digital Nanoelectronic systems must be inspected proficiently, so signal crossover in QCA circuits is accomplished through utilizing two types of wires which mentioned earlier. As is demonstrated in Figure 3, one QCA standard wire is crossed over another QCA rotated wire. This kind of QCA wiring is called coplanar wire crossing and studies have proved that the mentioned wires have no effect on each other. 3 Quantum Matter Vol. 4, No. 6, /2015/4/001/006 doi: /qm

2. Inverter and Three-Input Majority Gate Inverting signals in QCA logics is simply achieved by diagonal arrangements of QCA cells in single layer or by vertical arrangement of them as is shown in

2 RESEARCH ARTICLE Quantum Matter 4, 1 6, 2015 Fig. 1. QCA basic cell with two stabled arrangements Inverter and Three-Input Majority Gate Inverting signals in QCA logics is simply achieved by diagonal arrangements of QCA cells in single layer or by vertical arrangement of them as is shown in Figure 4(a). In addition, a Quantum-dot cellular automata three-input majority gate is composed of three input cells, one device cell and one output cell as is shown in Figure 4(b). According to the effects of input cells on the device cell and maximum vote of the inputs polarizations, the output polarization is specified. 2 3 Two-input AND gate and two-input OR gate as the basic gates are developed from three-input majority gate by setting one of its inputs to 0 logic and 1 logic, respectively. As is clear, logical expressions Eqs. (2) and (3) describe how to develop the basic gates form majority function equation (Eq. (1)). With putting together the mentioned structures (inverter and three-input majority gate), universal NAND and NOR gates can be formed. Although in QCA-compatible designs is tried to present novel structures with applying main structure of three-input majority gate. Maj A B C = AB + AC + BC (1) Maj A B 1 = AB + A 1 + B 1 = A + B (2) Maj A B 0 = AB + A 0 + B 0 = A B (3) 2.3. Five-Input Majority Gate In 2007, for the first time in QCA area, multi-input majority gate application was investigated with presenting a 3-dimentinal five-input majority gate in Ref. [10], as shown in Figure 5(a). However, the presented design requires high technologies to implement practically. Therefore, in 2010, two novel planar structures for five-input majority gate are proposed in literatures In the first layout which is made of the form found in Figure 5(b), the output cell is surrounded by the input cells and in the second layout is attempted to extract the output flow from one of the outer cells as shown in Figure 5(c) Clocking Mechanism Similar to the other digital circuits, QCA implementations are synchronized by dividing in clocking zones. Each clocking zone Fig. 3. Signal crossover in QCA using two types of cells. can be contained at least two QCA cells. QCA circuits are synchronized and controlled by four phases (Switch, Hold, Release and Relax) which trace all of the clocking zones sequentially as it is illustrated in Figure 6. 4 In the switch phase, cells polarizations will be switched due to the neighbor cells polarizations which are also in switch or hold phases. During the hold phase cells keep their polarizations and only can effect on the other cells. In release and relax phases cells lose their polarizations which are called un-polarized PREVIOUS ONE-BIT FULL-ADDER CELL DESIGNS As is obvious, one-bit full-adder cell is the basic element in arithmetic unit of digital systems and its performance can affect entire system operations. 8 Therefore, up to now many attempts have been made in literatures to present a well-organized and lowcomplexity structure for one-bit full-adder cell where most of them are constructed using three-input majority gate. In the following subsections, early one-bit full-adder designs are reviewed Tougaw s Design The first QCA-compatible design for one-bit full-adder cell has been presented in 1994 by Tougaw et al. 2 To produce correct Sum Fig. 2. wire. Two types of QCA wiring (a) standard QCA wire (b) rotated QCA Fig. 4. (a) QCA inverter arrangements (b) three-input majority gate. 2

Quantum Matter 4, 1 6, 2015 RESEARCH ARTICLE Fig. 5. The presented structures for 5-input majority gate (a) Three-dimensional structure in Ref. [10] (b) First planar structure in Ref.

3 Quantum Matter 4, 1 6, 2015 RESEARCH ARTICLE Fig. 5. The presented structures for 5-input majority gate (a) Three-dimensional structure in Ref. [10] (b) First planar structure in Ref. [11] (c) Second planar structure in Ref. [12]. and Carry signals, this design is comprised of five three-input majority gates and three inverters as illustrated in Figure 7 and no individual AND or OR gates are used. This design is utilized by researchers as the main structure of two QCA implementations. First architecture in Ref. [2] has consumed 192 cells in unsuitable cells arrangements which provide the QCA layout with more complexity. It is to be noted that the clocking mechanism is not considered in this circuit. In 2002, during the second attempt in Ref. [22], Vetteh et al. have introduced another slightly different QCA implementation based on conventional design considering clocking concept. This circuit has evaluated the output s waveform after 14 clocking phases, so latency of this architecture is 3.5 clocking cycle Wang s Design Second reduced logical design for QCA one-bit full-adder cell is introduced in Ref. [7] based on a new addition algorithm. As illustrated in Figure 8, this design is composed of five gates (3 three-input majority gates and 2 inverters). In the first QCA implementation which is presented in Ref. [7], circuit propagation delay is equaled by 1.25 clocking cycle. Considering the presented schematic diagram several implementations can be found in the literatures In Ref. [9], various kinds of adders using the presented one-bit full-adder such as ripple carry adders carry look ahead adders and conditional sum adders are designed. Each one of them has tried to suggest a QCA layout with less cell count, area occupation and delay Azghadi s Design The last optimized design for one-bit full-adder cell is based on five-input majority gate (Fig. 9). 10 Moreover, this design is composed of only one three-input majority gate and one inverter. Since advantages of this logical design such as gate count s diminution, simplicity and its low latency, most of the recent research papers have focused on QCA implementation based on this design In Figures 10(a), (b) and 11(a), (b), four presented QCA layout using Azghadi s design are illustrated. The presented structure in Figure 11(b) with 0.02 m 2 occupation area and 31 cells is the best implemented QCA one-bit full-adder cell up to now. Fig. 6. Clocking zones in QCA. Fig. 7. First three-input majority gate-based design for one-bit full-adder presented in Ref. [2]. 3

RESEARCH ARTICLE Quantum Matter 4, 1 6, 2015 Fig. 8. The presented schematic for one-bit full-adder cell in Ref. [7]. 4. ONE-BIT FULL-ADDER CELL In this section, we are going to present an efficient one-bit fulladder cell which is relied on logical diagram found in Figure 9.

As it shown in Figure 13, this design consists of six active layers which the Carry signal is generated in the first layer based on the corresponding equation (Eq.

Layers 3 and 4 are considered as the interface layers for transmitting the inputs (A, B and C) and Carry signals to the computation layer (Layer 5) which generates the Exclusive-NOR of the input

4 RESEARCH ARTICLE Quantum Matter 4, 1 6, 2015 Fig. 8. The presented schematic for one-bit full-adder cell in Ref. [7]. 4. ONE-BIT FULL-ADDER CELL In this section, we are going to present an efficient one-bit fulladder cell which is relied on logical diagram found in Figure 9. Figure 12 shows the proposed structure for one-bit full-adder cell with isometric view which makes easy to understand the location of cells on top of each other. As it shown in Figure 13, this design consists of six active layers which the Carry signal is generated in the first layer based on the corresponding equation (Eq. (4)) and all the input signals are injected to the three-input majority gate in the second layer. Layers 3 and 4 are considered as the interface layers for transmitting the inputs (A, B and C) and Carry signals to the computation layer (Layer 5) which generates the Exclusive-NOR of the input signals at the central cell of the five-input majority gate. The sixth-layer is contained only two cells; one is on the central cell of the five-input majority gate in order to transmit the Sum signal to this layer and the other one is the Sum cell which is placed next to this cell to propagate the summation of the input signals (Eq. (5)). Fig. 10. QCA layout of one-bit full-adder cell (a) The presented design in Ref. [11] (b) The presented design in Ref. [12]. which leads to low complexity circuit. It is worth to mention that all the input signals are organized in the first clocking zone in the layer two. Carryout layer (Layer 1) and the first interface layer (Layer 3) are ordered in the second clocking zone. Layer 4 and the input cells of the five-input majority gate (Layer 5) are arranged in the third clocking zone and finally the middle cells of layer 5 and 6 are ordered in the fourth clocking zone. As is clear, fast carry propagation (0.5 clocking cycle) and ability of carry extraction from both most bottom layers (Layer 1 and 2) will Carry = Maj3 A B C (4) Sum = Maj5 A B C Carry Carry (5) In order to optimization in hardware requirements (cell count and area occupation), this design is implemented in six layers. The inverters are embedded through layer transmission approach Fig. 11. Last optimized one-bit full-adder cells (a) First QCA layout in Ref. [6] (b) Second QCA layout in Ref. [6]. Fig. 9. The presented schematic for one-bit full-adder cell in Ref. [10]. 4 Fig. 12. Isometric image of the proposed one-bit full-adder cell.

Quantum Matter 4, 1 6, 2015 RESEARCH ARTICLE Table I. Comparison of full-adders. Full-adder design Area ( m 2 ) Complexity (cells) Delay Proposed design 0 004 30 4 clock phase Design in Ref.

[11] 0 03 61 3 clock phase Design in Ref. [2] 0 20 192 Not applicable Design in Ref. [22] 0 62 292 14 clock phase Design in Ref. [25] 0 10 108 4 clock phase Design in Ref.

5 Quantum Matter 4, 1 6, 2015 RESEARCH ARTICLE Table I. Comparison of full-adders. Full-adder design Area ( m 2 ) Complexity (cells) Delay Proposed design clock phase Design in Ref. [6] clock phase Design in Ref. [6] clock phase Design in Ref. [13] clock phase Design in Ref. [12] clock phase Design in Ref. [11] clock phase Design in Ref. [2] Not applicable Design in Ref. [22] clock phase Design in Ref. [25] clock phase Design in Ref. [10] >0 9 2 >107 2 Not applicable Design in Ref. [7] clock phase Design in Ref. [9] clock phase result in considerable achievement in overall circuit performance which is effective in designing n-bit full-adders. Fig. 13. Divided layers of the proposed one-bit full-adder cell. 5. SIMULATION AND DISCUSSION The proposed QCA full-adder is simulated and evaluated within both simulation engines (Bistable Approximation and Coherence Vector) of QCADesigner tool version with the following parameters: cell size = 18 nm, number of samples = 50000, convergence tolerance = , radius of effect = nm, relative permittivity = , clock low = e 021 J, clock high = e 022 J, clock shift = 0, clock amplitude factor = , layer separation = , maximum iterations per sample = A sample of outcome signals of the proposed one-bit full-adder is shown in Figure 14 and the correctness of the proposed structure is verified. The first meaningful carry and sum signal s wave forms are obtained after 0.5 and 1 clocking cycle, respectively. Comparison between the proposed architecture and the previous designs are reported in Table I. As is clear, the proposed structure is the most efficient design in terms of area occupation and complexity. 6. CONCLUSION In this investigation, according to the significant role of fulladder cells in QCA arithmetic units, a novel efficient one-bit fulladder cell has been proposed. To provide the correct functionality beside the least possible occupation area with this circuit, we have employed six active layers in an innovative approach which leads to keep the size of proposed one-bit full-adder cell equal by a five-input majority gate. It is reported that after implementation and verification processes by using QCADesigner environment, an effective circuit optimization is achieved in terms of cell count and area occupation in contrast to state-of-the-art designs. Acknowledgment: The authors wish to thank Professor Sadaf Sarmadi for her literature contribution. Fig. 14. Simulation result of the proposed one-bit full-adder cell. References and Notes 1. R. Compano, L. Molenkamp, and D. J. Paul, Proc. Eur. Comm. IST Programme, Future Emerging Technol. (1999). 2. P. D. Tougaw and C. S. Lent, J. Appl. Phys. 75, 1818 (1994). 3. A. Roohi and H. Khademolhosseini, Rev. Theor. Sci. 2, 46 (2014). 4. K. Kim, K. Wu, and R. Karri, IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E89-A, 1607 (2006). 5. V. Vankamamidi, M. Ottavi, and F. Lombardi, IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 27, 34 (2008). 5

6 RESEARCH ARTICLE Quantum Matter 4, 1 6, S. Sayedsalehi, M. H. Moaiyeri, and K. Navi, J. Comput. Theor. Nanosci. 8, 1769 (2011). 7. W. Wang, K. Walus, and G. A. Jullien, 3rd IEEE Conference on Nanotechnology (2003), pp V. Foroutan, M. R. Taheri, K. Navi, and A. Azizi Mazreah, INTEGRATION, The VLSI Journal 47, 48 (2014). 9. H. Cho and E. E. Swartzlander, IEEE Transactions on Computers 58, (2009). 10. M. R. Azghadi, O. Kavehei, and K. Navi, Journal of Applied Sciences 7, 3460 (2007). 11. K. Navi, S. Sayedsalehi, R. Farazkish, and M. R. Azghadi, J. Comput. Theor. Nanosci. 7, 1546 (2010). 12. K. Navi, R. Farazkish, S. Sayedsalehi, and M. R. Azghadi, Microelectronics Journal 41, 820 (2010). 13. S. Hashemi, M. Tehrani, and K. Navi, Sci. Res. Essays 7, 177 (2012). 14. K. Navi, A. Roohi, and S. Sayedsalehi, J. Comput. Theor. Nanosci. 10, 1 (2013). 15. A. S. Shamsabadi, B. S. Ghahfarokhi, K. Zamanifar, and A. Vafaei, J. Syst. Archit. 55, 180 (2009). 16. Sh. Sheikhfaal, K. Navi, Sh. Angizi, and A. H. Navin, Quantum Matter (2015), in press. 17. V. Vankamamidi, M. Ottavi, and F. Lombardi, IEEE Trans. Comput. 57, 606 (2008). 18. X. Yang, L. Cai, X. Zhaho, and N. Zhang, Microelectron. J. 41, 56 (2010). 19. Sh. Angizi, K. Navi, S. Sayedsalehi, and A. H. Navin, J. Comput. Theor. Nanosci. 11 (2014), inpress. 20. R. Farazkish, J. Nanopart. Res. 16, 2259 (2014). 21. P. Gupta, N. K. Jha, and L. Lingappan, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 15, 24 (2007). 22. A. Vetteth, K. Walus, G. A. Jullien, and V. Dimitrov, Proceed. IEEE Emerging Telecommun. Technol., Dallas, TX 2-I-4 (2002). 23. QCADesigner Documentation [online]. Available from: K. Walus, T. J. Dysart, G. A. Jullien, and R. A. Budiman, IEEE Trans. Nanotechnol. 3, 26 (2004). 25. R. Zhang, K. Walus, W. Wang, and G. A. Jullien, Proceed. IEEE Int. Symp. Circuits Syst. (2005), Vol Received: 16 June Accepted: 17 July

A Novel Architecture for Quantum-Dot Cellular Automata Multiplexer

www.ijcsi.org 55 A Novel Architecture for Quantum-Dot Cellular Automata Multiplexer Arman Roohi 1, Hossein Khademolhosseini 2, Samira Sayedsalehi 3, Keivan Navi 4 1,2,3 Department of Computer Engineering,