EXPLORATION ON POWER DELAY PRODUCT OF VARIOUS VLSI MULTIPLIER ARCHITECTURES

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1 International Journal of Mechanical Engineering and Technology (IJMET) Volume 9, Issue 1, January 2018, pp , Article ID: IJMET_09_01_006 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed EXPLORATION ON POWER DELAY PRODUCT OF VARIOUS VLSI MULTIPLIER ARCHITECTURES S.Karunakaran Professor, Department of ECE, Vardhaman College of Engineering (Autonomous), Shamshabad, Hyderabad, India Y.Pandurangaiah Professor, Department of ECE, Vardhaman College of Engineering (Autonomous), Shamshabad, Hyderabad, India Joseph Anthony Prathap Associate Professor, Department of ECE, Vardhaman College of Engineering (Autonomous), Shamshabad, Hyderabad, India B.Poonguzharselvi Assistant Professor, Department of CSE, Chaitanya Bharathi Institute of Technology (Autonomous), Kokapet, Hyderabad, India ABSTRACT: Multipliers plays a major role in signal processing and several other applications. High Performance VLSI architecture for multipliers is required in terms of low power dissipation, higer speed, lesser area. The most important consideration in Low power VLSI design is power dissipation. Researchers are taking more efforts to decrease the power consumption. The power dissipation efficiency can be identified by power delay product. The optimized design is one in which the architecture is having lesser power delay product. The methods used for doing multiplication are add and shift method. In parallel multipliers, the multiplier performance depends upon the partial products count. Array multiplier, On the fly conversion multiplier, vedic multiplier are designed and analysed. All the above multipliers are designed in Cadence Virtuoso Schematic Editor environment using 180nm technology. The power delay product for array multiplier, on the fly conversion multiplier, vedic multiplier is found to be be 5.41 pj, 5.04 pj, 4.58 pj respectively. So out of three proposed multipliers Vedic multipliers shows better power delay product. Keywords: Array Multiplier, on the fly conversion multiplier, Vedic multiplier 53 editor@iaeme.com

2 Exploration on Power Delay Product of various VLSI Multiplier Architectures Cite this Article: S.Karunakaran, Y.Pandurangaiah, Joseph Anthony Prathap and B.Poonguzharselvi, Exploration on Power Delay Product of various VLSI Multiplier Architectures, International Journal of Mechanical Engineering and Technology 9(1), 2018, pp INTRODUCTION: Multiplier plays a significant role in DSP applications. Multiplier consists of two inputs and one output. Two inputs are designated as multiplier and multiplicand. Repeated addition of the multiplicand with the times defined by the multiplier have to be performed to get the output in multiplier. The multiplicand is multiplied by every bit of the multiplier starting from the LSB bit. In this process, partial products are generated. Partial products have to be added to get the final result or product. Array multiplier, On the fly conversion multiplier, vedic multiplier are designed and analyzed.[1][5][6][7] 2. MATERIALS AND METHODS: 2.1. Array Multiplier: The incoming signals can be multiplied with the filter coefficients. This can be done by a multiplier module. Mainly multipliers are categorized into array multiplier and array multiplier. Array multiplier consists of two dimensional full adder arrays. Combinational multiplier is composed of array multiplier. Combinational multiplier consists of rows of carry save adder circuits. The summands are calculated in parallel with AND gates, which are then summed to the single bit full adder array. An nxn multiplier array comprises of (n-1) rows of carry save adders in which each row comprises (n-1) full adders. The final row is a ripple carry adder which is meant for carry propagation. Figure 1 Array multiplier basic cell The basic structure of an array is shown in the Figure 1. The inputs are designated as x, y, C in. The outputs are designated as Sum (S) and Carry out (C out ). The rules for implementing the array multiplication are, 1. Matrices should have equal dimensions. 2. When two matrices are multiplied, the resulting matrix dimensions also will be the same. 3. Resulting elements are the outcome of the corresponding elements in the matrices which are multiplied. The steps for doing multiplication process is given in Figure editor@iaeme.com

3 S.Karunakaran, Y.Pandurangaiah, Joseph Anthony Prathap and B.Poonguzharselvi X4 X4 X4 X4 X4 X4 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Figure 2 Array Multiplication In the Figure 3, 5*5 array multiplier is shown. The inputs are x i. and a i.the output is designated as p i. 2n bits will be the produced as output bits in the array multiplier. Figure 3 Carry save array multiplier The carry generated in carry save array multiplier from full adder and half adder is propagated to the adder s next row. Ripple carry adders are present in the last row and the generated carry is provided to the adder which is present in the same row. Since the carry is propagated in the last stage, the delay will be more. This type of carry propagation is eliminated in the case of on the fly conversion multiplier On the fly Conversion multiplier: Multiplier speed depends upon the speed of the carry propagation. The on the fly conversion logic is proposed to speed up the carry propagate addition which is happening at the final stage of multiplication process. In array multiplier, the number of output bits is 2*n bits. The LSB bits produced by on the fly conversion multiplier is computed in a similar way as computed in array multiplier. In On the fly conversion logic, the carry propagation at the last stage of multiplication process is eliminated. In this scheme, most significant bit is determined by making on the fly conversion multiplier to operate in parallel while computing the least significant bits. The time taken for multiplying two numbers is reduced in on the fly conversion multiplier. The On the fly conversion multiplier has lesser delay when compared to the array multiplier editor@iaeme.com

4 Exploration on Power Delay Product of various VLSI Multiplier Architectures Figure 4 On-the-fly conversion multiplier for unsigned numbers (N=5) Consider X and Y are the two numbers which can be represented as X = [x n-1 x n-2..x 0 ] and Y = [y n-1 y n-2...y 0 ] respectively. X is nothing but a binary number consists of 1s and 0s. Z is the product obtained by multiplying X and Y which is written as Z= X.Y. The LSB bits of array output Z are generated in carry form and the MSB bits are generated in sum carry pair form. On-the-fly conversion multiplier structure is shown in Figure 4. From the diagram shown it is clearly understood that when the carry-sum pair is generated from the array of full adder, the On the fly conversion calculation for each pair is initiated. Figure 5 On-the-fly conversion logic The On-the-fly conversion logic structure is shown in Figure 5. The carry and sum can be calculated by the above formulae, carry (c)=a i b i, i=1,2,, (n-1) sum (s)= a i ^ b i, i=1,2,, (n-1) The sum is XOR operation of a and b. The carry is AND operation of a and b editor@iaeme.com

5 S.Karunakaran, Y.Pandurangaiah, Joseph Anthony Prathap and B.Poonguzharselvi The sum is obtained by the XOR function of the input a and b. The carry is obtained by the AND function of the input a and b.the On the fly conversion multiplier netlist is generated and the same is also simulated.the schematic diagram of the on the fly conversion multiplier is shown in Fig 6. Figure 6 On-the-fly conversion multiplier circuit 2.3. Vedic Multiplier: Mathematics is based on sixteen sutras. Vertically and cross wise is one of the sutras. Vedic multiplier is based on vertically and crosswise. The important characteristics of the Vedic system is the feature of coherence. In general multiplication method, is quickly reversed to allow one line divisions and the simple squaring method can be allowed to provide one line square roots. In the Vedic system, complex problems can be solved by the vedic method. The methods which is given by vedic mathematics is more structured than the modern system. It is having the property of coherence and systematic way.[2][3][4] Multiplication is one of the most important arithmetic operations in signal processing applications. Data processing and signal processing involve multiplication. The bottleneck in the multiplication operation is the speed. Speed can be increased by decreasing the number of steps in the computation process. The efficiency of a system always depends upon multiplier speed. Speed, Power dissipation and memory are the three important considerations while determining the performance of the system. Vedic multiplier architecture is based on vertically and cross wise algorithm. The 2 multiplication is performed in a single line in Urdhva Tiryabhyam algorithm, where as in the existing system, four partial products are added to arrive at the result. The number of steps required to calculate the final product are reduced and also the time required for computation also reduced and the speed of the system will be improved. Illustration is shown in figure 7 Figure 7 Illustration of Urdhva Tiryagbhyam sutra 57 editor@iaeme.com

6 Exploration on Power Delay Product of various VLSI Multiplier Architectures Figure 8 Structure of Vedic multiplier. 3. SIMULATION RESULTS: The simulation results are tabulated in Table 1. Parameter Table 1 Simulation Results Array multiplier On the fly Conversion multiplier Vedic Multiplier Power dissipation (mw) Average delay(ns) Power delay product(pj) The power dissipation for array multiplier, On the fly conversion multiplier, vedic multiplier is found to be 7.41 mw, 7.21 mw, 6.95 mw respectively. The power delay product for array multiplier, on the fly conversion multiplier, vedic multiplier is found to be 5.41 pj, 5.04 pj, 4.58 pj respectively. 4. CONCLUSION In terms of power dissipation, Vedic multiplier offers superior characteristics. Vedic multiplier is recommended where speed and power consumption is a major concern. For the multiplication operation, Our ancient Indian Vedic mathematics had given effective algorithms. High performance VLSI architecture for multiplier had realized using vedic mathematics. Vedic multiplier shows better power consumption and better power delay product when compared with the array multiplier and on the fly conversion multiplier editor@iaeme.com

7 S.Karunakaran, Y.Pandurangaiah, Joseph Anthony Prathap and B.Poonguzharselvi REFERENCES: [1] Baran, D, Aktan, M & Oklobdzija, VG 2011, Multiplier structures for low power applications in deep-cmos, IEEE International symposium on Circuits and Systems (ISCAS), p [2] Krishnaveni D, Umarani T.G, VLSI Implementation of Vedic Multiplier with Reduced Delay, IJATER, NCET-Tech, ISSN No: , Volume 2, Issue 4, July [3] Poornima M, Shivaraj Kumar Patil, Shivu kumar, Shridhar KP, Sanjay H, Implementation of Multiplier Using Vedic Algorithm, IJITEE,ISSN: ,Volume-2,Issue-6, May [4] Premananda B.S, Samarth S. Pai, Shashank B, Shashank S.Bhat, Design and Implementation of 8-bit Vedic Multiplier, IJAREEIE, Vol.2,Issue 12,ISSN: , Dec [5] Abu-Khater, I., Bellaouar, A. and Elmasry, M. Circuit techniques for CMOS low-power high performance multipliers, IEEE Journal of SolidState Circuits, Vol.31, No.10, pp , [6] Shah, FA, Jamal, H & Khan, MA 2006, Reconfigurable Low Power FIR Filter based on Partitioned Multipliers, IEEE International Conference on Microelectronics, pp [7] Vinod, AP, Singla, A & Chang, CH 2007, Low power differential coefficients-based FIR filters using hardware optimised multipliers, IET Circuits, Devices & Systems, vol. 1, no. 1, pp [8] Aniket Kumar and Vishikha Comparative Analysis of Vedic & Array Multiplier, International Journal of Electronics and Communication Engineering and Technology, 8(3), 2017, pp [9] R. Kavitha and V. Rajini, Design and Implementation of a High Gain DC-DC Converter with Built-in Transformer Voltage Multiplier Cells. International Journal of Electrical Engineering & Technology, 8(2), 2017, pp [10] ShaziaFathima and Dr. Sardar Ali, Design & Performance of Six Pulse Voltage Multipliers, International Journal of Advanced Research in Engineering and Technology, Volume 4, Issue 3, April 2013, pp editor@iaeme.com