Design and Implementation of an Efficient Vedic Multiplier for High Performance and Low Power Applications

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1 Design and Implementation of an Efficient Vedic Multiplier for High Performance and Low Power Applications Assistant Professor Electrical Engineering Department School of science and engineering Navrachana University, Vadodara ABSTRACT This paper describes the work done towards design and implementation of multiplier modules using high speed architectures based on the concept of Vedic Mathematics. Unlike other Vedic multipliers where entire architecture is based on generating partial products in parallel and adding them, here the partial products for top level entity are adjusted using concatenation operation and are added using single carry save adder. However other entities are based on parallel partial product generation and adding using carry skip technique. This method allows for optimization in terms of speed and total thermal power dissipation. Additionally the multiplier module designed using carry look ahead adder is also presented which also allows for optimization between speed and area. The proposed designs are realized using ALTERA Cyclone V FPGA. Keywords Vedic, Urdhva-Triyagbhyam, Multiplier, Karatsuba. INTRODUCTION Multiplication is the fundamental operation of any processing unit like Digital Signal Processors, Microcontrollers, Microprocessors, FPGA, CPLD etc wherein some of them depend on multiplier most frequently and heavily whereas others are less. For example in many Digital Signal Processing (DSP) applications like convolution, Fast Fourier Transform (FFT) etc multiplication dominates the execution time. Thus the speed of a multiplier in any digital circuit design determines the efficiency of that design. So, it is essential to develop a faster mechanism to implement mathematical functions. Therefore, circuit designers are looking forward for new algorithms & methods to speed up all the arithmetic operations. The word Vedic was driven from the word Veda whichis ancient store-house of all knowledge. Vedic mathematicsprovides the solution to the problem of long computation timeby reducing the time delay needed for the operations to beperformed.vedic mathematics has been formulated on sixteen sutras and thirteen subsutras. These sutras offermagical short cut methods to all basic mathematicaloperations. All the advantages drives from the fact that Vedicmathematics approach is totally different & considered veryclose to the way a human mind works. Vedic mathematics canbe applied to every branch of mathematics includingarithmetic, algebra and geometry. [2] Out of the many techniques (Sutras) available, the proposed design is based on Urdhva-Triyagbhayam technique with certain improvisations while designing. As it had been proved that Vedic multipliers are fast when compared with normal array multiplier or booth multiplier, the work here presents a novel structure comprising use of both carry skip technique and Concatenation operation to design both 8-bit and 16-bit Vedic multipliers which lets optimize both speed and area with minimal thermal power dissipation. VEDIC MULTIPLIER ARCHITECTURE The Urdhva Triyagbhyam sutra is also known as vertical and cross-wire sutra. An illustration of this is given below: 80

2 Fig 1: Illustration of UT sutra The 4x4 multiplication has been done in a single line in Urdhva Triyagbhyam sutra, whereas in shift and add (conventional) method, four partial products have to be added to get the result. Thus, by using Urdhva Triyagbhyam Sutra in binary multiplication, the number of steps required calculating the final product will be reduced and hencethere is a reduction in computational time and increase in speed of the multiplier. [3] 4-BIT VEDIC MULTIPLIER MODULE The 4-bit Vedic multiplier is designed using UT sutra and carry skip technique for partial product generation. In a normal Vedic multiplier, the carry from each partial product addition is given to the next partial product bit calculation. The carries are not only rippled to the next partial product bit calculations but also to the subsequent bits using carry skip technique so as to reduce the carry propagation delay. The architecture is designed using only half adders. [1] Fig 2: 4-bit Vedic Multiplier using carry skip [1] n-bit VEDIC MULTIPLIER MODULE USING CONCATENATION The architecture of n-bit Vedic multiplier is shown in the figure below. The architecture consists of four n/2 bit multipliers used for calculating partial products. 81 Fig 3: Architecture of n-bit multiplier [3]

3 Next the results of these n/2 bit multipliers are adjusted using concatenation operation to have all the partial product terms of equal bit length. The partial product of right most multiplier is concatenated with the partial product of leftmost multiplier and the partial products of middle two multipliers are concatenated with n/2 zeros each. [3] PROPOSED ARCHITECTURE 8 Bit Vedic Multiplier Design - I The proposed architecture combines 4 bit multiplier module designed using carry skip technique and concatenation methodology to design 8-bit Vedic multiplier. Four 4-bit Vedic multiplier modules are used to design 8-bit Vedic multiplier and the partial products generated are first concatenated with zeros so as to keep all the products of equal length. Than they are added using carry save adder to generate rest of the product bits as shown above. This methodology helps to improve the delay performance of our circuit when compared with the other architectures. The delay performance of this design can be further improved, but it would lead to increased chip area and higher thermal power dissipation. Thus this design offers optimization between speed, area and power dissipation. Block diagram of proposed 8 bit Vedic multiplier is illustrated in the figure below: Fig 4: Proposed 8 bit Vedic Multiplier Design I 82

4 The 8 bit input sequence is divided into two 4 bit numbers and given as input to the 4 bit Vedic multipliers as A[3:0] and B[3:0] to V 1, A[3:0] and B[7:4] to V 2, A[7:4] and B[3:0] to V 3, A[7:4] and B[7:4] to V 4. The four multipliers are used to generate intermediate products of 8 bit each, among which Y [7:0] and Z [7:0] are than concatenated with zeros and W [7:0] is concatenated with X [7:4] to generate 12 bits each. These outputs labelled as I [11:0], J [11:0], K [11:0] are further given to 12 bit carry save adder to generate final output bits. The initial four bits are taken directly from the Vedic multiplier V 1. The design encompasses a single adder which leads to reduction in implementation area with less number of LUT s used and also speeds up the partial products addition process. 8 Bit Vedic Multiplier Design II This module of 8 bit multiplier is designed using the carry skip technique of 4 bit Vedic Multiplier, however the design uses carry look ahead adder instead of the suggested Adder in [1]. The CLA module here helps in generating carry bits in parallel at the cost of additional hardware. Thus the 8 bit module here is a fusion of carry skip and carry look ahead which ultimately speeds up our multiplier (comparison is given in results section). Block diagram of proposed design is illustrated in the figure below: Fig 5: Proposed 8 bit Vedic multiplier Design II The above shown 8 bit multiplication is done using four 4 bit Vedic multipliers. The products generated are labelled as M1 M2 M3 and M4, where each one is 8 bit in length. The LSB s from the output of first Vedic multiplier forms the final product term labelled as P [0] to P [3]. M2 and M3 are then used as input to 8 bit 83

5 carry look ahead adder, which uses parallel processing of carry bits to generate partial products. The resulting bits shown as M5, are given to adder 2 which generates product bits from P [4] to P [7]. The carry from adder 2 is given to adder 3 along with M4 and MSB bits of adder 2 labelled as M6 [7:4]. The final MSB for product bits are obtained from adder 3 as P [8] to P [15]. SIMULATION WAVEFORM AND RESULTS Here both the proposed 8 bit Vedic multipliers along with 16 bit Vedic multiplier are simulated using Altera Quartus II software. The designed modules are described using VHDL coding. Further the synthesis along with placement and routing and timing analysis is done using Quartus II and the design is implemented using Altera FPGA Cyclone V family and device 5CGXFC7C6F23C6. Figure 6 below shows simulation of proposed 8 bit Vedic multiplier design II Fig 6: 8 Bit Vedic multiplier Simulation design - II Figure 7 below shows simulation of proposed 8 bit Vedic multiplier design I Fig 7: 8 Bit Vedic multiplier simulation design I Figure 8 below shows simulation of 16 bit Vedic multiplier which is based on the methodology of design I. Here four 8 bit Vedic multiplier modules were used to simulate the design along with concatenation of partial products. 84 Fig 8: 16 Bit Vedic Multiplier simulation

6 The results obtained after synthesis are compared and tabulated below. Here the proposed design II is compared with Premananda B.S. [1] for propagation delay analysis. The module was implemented using ALTERA FPGA of Cyclone V family. Further the device utilization summary post synthesis is also tabulated for analysis. Multiplier type Table 1. Comparison of propagation delay (ns) Normal 8 bit Vedic Multiplier [1] Proposed model Design II Propagation delay Comparison Chart Normal Multiplier [1] Proposed Fig 9: Comparison of Propagation delay for multiplier modules The result of synthesis for Vedic multiplier Design I are tabulated in the sections below where the proposed module is compared with Richa Sharma[3] and Premanada S. [1] for comparison in terms of propagation delay. Here the design is based on both Carry save technique and carry look ahead to generate the partial products quickly and add them. The design was implemented using ALTERA FPGA device of family Cyclone V. Multiplier type Table 2. Comparison of propagation delay (ns) Normal 8 bit Vedic Multiplier [1] Proposed model Design I [3] Propagation delay The Device utilization summary for both the proposed Vedic multiplier modules is given below: Table 3. Comparison of device utilization Multiplier Type Proposed Design - II Proposed Design - I Logic Utilization No. of ALM s needed. No. of Combinational LUT s used Total Fan-out The Thermal power dissipation for proposed design I has also reduced as compared with KunalJadhav[5] and S.V.Mogre [4] as shown in the comparison table below: 85

7 Table 4. Comparison of Thermal power dissipation (mw) Multiplier type [4] [5] Proposed model Design I Thermal Power Dissipation The proposed module dissipates mW at 1.1V V cc, which is far less than other designs. This dissipation is divided into two sections: 1. Core Static Thermal power dissipation = mW 2. I/O Thermal power dissipation = 5.81mW CONCLUSION The paper thus presents a comparative analysis of various Vedic multiplier modules and proposes a novel architecture which utilizes both carry save technique along with concatenation operation to optimize the speed performance of circuit along with area and power requirements. It has also been proved that these devices offer even better delay performance as the number of bits increases. REFERENCES [1] Premananda B.S, Samarth S. Pai., Shashank B. and ShashankS.Bhat Design and Implementation of 8-bit vedic Multiplier. International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering. [2] Jagadguru Swami Sri Bharati Krishna TirthaJiMaharaj Vedic Mathematics. MotilalBanarasidas, Varanasi, India. [3] Richa Sharma, ManjitKaur, Gurmohan Singh Design and Implementation of Optimized 32-bit Vedic Multiplier and Square Architectures. International Conference on Industrial Instrumentation and control. [4] Ms. S.V.Mogre, Mr. D.G.Bhalke Implementation of high speed Matrix Multiplier Using Vedic Mathematics on FPGA International Conference on computing Communication Control and Automation. [5] KunalJadhav, AdityaVibhute, ShyamIyer, R.Dhanabal Novel Vedic mathematics based ALU using application specific Reversibility IEEE Sponsored 9 th International Conference on intelligent systems and control (ISCO). [6] Arshi S, R.K.Sharma An efficient binary Multiplier design for high speed applications using Karatsuba algorithm and UT algorithm. Proceedings of 2015 global conference on Communication Technologies (GCCT 2015). [7] Poornima. M, Shivaraj Kumar Patil, Shivkumar, Shridhar K P, Sanjay H, Implementation of multiplier using Vedic algorithm. International Journal of Innovative Technology and Exploring Engineering (IJITEE). Vol- 2, Issue- 6. [8] G.Ganesh Kumar, V.Charishma, "Design of high speed Vedic Multiplier using Vedic Mathematics Techniques", International Journal of Scientific and Research Publications, Vol- 2, Issue -3, March [9] Dilip Kumar, Abhijeet Kumar, Siddhi, Hardware Implementation of 16 * 16 bit Multiplier and Square using Vedic Mathematics, International Conference on Signal, Image and Video Processing (ICSIVP). [10] Ramalatha M, Thanushkodi K, Deena Dayalan K,Dharani P, A Novel Time and Energy Efficient Cubing Circuit using Vedic Mathematics for Finite Field Arithmetic, International Conference on Advances in Recent Technologies in Communication and Computing, pp