Research Article Volume 6 Issue No. 4

Transcription

1 DOI / ISSN IJESC Research Article Volume 6 Issue No. 4 Design of Combinational Circuits by Using Reversible Logic Circuits S.Rambabu Assistant professor Department of E.C.E Santhiram Engineering College, Nandyal, Kurnool, AP, India ramu.luck@gmail.com Abstract: The growing technologies have increased the demand of high power complexity. In order to get low power consumption, Reversible complexity is used. Reversible logic circuit is widely used in quatanum computing, optical computing and power efficient nano technology. Reversible circuits do not use the information. These are many reversible logic circuits such as MZI, Toffoli gate, Feynman gate. By using this logic gates we can implement the combinational circuits such as multiplexer, demultiplexer, full adder etc; by implementing the combinational circuits with the help of reversible circuits. We obtain low power consumption. The delay is decreased. Keywords: Optical Reversible computing, Mach Zehender Interferometer (MZI), Full Adder, Multiplexer; Decoder; Optical cost. I INTRODUCTION With the rapid growth of portable electronic devices, it is becoming a critical challenge to design low-power, high speed(lphs) circuits that occupy small chip areas. Such studies mostly rely on creative design ideas but do not follow a systematic approach. As consequences, most of them suffer from some different disadvantages. 1) They are implemented with logic styles that have an incomplete voltage swing in some internal nodes, which leads to static power dissipation. 2) Most of them suffer from severe output signal degradation and cannot sustain low voltage operation. 3) They predominantly have dynamic power consumption for non balanced propagation delay inside and outside circuits which results in glitches at the outputs. Therefore, a well-organised design methodology can be regarded as a strong solution for the challenge. It is not tryand-error-driven, which means that is systematically and deliberately aims to the design goals. It also picks circuit components wisely and does not postpone the determination of the circuit characteristics. VLSI chiefly comprises of front design these days. While front end design includes digital design using HDL, design verification techniques the design from gates and design for testability, backend design comprises of CMOS library design and its characterization. The major design steps are different levels of abstraction of device as whole. It is more of a high level representation of the system, The major parameters considered at this level are performance, functionality, physical dimensions, fabrication technology and design techniques. It has to be a trade off between market requirements the available technology and the economical viability of the design. The end specifications include the size, speed, power and functionality of the vlsi system. Gate minimization techniques are employed to find the, simplest or rather the smallest most effective implementation of the logic. While the logic design gives the simplified implementation of the logic, the realization of the circuit in the form of a netlist is done in this step. Gates, transistors and interconnects are put in place to make a list. This again is a software step and the outcome is checked via simulation. The conversion of the netlist into its geometrical representation is done in this step and the result is called as output. This step follows some predefined fixed rules like the lambda rules which provide the exact details of the size, ratio and spacing between components. II.PREVIOUS WORK Combinational circuit is a circuit which we combine we combine the different gates in the circuit, for example encoder, decoder, multiplexer, demultiplexer. Some of the characteristics of the combinational circuits are as follows: 1) The output of the combinational circuits at any instant of time depends on the levels present at the input terminals. 2) The combinational circuits do not have any memory. The previous state of the input does not have any effect on the present state of the circuit. 3) The combinational circuits have n number of inputs and m number of outputs. MULTIPLEXER: Multiplexer is a special one type of combinational circuit. It has a n number of data input and, one outputs m select inputs with 2m=n. International Journal of Engineering Science and Computing, April

2 demand for faster communication is increasing day by day, in order to full fill this MZI switch is used. Fig 1: Internal Diagram of MZI switch DEMULTIPLEXER: A demultiplexer performs the reverse option of a multiplexer i.e., it receives one input and distributed it over several outputs. TOFFOLI GATE: Universal reversible logic gate, named its inverter Tommaso Toffoli. IT means that any reversible circuit can be constructed from toffoli gate. Fig 2; Internal Diagram of Toffoli Gate FULL ADDER: Full Adder is developed to overcome the drawback of Half Adder circuit. It can be add two one-bit numbers A and B, and carry. The full adder is a three input and two output combinational circuit. FEYNMAN GATE: In the previous approach we have high power consumption and loss of information. In order to overcome this problem we are moving to our proposed approach. III.PROPOSED APPROACH In 1973, C.H.Bannet stated that reversible logic can overcome the heat dissipation problems of VLSI circuits. A device is said to be reversible if it satisfies the following conditions: 1) For any deterministic device to be reversible is that its input and output be uniquely retrievable from each other. 2) A device can actually run backwards. In a normal gate input states are lost since less information is present in the output that was present at the input. Some of the reversible logic circuits are MZI, TOFFOLI GATE, FEYNMAN GATE etc; MZI: MZI stands for Mach Zehender Interferometer. It is used to determine the relative phase shift between two beams. The Fig 3: Internal Diagram of Feynman Gate The reversible combinational circuits are: MULTIPLEXER: It is a digital circuit when selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted with outputs. Fig 4: Internal diagram of reversible multiplexer International Journal of Engineering Science and Computing, April

3 Truth Table of Multiplexer DEMULTIPLEXER: At a time only the output line is selected by the select lines and the input is transmitted to the selected output. A demultiplexer is equivalent to a single pole multi way switch. FULL ADDER: Fig: Internal diagram of reversible full Adder The abow diagram represent the full adder that implemented based on one ORGI and one FG revesable gates and the function table for full adder is shown in below Fig 5: Internal Diagram of reversible Demultiplexer Truth Table of Demultiplexer The above table signifies the truth table for Demultiplexer DECODER: Truth Table of Full Adder The below fig shows the implemented diagram for full adder International Journal of Engineering Science and Computing, April

4 IV.RESUT AND ANALYSIS The below all figure shows the resultant waveforms and layout for multiplexer, demultiplexer, Decoder and full adder shown in below Fig 6: Layout of multiplexer Fig 10:layout of Decoder Fig 7: waveforms of multiplexer Fig 11: waveforms of Decoder Fig 8:Layout of Demultiplexer Fig 12:layout of full adder Fig 9: wave forms of Demultiplexer International Journal of Engineering Science and Computing, April

5 implemented MUX,DEMUX, DECODER, FULLADDER circuits and simulated based on Microwindow tool and the resultant waveforms are show in above section and from the above result analysis and tables, concluded that Reversible logic is a best approach to reduce power, area, delay in Digital circuits Fig13:wave forms of full adder The below tables signifies the comparison tables for all implemented circuits. that comparison done between CMOS and Reversible Technique shown in below VI.REFERENCES [I] World's First 2-Billion Transistor Microprocessors Intel Corporation. Feb [Online]. Available: architecture silicon! 2billion.htm?iid=tech_micro+2b. [2] D. H. Allen. S. H. Dhong, H. P. Hofstee, 1. Leenstra, K. J. Nowka, D. L. Stasiak, and D. F. Wendel, "Custom circuit design as a driver of microprocessor performance," ibm J. Res. and Develop., vol. 44, no. 6, pp , Nov [3] P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-performance microprocessor design," ieee J. Solid State Circuits, vol. 33, no. 5, pp , May [4] K. Yelamarthi and c.-i. H. Chen, "Process variationaware timing optimization for dynamic and mixed-staticdynamic CMOS logic," ieee Trans. Semicond. Manuf, vol. 22, no. I, pp , Feb [5] 1. P. Fish burn and A. E. Dunlop, "TlLOS: A posynomial programming approach to transistor sizing," in into Con] Computer Aided Design, 1985, pp Table:Comparision table of all combinational circuits based on CMOS Fig 14: Comparison table of all combinational circuits based on Reversible logic technique From the above tables we can analyze that the reversible logic give better performance compared to Cmos in terms of Power dissipation, area, delay. V.CONCLUSION The growing technologies have increased the demand of high power complexity. In order to get low power consumption, Reversible complexity is used. In this International Journal of Engineering Science and Computing, April