A 1: 128 multiplexing rate Time Domain SQUID Multiplexer
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1 A 1: 128 multiplexing rate Time Domain SQUID Multiplexer D. Prêle, F. Voisin, M. Piat, T. Decourcelle, C. Perbost, D. Rambaud, S. Maestre, W. Marty, L. Montier Low Temperature Detectors - LTD July Grenoble
2 Q & U Bolometric Interferometer for Cosmology - QUBIC Cosmology experiment for B-mode polarization of the Cosmic Microwave Background Bolometric Fizeau interferometer NbSi focal plane imager Interference fringes (synthesized image) 1024 NbSi on 4 wafers ( 2 freq.) C. Perbost A 248 Array for CMB B-mode detection Poster 45cm window / 14 field-of-view 400 back/back horn (looking sky) 400 switches (self calibration) Off-axis Gregorian (combiner) filled array (150/220GHz) A. Tartari QUBIC : A Fizeau interferometer for B-Modes Thursday 23 - Session 5 Present work, sub-system : 256 s, 256 SQUIDs (TDM), 2 ASICs (LNA + bias) prele@apc.in2p3.fr 2 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
3 Outline 1 : 128 TDM multiplexer topology 1 1 : 128 TDM multiplexer topology 2 SQUID stage Cryogenic integrated circuit 3 prele@apc.in2p3.fr 3 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
4 Outline 1 : 128 TDM multiplexer topology 1 1 : 128 TDM multiplexer topology 2 SQUID stage Cryogenic integrated circuit 3 prele@apc.in2p3.fr 4 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
5 readout topology based on 2D multiplexing scheme Vout R FB bias mux(4 : 1)LNA + Integrator C Bias mux(32 : 1)diff. SQUID bias 32 prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
6 readout topology based on 2D multiplexing scheme Vout R FB bias mux(4 : 1)LNA + Integrator C Bias mux(32 : 1)diff. SQUID bias 32 prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
7 readout topology based on 2D multiplexing scheme Vout R FB bias mux(4 : 1)LNA + Integrator C Bias mux(32 : 1)diff. SQUID bias 32 prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
8 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
9 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
10 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
11 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
12 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
13 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
14 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
15 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
16 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias 32 lines prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
17 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
18 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
19 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
20 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
21 readout topology based on 2D multiplexing scheme Vout R FB bias C Bias prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
22 readout topology based on 2D multiplexing scheme Vout R FB bias mux(4 : 1)LNA + Integrator C Bias mux(32 : 1)diff. SQUID bias 32 prele@apc.in2p3.fr 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
23 Outline 1 : 128 TDM multiplexer topology SQUID stage Cryogenic integrated circuit 1 1 : 128 TDM multiplexer topology 2 SQUID stage Cryogenic integrated circuit 3 prele@apc.in2p3.fr 6 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
24 SQUID stage Cryogenic integrated circuit Time domain SQUID multiplexer for QUBIC QUBIC Readout sub-system : 256, 256 SQUID, 2 ASIC Sub-system : NbSi Wafer (300 mk) SQUIDs (1K) + 2 ASICs (40K) Integration of this sub-system in a dilution fridge for readout test prele@apc.in2p3.fr 7 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
25 SQUID stage Cryogenic integrated circuit SQUID glued and wire bonded on a PCB StarCryoelectronics SQ680 specific design. Solder plated track (no parasitic resistances) Shunt resistor and filter devices prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
26 SQUID stage Cryogenic integrated circuit 32 SQUIDs glued and wire bonded on a PCB prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
27 SQUID stage Cryogenic integrated circuit 32 SQUIDs glued and wire bonded on a PCB prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
28 SQUID stage Cryogenic integrated circuit 64 SQUIDs glued and wire bonded on a PCB prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
29 SQUID stage Cryogenic integrated circuit 96 SQUIDs glued and wire bonded on a PCB prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
30 SQUID stage Cryogenic integrated circuit 128 SQUIDs glued and wire bonded on a PCB prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
31 SQUID stage Cryogenic integrated circuit 128 SQUIDs glued and wire bonded on a box prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
32 SQUID stage Cryogenic integrated circuit SQUIDs glued and wire bonded on a box prele@apc.in2p3.fr 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
33 SQUID stage Cryogenic integrated circuit ASIC Stage (Application Specific Integrated Circuit) 9 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
34 SQUID stage Cryogenic integrated circuit SiGe ASIC for cryogenic 1 :128 TD SQUID M BiCMOS SiGe ASIC 350nm AMS technology 32 SQUID bias 33 Row MUX 3 I SQ ADR Serial link mux output 1 : V CM I Amp CM FB OS FB Diff Mux Vdd Gnd 1 SQUID rows addressing : Biasing through capacitors with AC multiplexed current sources (1 : 32) 2 Low noise amplifier with multiplexed inputs : FLL preamplifier column mux. (1 : 4) 3 Digital addressing circuit controlled by external Ck Ck input (from SQUID) prele@apc.in2p3.fr 10 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
35 Outline 1 : 128 TDM multiplexer topology 1 1 : 128 TDM multiplexer topology 2 SQUID stage Cryogenic integrated circuit 3 prele@apc.in2p3.fr 11 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
36 Multiplexed time line 1 :128 multiplexing rate prele@apc.in2p3.fr 12 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
37 Multiplexed time line 1 :128 multiplexing rate The ASIC allows to reduce the part of the array readout prele@apc.in2p3.fr 12 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
38 Flux Locked Loop (FLL) in multiplexed mode FLL to linearize the "sine-like" SQUID transfer function Analog FLL bias φ ext V out R fb φ fb prele@apc.in2p3.fr 13 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
39 Flux Locked Loop (FLL) in multiplexed mode FLL to linearize the "sine-like" SQUID transfer function Multiplexed analog FLL bias φ ext V out R fb φ fb Multiplexed mode : FLL operating point jump a φ 0 between samples prele@apc.in2p3.fr 13 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
40 "digital" FLL 1 : 128 TDM multiplexer topology φ ext bias G R fb error signal 0 ADC t 1 fb value (memory) DAC φ fb digital FLL operating point storing Warm readout/acquisition (FPGA + ADC/DAC) Realtime feedback compensation implemented into the FPGA Series link with ASIC Power supply ASIC IRAP collaboration prele@apc.in2p3.fr 14 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
41 Demultiplexing software IRAP collaboration 15 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
42 Demultiplexing software IRAP collaboration 15 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
43 Conclusion and outlook Implementation and operation of a 1 : 128 TDM 2D multiplexing : SQUID stage + ASIC stage Demultiplexing and digital FLL in a FPGA To be done soon : 1 Increase of multiplexing frequency 2 Noise measurements without aliasing prele@apc.in2p3.fr 16 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
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