Reflective Electron Beam Lithography: Lithography Results Using CMOS Controlled Digital Pattern Generator Chip

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1 Reflective Electron Beam Lithography: Lithography Results Using CMOS Controlled Digital Pattern Generator Chip Thomas Gubiotti 1, Jeff Sun 1, Regina Freed 1, Françoise Kidwingira 1, Jason Yang 1, Chris Bevis 1, Allen Carroll 1, Alan Brodie 1, William M. Tong 1 ; Shy-Jay Lin 2, Wen-Chuan Wang 2 ; Luc Haspeslagh 3, Bart Vereecke 3 1 KLA-Tencor, Milpitas, California (USA) 2 Taiwan Semiconductor Manufacturing Co. Ltd., Hsinchu City (Taiwan) 3 IMEC, Leuven (Belgium) ABSTRACT Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons are generated in a flood beam via a thermionic cathode at kev and decelerated to illuminate the DPG chip. The DPG-modulated electron beam is then reaccelerated and demagnified x onto the wafer to be printed. Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be presented. Keywords: electron beam, direct write, lithography, roadmap, REBL, digital pattern generator 1. INTRODUCTION The Reflective Electron Beam Lithography (REBL) tool currently under development at KLA-Tencor for DARPA (MTO) is designed for custom ASIC processing. Corporate development efforts over the past several years have also focused on developing a tool for high volume manufacturing (HVM). The system currently under development is targeting critical patterning steps at the sub 16 nm half pitch node at a cost of ownership equivalent to 193nm immersion optical lithography. As noted in earlier work 1, the patented, reflective electron optic or Digital Pattern Generator (DPG) enables the REBL system to produce a massively parallel lithographic exposure using well over a million electron beams. The DPG is a CMOS ASIC chip (from TSMC) with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~1Tbps). The lens elements on the DPG are fabricated at IMEC (Leuven, Belgium) under IMEC s CMORE program. To drive throughput and reduce overall system risk, the REBL team has plans to implement multiple DPGs (multiple-columns) and replace a Alternative Lithographic Technologies V, edited by William M. Tong, Douglas J. Resnick, Proc. of SPIE Vol. 8680, 86800H 2013 SPIE CCC code: X/13/$18 doi: / Proc. of SPIE Vol H-1

2 previously planned rotary stage concept with a dual action, linear stage technology. This new multi-column and linear stage architecture has the potential to produce wafer throughputs similar to current 193 nm immersion lithography systems. The new linear stage design also has the added benefit of reduced system vibration and cancellation of stage acceleration forces. Electron Beam Lithography (EBL) had not been under serious consideration for HVM (except for mask making 2 ) because of insufficient throughput. Electron Beam Direct Write (EBDW) has found a niche in applications which require both high resolution, quick-turn-around, 4,5 and high customization (i.e., maskless), such as fabrication of lowvolume prototypes for cutting edge R&D. In the 1990s, SCALPEL 7 and PREVAIL 8,9 were two competing electron projection lithography programs that demonstrated very good progress, but their failure is partly attributable to their adoption of a mask. This brought on technological challenges, some of which were similar to those for optical lithography while others were unique to e-beam projection. Advances in MEMS technology in the past decade enabled the pixilation of an electron beam into thousands to millions of beamlets. An electron-optical mask could be replaced by an electron-optical MEMS. Thus the high flexibility and low cost of maskless e-beam lithography can be maintained without sacrificing throughput and resolution. Currently, there are three major maskless EBDW programs under development: MAPPER 10, IMS 11, and REBL 12,13. This report summarizes work for extending the REBL technology for HVM 10 nm technology node (logic, 16 nm HP). The near-term goal for the REBL tool is to direct write 5-7 wafer layers per hour for the 45 nm node. Figure 1 shows a schematic layout of the REBL electron beam optics integrated to a linear stage concept that will be part of a HVM system. Digital Pattern Generator Illumination Optics Projection Optics EXB Filter Electron Gun i I e Demag Optics l'iar I.-Multiple Wafer Linear Stage Figure 1: REBL linear stage concept; multiple wafer stage, DPG, and beam optics 2. PLATFORM REVIEW Over the past year, KLA-Tencor has investigated several different stage and e-beam column configurations that have the potential for HVM for the 10 nm technology node (logic, 16 nm HP). Since a single REBL column will not provide the throughput needed for HVM the REBL team continues design work for a multi-column prototype system (Figure 2). As the number of columns increases many other system requirements are significantly reduced. A larger number of columns allows for a lower writing speed, reducing the requirements on current through a single column, stage speed, etc. The key then, is to make the electron optics small, simple, reliable, and inexpensive enough to replicate many times per Proc. of SPIE Vol H-2

3 cluster. Increasing the number of columns allows REBL to concentrate complexity into subsystems which scale well, such as the DPG, rendering algorithms and stage positioning and beam positioning algorithms. The DPG leverages CMOS technology and infrastructure, which scale with device node. The rendering algorithms leverage HPC infrastructure, which also improves with increasing shrinks of chip design. Our stage control and beam positioning algorithms leverage high performance computing, digital signal processing, and FPGA. In contrast, things which are traditionally complex in optical lithography systems are comparatively simple in e-beam lithography. For example, the optics, stage and source are all readily available. Figure 2: REBL HVM Concept; showing 36 columns (in groups of six) 3. REBL DIGITAL PATTERN GENERATOR During the past year, KLA-Tencor has worked closely with TSMC and IMEC (Leuven, Belgium) to produce functional CMOS DPGs. The latest DPG chips (248 x 4096 electron-optical mirror array at 1.6 µm pitch) from IMEC have been integrated to the 75 kv column and fine tuned to optimize imaging in both PMMA and Chemically Amplified Resist (CAR) films (Figure 3). As can be seen in Figure 4, significant imaging performance improvements have been recently achieved for the DPG chip. Here we discuss improvements in two key areas of the DPG fabrication process which have resulted in the enhanced uniformity, contrast, and functionality improvements. Figure 3: REBL DPG with CMOS and Lenslet array (248 x 4096) mounted to a custom ceramic substrate Proc. of SPIE Vol H-3

4 Figure 4: DPG Performance Jan 2012 (left) and Sept 2012 (right). Aerial image viewed via mag stack and YAG screen The first improvement is in the passivation layer that lies between the CMOS circuitry and the manufactured MEMS lenslets. Due to process tool limitations, earlier iterations of the DPG chip only had 120 nm of silicon dioxide passivation between these two parts of the chip. Non-performing segments of the lenslets were frequently observed. Testing of failed chips demonstrated that the 120 nm silicon dioxide passivation layer was insufficient to prevent mechanical and electrical breakdowns between the CMOS and lenslets. A new process was implemented and this passivation layer is now 1 µm thick. The second improvement is in the charge drain coating in the lenslets. The electrode layers in the lenslets are separated by silicon dioxide insulator layers which are 1µm thick (Figure 5). We found that a charge will build up on the silicon dioxide when the chip is exposed to the electron beam. This charge will affect the electron-optical properties of the lenslets and prevent their proper operation. 1.6pm pitch 111Woomt E liewoomr Figure 5: Cross section of MEMS lenslet structure showing electrode planes separated by silicon dioxide insulator (white) To prevent this problem, a charge drain coating is to be applied to the lenslet walls. This coating needs to have an electrical resistance high enough to effectively drain electrons from the silicon dioxide, but low enough not to shortcircuit successive electrode planes which are at different voltage potentials. We calculated that a 14 nm coating with a resistivity of ~10-7 ohm-cm would lead to optimal performance of the lenslets. Other required characteristics are that the Proc. of SPIE Vol H-4

5 film be conformal to the high aspect ratio features, have a precisely controllable thickness, not exceed 300 C deposition temperature, and be stable in vacuum under 25MV/m electric fields. REBL had previously used a homogeneous mixture of two binary oxides deposited via Atomic Layer Deposition (ALD) for this purpose. These films were tunable in resistivity and met all the requirements except stability. Experimental testing found that under the high electric fields in the lenslets, these materials undergo slow electrochemical reduction, resulting in a drop in resistivity of several orders of magnitude over a few days. Due to this issue, a new material had to be found. The solution for charge drain coating consists of molybdenum oxide nanoclusters embedded in alumina (Figure 6). This material was co-developed with Argonne National Laboratories (ANL) and meets all the requirements for the charge drain coating resistivity. Moreover, the system is stable under vacuum and high electric fields. Data from testing under column conditions is shown in Figure 7, demonstrating the markedly improved stability of the new charge drain coating. A detailed paper by KLA-Tencor and ANL on this charge drain coating will be forthcoming. Figure 6: MoO 3-x nanoclusters (black) embedded in Al 2 O 3 imaged via TEM 1. E E+08 = _ - Homogeneous binary oxide - MoO3 x nanoclusters embedded in Al2O3 1. E+07 Mo03 -x nanoclusters: stable on colu (One of our chips has been operatingsinc; Homogeneous binary oxides: ra degradation short life 1. E E Time (hrs) Figure 7: Charge drain coating resistivity vs. time under column conditions Proc. of SPIE Vol H-5

6 As a result of these technological improvements, the imaging performance of the DPG chip has been greatly improved. CMOS controlled chips have shown multi-month stability on column with on:off contrast of up to 47:1. This is more than sufficient for lithography and the chips are currently being used for printing in PMMA and CAR. The chips are also capable of printing in Temporal Dose Integration (TDI) mode on a moving stage using grayscaling. il 1 /1 1 /1 1\ H 1\ 11 IN /1 1\ /1 1 \ /1 1\ /I IN i1 /1 IN /1 1\. l\ ID IL. IL, IL CI I I ILI ILI ILI ILI ILI ILI ILI ILI ILI ILI ILI Ir encor K t4 rencor K K LJ, irencor K KL4 encor K / K KL4)encor K K, entor K Figure 8: Test patterns on functional CMOS DPG chips imaged via a mag stack below the stage. Contrast up to 47:1 has been achieved. For future work at the 16 nm HP logic node the team is in the process of building a 100 kv column that will operate with a beam current >1 µa. The team is also working on a DPG3 version that will have a 248 x 4096 lenslet array with integrated data compression that can be addressed in rows. These DPG modifications will enable the DPG to write data in both directions which is needed for HVM applications. 4. LITHOGRAPHY RESULTS The third generation REBL column has now been integrated with a precision controlled wafer stage at KLA-Tencor (Figure 9). The team is currently running both static and dynamic (moving wafer stage) TDI lithography exposures using both PMMA and CAR films. With a 75 kev column (and 85X demagnification) the REBL team has produced static prints several different contact arrays down to a 28 nm half pitch (Figure 10). This print serves as a test of ultimate column resolution for Column 3 and met its original designed goals (32-28nm HP lower design limit). Proc. of SPIE Vol H-6

7 I. 3rd Generation Column 75kV source 85X demag 18.7nm pixel wafer Beam current 200nA - 1 wafer DPG2 Chip 4096 x 248 pixel array CMOS controlled 2.5V switching voltage FMaglev Stage Demo Platform 6 wafer stage I. Under -stage mag stack I Direct viewing of aerial image Figure 9: Experimental setup and conditions for lithography results 35nm HP 28nm HP Figure 10: Static printed hole arrays showing contact holes at 37 nm and 28 nm half pitch in PMMA (200 na beam current at wafer plane) Initial printing of patterns in TDI mode (on a moving stage) is shown in Figure 11. These are 120 nm chevrons printed at 300 na wafer plane beam current in PMMA. Printing direction is from the bottom to the top of the frame. These results are the first successful test of all aspects of the TDI printing system: CMOS DPG, rendering, data clocking, and stage metrology. The print resolution and LER for these prints are not yet meeting targets, however, due to electrical noise on the system that still needs to be identified and eliminated. This work is currently underway and is expected to allow the system to achieve 45 nm HP lithography in the coming months. Additional test print results are shown in Figure 12. Proc. of SPIE Vol H-7

8 -KLA- TENCDN CD SEM v v v tv / `7 N r A r V V \../../k//\\ V^V^` ^V^ Micron : Figure 11: 120nm HP dense chevrons printed on a moving stage in TDI mode, 300nA total beam current at wafer plane 125nm CD, 17 NClcm2 CAR, 300nA 92nm CD, PMMA, INA 120nm CD, PMMA, 500nA Figure 12: Additional TDI test prints in negative CAR and PMMA Der: O.4000om As a further demonstration, a device test pattern was obtained from an IMEC publication 14 consisting of a combined contact/metal pattern from a finfet device. This pattern was scaled to 100 nm HP node so that it could be printed on the REBL system given the current system noise limits (Figure 13). This is a lithographically challenging pattern because of the significant differences in pattern density between the isolated contacts and the dense metal. By using grayscale dosing, REBL is able to optimize the aerial image to print both patterns at the same time. Proc. of SPIE Vol H-8

9 100nm FinFET 6 -T SRAM Hole + Metal Level GDS (Scaled to 100nm HP) Figure 13: Combined contact/metal finfet pattern and scaled 100nm GDS version Figure 14 shows the GDS file rendered into a dose map by the KLA-Tencor EDGE software, which is a package which performs rendering, dose assignment, proximity correction, and backscatter correction for REBL prints. Each pixel in the image represents one pixel at the wafer plane, and the gray level corresponds to the 5-bit dose: with white being equivalent to dose zero and black to dose level 31. These data are then sent to the DPG chip and clocked across the chip in synchronization with the stage. As the wafer moves beneath the pattern, the appropriate bit blocks in the DPG chip are illuminated such that the pixels on the wafer receive the appropriate cumulative dose level from the DPG. A snapshot of the scrolling pattern on the DPG is also shown in Figure 14. DPG, wafer : :4:i,:4:....1:.1:.1:. : :4 ::..1:.1:.1: : :.1:. :4,: :4. : : :i; :so...1:.1:.1:...1:.1:.1:. : : o,í :1. White = dose Ivl 0, Black = dose lvl 31 Figure 14: Pixel grayscale dose assignments via EDGE software (left), mag stack image of DPG with scrolling grayscale pattern (right) Figure 15 shows print results from this test pattern printed in TDI mode on Column 3. CAR with 17 µc/cm 2 sensitivity was used and total beam current was 200 na at the wafer plane. These results show that REBL is capable of printing arbitrary device patterns on a moving stage in CAR. Ongoing work is being done to further improve the system, such as Proc. of SPIE Vol H-9

10 in isolating and removing electrical noise, in order to enable us to print patterns with a target 45 nm HP resolution on this system. Figure 15: 100nm HP Contact / Metal Test Pattern Print in CAR, wafer plane 5. SUMMARY We have demonstrated that the REBL architecture has the potential to provide a HVM solution at 16 nm and beyond, and our throughput calculations support current design decisions. KLA-Tencor optical simulations support HVM capability through at least the 16 nm HP node (logic). We described improvements in CMOS controlled DPG performance to the point where the chips are usable for arbitrary-pattern lithography. TDI printing on a moving wafer stage has produced a wide variety of grayscaled lithography patterns at 100 nm HP. Further work needs to be done to reduce electrical noise and achieve our full resolution entitlement. 6. ACKNOWLEDGEMENTS This project is supported by DARPA and KLA-Tencor under the DARPA Agreement No. HR The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. The authors wish to thank the staff at DARPA, SPAWAR, NRL, and MIT-Lincoln Laboratory for their technical support and many helpful suggestions. Thanks to ANL for their assistance in development of the charge drain coating. Thanks to DI^2 for continued technical support. REFERENCES 1) R. Freed, T. Gubiotti, J. Sun, A. Cheung, J. Yang, M. McCord, P. Petric, A. Carroll, U. Ummethala, L. Hale, J. Hench, S. Kojima, W. Mieher, C. Bevis, Reflective electron-beam lithography performance for the 10 nm logic node, BACUS, ) R. Herriott, R. J. Collier, D. S. Alles, and J. W. Stafford, IEEE Trans.Electron Devices 22, 385, ) Kretz et al., Microelectron. Eng. 85, 792, ) Moore, G. Caccoma, H. Pfeiffer, E. Weber, and O. Woodard, Electronics 54, 138, ) C. Pfeiffer, Solid State Technol., 27, 223, ) Maruyama et al., Proc. SPIE , Proc. of SPIE Vol H-10

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