Predicting Package Level Failure Modes in Multilayered Packages

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1 Predicting Package Level Failure Mdes in Multilayered Packages Dr. Gil Sharn, February 18, Virginia Manr Rd Ste 290, Beltsville MD

2 Speaker Bi: Research fcus: Mechanical reliability f electrnic systems and cmpnents Multidisciplinary reliability f cmplex electr mechanical systems Characterizatin and mdeling f material behavir Physics f failure f electrmechanical and MEMS system Mechanical perfrmance f flip chip packages Dctral research Slder reliability MEMS structures characterizatin Embedded cmpnents failure analysis Particle beam acceleratr mechanical fatigue. Experience at Amkr technlgy Advanced prduct develpment grup as senir engineer Analysis f chip-package interactins Ph.D, Mechanical Engineering (University f Maryland) Sales cntact: Tm O Cnnr tcnnr@dfrslutins.cm 9000 Virginia Manr Rd Ste 290, Beltsville MD

3 Questin Everything I want yu t remember that everything I am saying may be wrng and I want yu t questin everything that I m saying. -Nathan Myhrvld Frmerly Chief Technlgy Officer at Micrsft 9000 Virginia Manr Rd Ste 290, Beltsville MD

4 Intrductin Package technlgy is cnstantly imprving in rder t keep up with the advances in silicn technlgy. Multi layered packages exhibit several failure mdes that can be predicted using mdern sftware tls This paper prvides a methdlgy fr creating a highfidelity mdel f the interpser with all the cnductr gemetries. The tw failure mdes that are explred with this mdel are package warpage predictin due t actual cpper imbalance and filled micrvia delaminatin Virginia Manr Rd Ste 290, Beltsville MD

5 The substrate mdel was created frm the multi-chip mdule (MCM) files f a 25 by 25mm creless substrate. Generating the Mdel Examples f multi chip mdules: Surce: ACME Systems, ARM9 Linux Embedded Mdule, Aria G25 riag25 Surce: Rick Grigalunas, Design Engineers! 1 Mre Reasn T Use Bare Die. ES Cmpnents Blg March 19, 2015 Surce: Eric Bgatin, Radmaps f Packaging Technlgy 1997, Integrated Circuit Engineering Crpratin, ISBN: A 15 by 15mm piece f the substrate was cut ut fr this investigatin. A three dimensinal mdel f the substrate was created using the Sherlck tl. Every segment f gemetry is mdeled fr every trace and material prperties are assigned autmatically by the sftware. The drill hles fr every layer are als created and the whle layered mdel is exprted t the Abaqus cmputer aided engineering tl Virginia Manr Rd Ste 290, Beltsville MD

6 Mdel Meshed in Abaqus Bundary cnditins are applied and the whle mdel is meshed inside Abaqus. The resulting mdel fr the tp and bttm layer f the substrate are shwn belw Abaqus FEA is a sftware suite fr finite element analysis and cmputer-aided engineering Virginia Manr Rd Ste 290, Beltsville MD

7 Detailed Gemetry The mdel can be mdified t perfrm predictins fr several different phenmena because each trace and via has a selectable gemetrical entity. The figure shws a single trace in the mdel after it has been meshed. The laminate and resin material is invisible 9000 Virginia Manr Rd Ste 290, Beltsville MD

8 The analysis is this prject is cncentrated n predicting mechanical perfrmance Analysis Objectives The mdel can easily be cnverted t perfrm electrmagnetic, thermal and multi-physics simulatins. The image illustrates the detailed crss sectin f several vias. Stacked Via Buried Via Thrugh Via Flange The level f detail shws Flanges Buried vias Different cpper layer thicknesses Stacked vias This example emplys a stacked via structure withut staggered vias 9000 Virginia Manr Rd Ste 290, Beltsville MD

9 The Mdel Characteristics The mdel has 2,851,604 ndes and 2,044,465 elements. The mdel includes tw materials. The cpper material is istrpic and linear elastic and applied t the traces and vias. The buildup material is rthtrpic. Sme BGAs will have laminate layers The ne in this analysis is creless and the entire material is presumed t be buildup Surce: Virginia Manr Rd Ste 290, Beltsville MD

10 Predicting Package Warpage Excessive warpage can hinder the creatin f slder jints when a die is attached t the pads Malfrmed slder jints can lead t a higher prbability f cracks frming in the jints. Package warpage is caused by cpper imbalance between the tw sides f the substrate stackup Predictin f package warpage can be perfrmed using effective prperties and simpler mdels An accurate mdel was useful fr addressing the warpage issue successfully [4]. The detailed mdel can prvide infrmatin abut lcalized effects f each via [4] Li, Yuan. "Accurate predictins f flip chip BGA warpage." Electrnic Cmpnents and Technlgy Cnference. IEEE; 1999, Virginia Manr Rd Ste 290, Beltsville MD

11 Examples f Pssible Issues Caused by Warpage Surce: Raiy Aspandiar (Intel), FCBGA Package Warpage HDP User Grup meeting 9000 Virginia Manr Rd Ste 290, Beltsville MD

12 Warpage Plt This figure illustrates the displacement magnitude The warpage analysis was perfrmed fr a temperature f -55 C and 260 C, with the reference temperature 25 C 9000 Virginia Manr Rd Ste 290, Beltsville MD

13 Predicted Diagnal Warpage At the high temperature, the diagnal warpage is predicted t be 55µm r 2.1 mils as shwn This mdel is verkill fr a simple warpage calculatin! 9000 Virginia Manr Rd Ste 290, Beltsville MD

14 A Simpler Apprach Warpage mdeling alng with substrate traces is bad fr cmputatinal efficiency. Prhibitively expensive Large packages Substrates with many metal levels. Surce: Siva Gurrum, Mechanical Mdeling Advances Imprve Semicnductr Packaging, Electrnic Design, Jun 3, Virginia Manr Rd Ste 290, Beltsville MD

15 This analysis culd be perfrmed using effective prperties r layered mdels Warpage Analysis It is mre challenging t btain the warpage effect n individual vias. The image belw shws the ut-f-plane directin defrmatin This plt indicates that wherever there are plated vias, the utf-plane CTE mismatch f the buildup and cpper is causing a small difference in lcalized defrmatin. This finding wuld be difficult t btain fr a creless substrate withut using the high fidelity trace and via mdel Virginia Manr Rd Ste 290, Beltsville MD

16 Micrvia Delaminatin and Cracking Stresses Micrvias create the electrical cnnectin between cpper planes and pads in substrates They are cmmnly used in packages with high input/utput density and creless substrates are n exceptin They can be filled r unfilled They can be stacked, staggered r buried The image shws a cracked via flange due t CTE mismatch between the cpper and the buildup. The lcatin f the micrvias and the shape f the stack has been shwn t have an effect n micrvia reliability Stress predictins using finite element mdels have been used t predict these stresses in simplified mdels [8]. [8] Ning, Yan, Michael H. Azarian, and Michael Pecht. "Influence f Plating Quality n Reliability f Micrvias." IPC APEX Exp, Virginia Manr Rd Ste 290, Beltsville MD

17 Micrvia Stresses at the Free Surfaces The stresses predicted by the mdel will allw the substrate designer t highlight prblematic areas befre ging t prductin. This mdel nly prvides linear elastic stresses f the cpper structures but it can easily be mdified t capture fatigue effects. The results shw that the shape f the stack has an effect n the stresses in the cpper. It is easier t cncentrate n singular vias rather than using a design rule when a stress map exists fr all the vias and pads Virginia Manr Rd Ste 290, Beltsville MD

18 Micrvia Stresses at the Free Surfaces Red areas are abve the ultimate stress f electrplated cpper Predicted t have a higher prbability f cracking. The traces have a higher stress than the substrate underneath The pads that d nt have a via underneath are at a relatively lw stress and act as a stress redistributin layer fr the slder attach. Bttm Tp 9000 Virginia Manr Rd Ste 290, Beltsville MD

19 Micrvia Pad Design The micrvia stack and pad design causes a lwer stress state n ne pad cmpared t the ther Dg-bne design is a standard ruting pattern fr high density substrates fr this reasn The results shw the added advantage fr cpper stress This als alleviates stress frm the slder balls after assembly 9000 Virginia Manr Rd Ste 290, Beltsville MD

20 Stacked Micrvia Stresses The cpper stress at the free surfaces are nly ne part f the stacked via. The vias have structures that g thrugh the entire substrate and the stresses can be higher in the middle f the stack than the flanges. The stress field induced by differential thermal expansin in the via is threedimensinal in nature [1]. We need t cmpare the Vn-Mises stress with the first principal stress in rder t lk at the interfaces f the stacked vias. The Vn-Mises stress is apprpriate when lking at the ductile failure f cpper at the flanges and barrel but the interfaces between vias are mre susceptible t brittle fracture [3]. The Vn-Mises stress plt shws the stress distributin in a stacked via. The high stress regins are at the bttm interface, an inner interface and the flange. [1] Suk-Kyu Ryu, Kuan-Hsun Lu, Jay Im, Rui Huang and Paul S. H, Stress-Induced Delaminatin Of Thrugh Silicn Via Structures in AIP Cnf. Prc. 1378, 153 (2011); di: / [3] Ming-Han Wang, Mei-Ling Wu Therm-mechanical Stress f underfilled 3D IC packaging IEEE EurSimE, 7-9April, Virginia Manr Rd Ste 290, Beltsville MD

21 Myers, Alan M., et al Explanatin f Stresses As a result f different thermal expansin cefficients f the metal intercnnects, vias, and insulating layers, the via cnnectins are subjected t large amunts f stress as the device is temperature cycled. Varius residues cnsisting f flurides and xides, frmed during the via etch prcess, are generally left at the interface prir t via metallizatin. These flurides and xides are generally brittle materials and when subjected t large amunts f thermal stress, crack and cause via delaminatin. Surce: Myers, Alan M., et al. "Via hle prfile and methd f fabricatin." U.S. Patent N. 5,470, Nv The Via interface is mre susceptible t brittle fracture 9000 Virginia Manr Rd Ste 290, Beltsville MD

22 First Principle Stress Plt fr Stacked Via The figure belw shws the first principle stress in the same stacked via as previusly shwn. The tw plts can be cmpared t shw that the high stress in the via t pad interface is f greater cncern fr causing brittle fracture. Failure analysis perfrmed at Intel crp. (ADT) claims that via delaminatin ccurred at the interface between the first electrlytic Cu and electrless Cu [11]. The first principal stress plt indicates that the interface is laded in the tensile directin and predicts this failure mde. The Vn-Mises plt indicates that while the flange is mre susceptible t ductile mdes f failure it is nt at risk fr brittle fracture. [11] Yeh, Hwai Peng, et al. "Flip chip pin grid array (fcpga) packaging technlgy." Electrnics Packaging Technlgy Cnference, 2000.(EPTC 2000). Prceedings f 3rd. IEEE, Virginia Manr Rd Ste 290, Beltsville MD

23 Hw Des this Help Designers The stress plts fr the substrate enable the bard designers t predict many reliability issues. Nt just warpage and Via delaminatin The high-fidelity mdel prvides the predictive capability Allws designers t adjust the layut befre any manufacturing has taken place Virginia Manr Rd Ste 290, Beltsville MD

24 Cnclusins Making a full three dimensinal finite element mdel used t be a difficult and lengthy prcess. Detailed trace apprach used t be prhibitively expensive fr large packages and substrates with many metal levels [2]. Expert mdelers spent many hurs t create the mdels frm layut files. It is mre efficient t allw sftware t create the high fidelity substrate mdel autmatically. Autmatin allws the reliability experts, wh need nt be mdeling experts, t directly interact with the substrate mdel. Surce: Gurrum, Siva, Mechanical Mdeling Advances Imprve Semicnductr Packaging in Electrnic Design, Jun Virginia Manr Rd Ste 290, Beltsville MD

25 Cnclusins (cntinued) The stresses in the filled micrvias are shwn t be affected by the stack prperties. Bth ductile and brittle failures can be predicted using this mdeling methd. The Vn-Mises stresses at the flange f the vias are indicative f the ductile cracks. The first principal stress at the via and pad interfaces are predicting a high prbability f delaminatin due t brittle fracture. The stresses in the traces are als helpful in designing substrates that can decrease lcalized stresses using different cpper trace gemetries. All three cpper stress predictins were made pssible by the high fidelity mdel f DfR s Sherlck Sftware 9000 Virginia Manr Rd Ste 290, Beltsville MD

26 Highlights (If yu remember nthing else ) This prject highlights the advantages f using autmatin f mdel creatin t imprve mdeling techniques. The cnstant demand fr imprved cmpnent packaging is driving the demand fr imprved mdeling techniques. The advanced Sherlck sftware trace mdeling capabilities imprve the mdeling capabilities while shrtening the mdel creatin time Virginia Manr Rd Ste 290, Beltsville MD

27 Thanks Greg Caswell and Gil Sharn DfR Slutins Virginia Manr Rd Ste 290, Beltsville MD