DPC Wafer Level Packaging

Transcription

1 JANUARY/FEBRUARY 2016 Vol. 43 No. 1 DPC Wafer Level Packaging Cost Analysis of Flip Chip Assembly Processes... Qualification of a Low Cure Polymer... Resolution and Resist Profile Considerations... IMAPSource Trending page 26

2 SAVE THE DATE! IMAPS 12th International Conference and Exhibition on Device Packaging The Largest 2016 Conference Dedicated to... Interposers, 3D IC & Packaging; Flip Chip, Wafer Level Packaging & Fan-Out; SiP & Engineered Micro Systems/Devices (including MEMS & Sensors) March 14-17, 2016 We-Ko-Pa Resort and Conference Center (also known as Radisson Fort McDowell Resort & Casino) Scottsdale/Fountain Hills, Arizona - USA For more information, please visit:

3 JANUARY/FEBRUARY 2016 Features Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Amy Palesko Lujan Qualification of a Low Cure Polymer for Fan-in Applications B. Rogers, R. Valencia, K. Quilaton, S. Jayaraman, M. Almonte Resolution and Resist Profile Considerations for Advanced Packaging Lithography Doug Shelton s6 s12 s16 On the Cover: Courtesy of Canon. Canon steppers utilize a multi-channel Optical Tilt Focus (OPTF) System that performs die-by-die focus and tilt measurement of the wafer using multiple focus sensors within each shot. Prior to exposure, the wafer stage and fine-drive Theta-Z-Tilt Unit drive the wafer surface to a position calculated to match the stepper best-image plane.

4 ADVANCING MICROELECTRONICS CONTENTS IMAPS 4-TIER PARTICIPATION Industry Systems & Applications Design Materials & Process DEPARTMENTS 4 From the Editor-in-Chief and the Technical Editor UPDATES FROM IMAPS 5 Device Packaging 11 Jobs MarketPlace 22 IMAPS 2015 Best Paper Award Winners 24 IMAPSource now available! 28 Industry News 32 Chapter News 34 IMAPS Reaches Out at the High School Level 39 Individual Member Benefits 40 IMAPS Premier Membership for Microelectronics Companies 41 Premier Corporate Members MEMBER TOOLS 43 Chapter Contacts 44 Advertiser Hotline 44 Advancing Microelectronics 2016 Editorial Schedule 44 Who to Call at IMAPS HQ INSIDE BACK COVER Calendar of Events IMAPS - International Microelectronics Assembly and Packaging Society PO Box TW Alexander Dr Building Suite 115 Research Triangle Park, NC USA Tel: E-Fax: IMAPS@imaps.org See us on IMAPS s Home Page: COMING NEXT ISSUE 3D including 3DIC and 3D Pkg. (POP) 2

5 UPCOMING EVENTS Advanced Technology Workshop on Advanced Packaging for Wireless Medical Devices January 26-27, 2016 San Diego, CA Advanced Technology Workshop & Tabletop Exhibition on Wire Bonding February 9-10, 2016 Toll House, Los Gatos, California - USA Device Packaging Conference March 14-17, 2016 Scottsdale/Fountain Hills, AZ 2016 RaMP Workshop and Tabletop Exhibition April 5-6, 2016 San Diego, CA Advanced Technology Workshop on Chip-Package Interactions with Fan-Out Wafer Level Packaging 2016 April 6-7, 2016 San Diego, CA IMAPS/ACerS 12th International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT 2016) April 19-21, 2016 Denver, Colorado 17th Symposium on Polymers for Microelectronics Innovations Driving a Smart and Interconnected World April 25-27, 2016 Winterthur, DE International Conference on High Temperature Electronics (HiTEC 2016) May 10-12, 2016 Albuquerque, NM Advanced Technology Workshop & Tabletop Exhibits on Additive Manufacturing & Printed Electronics June 20-21, 2016 Lowell, MA IMAPS 2016 October 10-13, 2016 Pasadena, CA PASADENA 49 th International Symposium on Microelectronics October 10-13, 2016 Pasadena Convention Center JANUARY/FEBRUARY 2016 Executive Council President Susan Trulli Raytheon President-Elect Ron Huemoeller Amkor Technology First Past President Dave Seeger IBM Vice President of Technology Matt Nowak Qualcomm Vice President of Membership and Marketing Iris Labadie Kyocera America Secretary Bill Ishii Torrey Hills Technology Treasurer David Virissimo Coining, Inc., an Ametek Company Directors Benson Chan, Endicott Interconnect Robert Dean, Auburn University Ray Fillion, Consultant Mark Hoffmaeyer, IBM Rich Rice, ASE US Student Programs Venky Sundaram, Georgia Tech Ex-Officio (Executive Director) Michael O Donoghue, IMAPS Publications Committee Editor-in-Chief, Advancing Microelectronics Tim Jensen, Senior Product Manager for Engineered Solder Materials, Indium Corporation Technical Editor, Advancing Microelectronics Maria Durham, Technical Support Engineer for Semiconductor and Advanced Assembly Materials, Indium Corporation Editor, Journal of Microelectronics and Electronic Packaging John Pan, Cal Poly State University Managing Editor, Advancing Microelectronics Ann Bell, or abell@imaps.org Staff Director of Programs Brian Schieman Advancing Microelectronics (formerly Inside ISHM) is published six times a year and is a benefit of IMAPS membership. The annual subscription price is $75; $15 for a single copy. Copyright 2016 by IMAPS International Microelectronics Assembly and Packaging Society. All rights reserved. Except as defined in 17 USC, Sec. 107, permission to republish any materials in this publication must be obtained from IMAPS, PO Box , 79 TW Alexander Dr., 4401 Building Suite 115, Research Triangle Park, NC Telephone Visit for links to all upcoming events 3

6 ADVANCING MICROELECTRONICS FROM THE EDITORS Wafer Level and Device Packaging Tim Jensen, Editor-in-Chief Maria Durham, Technical Editor In this issue of Advancing Microelectronics, we have a number of excellent articles that should be of great interest to people involved in the semiconductor industry. Advanced Packaging Technology is becoming more and more demanding in regards to integration capability, design flexibility, small and tiny packages, and cost, just to name a few. There are several emerging wafer level packaging solutions that are being explored. Wafer Level Packaging gives small and thin packaging and allows for high volume manufacturing. One technology that is gaining interest is Fan-Out Wafer Level Packaging (FO-WLP). This technology has been around for a number of years, but it is starting to gain broader adoption throughout the industry for applications where higher performance and bandwidth is required. FO-WLP, also known as embedded wafer level ball grid array (ewlb), allows for the highest density in 2D and is currently being advanced into 3D stacking. FO- WLP technology allows for more than a 20 percent reduction in package size/thickness with increases in overall performance. This is achieved while also being low cost and desirable for automotive, mobile, and IoT applications. Of course, FO-WLP isn t without its own challenges such as wafer warpage and die shift. When considering the wafer warpage in particular, there are a number of factors related to materials and processes that will have a dramatic impact on this issue. For example, the epoxy mold compound (EMC) can be designed to reduce warpage. Characteristics such as Tg, modulus, and CTE can be used to evaluate the EMC and its impact on warping. Additionally, the molding equipment has moved toward a compression process vs. the traditional transfer mold process. Continued research on materials and processes will help advance this technology at an even faster rate. New information on this technology development is constantly being released. In March, IMAPS will be having its 12 th annual International Conference and Exhibition on Device Packaging. This conference is simply the biggest and best opportunity to gain knowledge on 3D interconnects and packaging, flip chip, and wafer level packaging. The conference is really well organized into focus tracks allowing attendees to easily target the topics that are of interest to them. In the 3D IC track, the discussion of some of the latest advancements in advanced 3D technologies covering wire-bonded chip stack, interposers, package-on-package (PoP), through-silicon-via (TSV) based die-to-die (or chip), die-to-wafer, and wafer-towafer 3D approaches. The track on wafer level and flipchip will focus on packaging technologies such as fan-out, wafer level materials, and reliability considerations. The third track is on SiP and engineered micro systems where there are some great topics on system-in-packages, sensors, and other MEMS devices. Face-to-face interaction with technical experts just can t be replaced with internet searches and paper downloads. Enjoy this issue of Advancing Microelectronics and join us as we continue to increase our knowledge through technical papers and excellent conferences. Visit IMAPS.org to see all upcoming Advanced Technology Workshops and Conferences 4

7 JANUARY/FEBRUARY 2016 IMAPS 12th International Conference and Exhibition on Device Packaging March 14-17, 2016 The Largest 2016 Conference Dedicated to... Interposers, 3D IC & Packaging; Flip Chip, Wafer Level Packaging & Fan-Out; SiP & Engineered Micro Systems/Devices (including MEMS & Sensors) 2016 Conference Overview: The 12th Annual Device Packaging Conference (DPC 2016) will be held in Fountain Hills, Arizona, on March 14-17, It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS). The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in device packaging fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, and sales & marketing professionals. Featuring 3 Topical Workshop Tracks, with New Changes For 2016: Interposers, 3D IC & Packaging Flip Chip, Wafer Level Packaging & Fan-Out SiP & Engineered Micro Systems/Devices (including MEMS & Sensors) Device Packaging Exhibit and Technology Show: IMAPS will hold a concurrent exhibition for vendors and suppliers who support the many aspects of Device Packaging. This venue features an ideal atmosphere to showcase your products and services to key decision making professionals in the industry. Full 8 by 10 exhibit spaces will be available. To reserve booth space, please fill out the application form before December 1, 2015 at: or contact Brian Schieman by at bschieman@imaps.org or by phone at The exhibits have sold out every year since 2006 and we expect a sell-out again in so book before December! Device Packaging Professional Development Courses (PDCs): For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 14th, preceding the technical conference. PDC details and registration on-line soon. Please contact Brian Schieman by at bschieman@imaps.org or by phone at if you have questions about the technical program, exhibits, golf or PDCs. 5

8 FEATURE ARTICLE Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Amy Palesko Lujan, SavanSys Solutions LLC, Peonia Court, Austin, TX USA, Ph: , Abstract Many factors affect the selection of the assembly and interconnect processes used to package a die. For example, the size of the die and package, the type of substrate, and the number of IOs all must be considered. In this paper, two processes are compared: a flip chip process using mass reflow with capillary underfill versus a flip chip thermocompression bonding process using nonconductive paste. Activity-based cost modeling is used for the analysis. Both of the process flows are presented in detail, then multiple cost comparisons are presented. Examples of the variables that will change are package size, material cost, and equipment cost. In most cases, the bonding and material portions of the process flows are focused on rather than the entire assembly and substrate processes this allows for a better analysis of particular details. Conclusions are drawn about which design scenarios are suitable for each process flow. Key cost drivers that may affect future cost comparisons as the technologies advance are also indicated. Key words Cost analysis, flip chip package, mass reflow with capillary underfill, thermocompression bonding with nonconductive paste I. Introduction There are many packaging choices available in the industry today, from mature processes like wire bonding through more complicated processes such as wafer level packaging and its various incarnations. In addition to determining which packaging technology to use, designs often must also make selections within each type of packaging. Flip chip is a good example of this. Although flip chip technology has been around for a long time, there are variations within the available processes. A key item of interest with flip chip technology is the method of bonding the die to the substrate. The most established process flow is arguably flip chip assembly that relies on mass reflow and capillary underfill for die bonding [1]. Thermocompression bonding, which may use nonconductive paste or film, is also an option. Although thermocompression bonding is generally viewed as the more expensive option, only to be used when the design rules require it, it can nevertheless sometimes be more cost effective than mass reflow with capillary underfill. This paper explores the process flows and cost drivers behind both types of flip chip assembly processes. Activity-based cost modeling was used to construct basic process flows for this study. In activity-based cost modeling, the process flows are divided into a series of activities and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, amount of labor required, cost of material required (consumable and permanent), tooling cost, equipment cost (including factors such as depreciation), and yield loss. II. Process Flows In this section, the process flows are introduced. The general flip chip process flow is described on a summary level in Table I, then the main flip chip cost drivers are highlighted. Parts A and B of this section explain in more detail the steps (activities) that are different in the bonding portions of the process flows. Substrate Fabrication Die Preparation Includes inner layer and core processes, creation of through holes, build-up layer processing and lamination before concluding with surface finish Inspection, test, wafer bumping and wafer mounting followed by singulation Begins with bonding the die, includes BGA Assembly ball attach, singulation (if strips), then inspection and testing Table I Overview of a Flip Chip Process Flow Package size is a major cost driver for this process flow, as is the substrate structure [2]. The substrate structure required will depend on the size of the die, because this determines the amount of routing that has to be included in the build-up layers. The fact that wafer bumping is required for flip chip technology can also be seen as a cost driver, particularly if comparing it to a technology that doesn t require wafer bumping (e.g., wire bonding). The method for bonding the die is an important cost driver, and the rest of this paper focuses on a process flow and cost analysis of the die bonding method. A. Flip Chip with Mass Reflow and Capillary Underfill Table II details the bonding steps required for a mass reflow with capillary underfill flip chip process. Unlike the previous summary of the entire process flow, here the steps are broken down into the individual activities that make up the bonding process. These steps take place after 6

9 JANUARY/FEBRUARY 2016 the substrate has been diced and before moving on to ball attach. Setup for die bonding Dispense flux for die bond Place die Reflow solder Plasma clean Optical inspection Bake the substrate Setup for underfill Dispense underfill + underfill flow out Move underfill dispenser to next die Cure underfill Laser marking Table II Mass Reflow + CUF Bonding Activities The die bond process itself is relatively quick, and the material cost of the flux associated with that activity is low. The equipment required for mass reflow is not very expensive, so that is not considered a major cost driver. The underfill process contributes a high cost, primarily due to the cost of the material itself and the fact that a relatively high volume of underfill is necessary [3]. The underfill is dispensed along the sides of the die and capillary action pulls it under (the rate at which it flows depends on pitch) [4]. Due to this process, there are fillets left on the side(s) of the die, and these fillets represent a not insignificant portion of material cost when looking at the process as a whole. B. Flip Chip with Thermocompression Bonding and Nonconductive Paste Table III details the steps required for thermocompression bonding using nonconductive paste. Note that there are differences between the two flip chip process flows not captured by listing the bonding process steps alone. For example, copper pillars are required earlier in the thermocompression bonding flow, which is not the case for mass reflow. However, the focus of this comparison is the cost associated with the bonding portions only. Furthermore, and somewhat surprisingly, the cost of a solder bumped wafer is not very different from the cost of a wafer with copper pillars [5]. volume of a cheaper material, while the other requires less of a more expensive material. There is more to consider beyond material costs. The thermocompression bonding process is slower on a per die basis, and thermocompression bonding equipment is more than twice as expensive as the equipment needed for a mass reflow and underfill based process [6]. III. Cost Comparison Table IV shows the key assumptions that were made for the bonding parameters in both flows. These are considered to be the baseline numbers for all trade-offs unless otherwise stated. Die bond time Bonding equipment cost Material cost Underfill dispense/ flow-out time Mass Reflow 3000 die per hour TCB + NCP 327 die per hour $350,000 $1,000,000 Underfill cost: $1.7/ gram and $2.4/gram 1.86 min per die area NCP cost: $3.074/gram N/A Table IV Process Flow Assumptions A calculator provided by Nordson ASYMTEK was used to calculate the volume of underfill required in various areas beneath the die, in the fillet, etc. This was used to obtain the volume of underfill required for numerous die sizes at two die thicknesses. The volume of NCP required was assumed to equal the volume of underfill beneath the die plus a twenty percent increase to account for dispensing irregularities. Table V shows the die sizes and basic design characteristics that were included in the analysis. Die Size (mm) Package Size (mm) Substrate Structure IO Count 2x2 3x x3 5x x5 9x x7.5 15x x10 20x Setup for die bonding 12.5x x Dispense NCP Table V Die Sizes and Characteristics Perform thermocompression bond Two die thicknesses were included in the analysis, Cure die bond with different fillet width assumptions. Plasma clean 0.8mm thick die (fillet width 1.6mm) Optical inspection 0.15mm thin die (fillet width 1mm) Bake the substrate The baseline results are shown in Figures 1, 2, and 3. Figure 1 shows the total cost of the package. The scale Laser marking makes it difficult to see details, but the crossover point Table III TCB + NCP Bonding Activities for the total package cost occurs near the largest package Some of the differences between the flows present themselves immediately. From a process flow standpoint, there are fewer steps here than in the mass reflow and underfill process, which is an advantage. The most expensive portion of the mass reflow process the use of underfill is missing from this shorter flow. On the other hand, nonconductive paste carries a higher cost per gram than underfill. This creates an interesting trade-off when it is considered that one bonding option requires a greater size. Although the impact on total package cost should not be disregarded, the focus of this analysis is how the cost of the bonding portion of the flow changes. Figures 2 and 3 show the cost of the bonding steps and associated material costs. Both the thicker and thinner die show that the thermocompression bonding process becomes more cost effective when looking at a larger package. In the 0.8mm thick die scenario, the reason thermocompression bonding continued on page 8 7

10 ADVANCING MICROELECTRONICS continued from page 7 Figure 1 Total Package Cost for 0.8mm Thick Die Figure 2 Cost of Bond Steps Only for 0.8mm Thick Die Figure 4 Bonding Process Cost Contributors Figure 3 Cost of Bond Steps Only for 0.15mm Thin Die becomes cost effective sooner than in the thin die scenario is that a thicker die means more underfill is required, so there are higher material costs associated with that flow. Once the die becomes thinner in the second graph (Figure 3), the underfill material cost drops because less underfill is needed. This pushes the crossover point with thermocompression bonding toward larger die sizes. Another interesting way to look at this initial data is to examine how the different types of cost break out. The following two pie charts in Figure 4 show a breakdown by percentage of the different categories of cost. Both charts are for the 5x5mm die scenario. These charts highlight the key points made about each flow in the initial process introductions. Thermocompression bonding requires more expensive equipment, and this accounts for over 60% of the cost of the bonding process. Despite the fact that nonconductive paste is expensive, material costs are not a large contributor for the overall process. Mass reflow carries a much higher material cost, accounting for one fifth of the total bonding cost, due in large part to the necessity of using so much underfill. The conclusion of this section is fairly straightforward: thermocompression bonding as a process is generally more expensive, but there are crossover points to be found with certain die characteristics. In the next section, the analysis moves a step farther, determining the ways in which the thermocompression bonding process may become more cost competitive. IV. Cost Trade-offs and Sensitivity Analyses This section focuses on how the cost numbers and crossover points shift when details about the processes 8

11 JANUARY/FEBRUARY 2016 change. The focus here is on thermocompression bonding parameters. The mass reflow and capillary underfill process is already mature; there is not much expectation of impactful changes occurring with regard to material cost, equipment cost, or other process parameters. The first trade-off focuses on the cost of the thermocompression bonding equipment. The previous results for both mass reflow scenarios are charted in the graph in Figure 5, while the thermocompression scenarios were re-run with the equipment cost for the bonding step set at $750,000. This $250,000 change in equipment price has a noticeable impact. The crossover point at which thermocompression bonding becomes more cost effective occurs closer to the 15x15mm package size scenario, whereas it was closer to the 20x20mm package size scenario in the baseline results. Another way to look at this trade-off is by varying the throughput of the thermocompression bonding step. From a cost modeling standpoint, capital costs are not based only on the price of the equipment itself, but include factors such as how often that piece of equipment is utilized, how long the product spends on that equipment, etc. The chart in Figure 6 shows the impact of shaving a few seconds off of the bonding time, which is 11 seconds per die in the baseline scenario. Similar to the previous example, this pushes the crossover point closer to the 15x15mm package size scenario. Next, the impact of changing the cost of the nonconductive paste was evaluated. The thermocompression bonding scenarios were re-run with the nonconductive paste cost dropping by about 40 cents per gram. The impact on total bonding cost is not as noticeable, as shown in the graph in Figure 7. The crossover point between mass reflow and thermocompression does occur sooner than in the baseline comparison, but only slightly. The difference between the cost of the bonding steps for a 20x20mm package with nonconductive paste costing $3/gram and costing $2.6/gram is about 0.7 cents. While there are other variables that could be tested for sensitivity in the thermocompression process, material cost, equipment price, and equipment throughput were selected as the key cost drivers. The purpose of this analysis was not only to analyze and compare the steps and cost drivers associated with both assembly processes, but to highlight the ways in which the less mature of the two processes thermocompression bonding may be able to become more cost competitive. Bringing down capital costs (such as through equipment price reduction or equipment throughput capability improvement) or the NCP material cost are both key methods for making thermocompression bonding more cost competitive. V. Conclusion Two types of flip chip assembly bonding processes were presented in detail, and their cost drivers were analyzed. While mass reflow with capillary underfill and thermocompression bonding both have material costs to take into account, it is a less than straight-forward comparison because one requires a high volume of a less expensive material and the other requires less material that comes at a higher price point. Capital cost considerations such as equipment price and equipment throughput were also identified as cost drivers for the thermocompression process. Figure 5 Cost of Bond Steps at New TCB Equip. Price Figure 6 Cost of Bond Steps at Different TCB Speeds Figure 7 Cost of Bond Steps at New NCP Price Point continued on page 10 9

12 ADVANCING MICROELECTRONICS continued from page 9 Baseline results using process flow parameters based on industry averages revealed that thermocompression bonding can be cost effective for larger packages. More important, further analysis revealed that thermocompression bonding the less mature of the two assembly processes has the potential to become cost effective in more applications if capital or material costs are improved. Biography Amy Palesko Lujan received her degree in Chemistry from The College of William and Mary; she is currently VP of Business Development at SavanSys Solutions LLC. Prior to joining SavanSys, Amy held positions in business development at TOK America and engineering at Nokia Japan. In 2006, she spent one year in Japan on a Fulbright grant, analyzing the cost impact of shifting to lead-free manufacturing. References 1 A. C. Mackie, Thermocompression Bonding (TCB) for Dimensional (2.5D and 3D) Assembly, Chip Scale Review, September/October Y. Ranade, Evolution of Organic Flip Chip Packaging, blog entry on Solid State Technology. 3 M. Joshi, R. Pendse, V. Pandey, T. K. Lee, I. S. Yoon, J. S. Yun et al., Molded underfill (MUF) technology for flip chip packages in mobile applications, ECTC J. W. Wan, W.J. Zhang, D. J. Bergstrom, An Analytical Model for Predicting the Underfill Flow Characteristics in Flip-Chip Encapsulation, IEEE Transactions on Advanced Packaging, E. Jan Vardaman et al., 2015 Flip Chip and WLP: Emerging Trends and Market forecasts, March B. Chylak, High Productivity Thermocompression Flip Chip Bonding, SEMICON West

13 JANUARY/FEBRUARY 2016 IMAPS JOBS MarketPlace Your IMAPS membership provides you with the on-line JOBS MarketPlace. This is a proactive, valuable, complimentary member service for both job seekers and prospective employers. Take advantage of it to find open positions or fulfill staffing needs. IMAPS members can post unlimited job openings at no cost. Hiring managers can search for and view resumes of industry participants at no cost by using convenient sort criteria. Member job seekers can post resumes and/or search for current openings at no cost. Job seekers can make their search even easier by setting up a job alert so compatible openings (by industry, location, and job function criteria) will be ed as they are posted. Find out more information at 11

14 FEATURE ARTICLE Qualification of a Low Cure Polymer for Fan-in Applications B. Rogers, R. Valencia, K. Quilaton, S. Jayaraman, and M. Almonte, Deca Technologies, Inc., 7855 S. River Parkway, Suite 111, Tempe, AZ Abstract Polymers with low cure temperatures (<250 C) are required for Wafer Level Fan-out applications, where RDL buildup layers are fabricated over reconstructed panels containing both mold compound and silicon die. As fan-out technology has matured, low cure polymers with improved mechanical properties have been introduced to provide increased reliability and extend applicability of this growing packaging technology. For several of these new polymers, properties have been enhanced to the point that these polymers can also be considered for wafer-level chip-scale package (WLCSP) or fan-in applications, where polyimides and PBOs with higher cure temperatures are generally used. Using a low cure polymer for fan-in can facilitate WLCSP packaging of temperature sensitive devices. Enabling packaging suppliers to use the same material for both fan-in and fan-out provides manufacturing benefits, allowing for consolidation of process flows and simplifying material management. This paper describes the qualification of a low cure polymer for WLCSP, demonstrating the viability of these materials for both fan-in and fan-out packaging. Introduction Wafer-Level Chip-Scale Packaging (WLCSP) offers the smallest package form factor and has become a preferred option for the handheld consumer electronics space, where portability and increasing functionality are strong drivers. WLCSPs also continue to migrate into other applications requiring small size, high performance, and low cost. In WLCSP technology, chip IOs are generally fanned-in across the die surface using polymer and redistribution line (RDL) buildup layers to produce an area array, and large solder bumps are then formed at the terminals by ball drop, solder paste printing, or plating. These additive processes allow the chip to be attached directly to a printed circuit board (PCB) with good reliability [1]. An image of a free-standing WLCSP and one attached to a PCB are shown in Figure 1. The thermal mismatch between the silicon chip and the organic PCB has limited WLCSPs to relatively small die sizes usually less than 5 5mm 2. WLCSP suppliers and users are continually looking for ways to improve reliability and extend the size of chips that can utilize this unique packaging technology. In recent years, the introduction of new materials and design and structural improvements have extended the usable die sizes into the 5 5mm 2 to 6 6mm 2 range [2] [4]. Figure 1. Free-standing WLCSP, and WLCSP after attachment to printed circuit board. The mechanical properties of the polymers used in the buildup layers on the WLCSP play an important role in the reliability of the part. Photo-imageable polyimides and polybenzoxazoles (PBOs) are generally chosen for these applications because these materials exhibit high elongation, good tensile strength and moderate modulus, allowing them to absorb stresses in the WLCSP induced by the thermal mismatch with the PCB. However, to achieve the acceptable mechanical properties, these films generally must be cured at relatively high temperatures, in the range of 300 C to 400 C. The high cure temperatures sometimes limit the extension of WLCSP to temperature-sensitive devices for example, memory parts where data retention might be compromised. With the advent of Wafer Level Fan-Out (WLFO) technology, polymers with lower cure temperatures are becoming much more prevalent. In WLFO, chips are singulated and embedded in molded panels. The extra mold surface around the chip allows the part to accommodate a larger number of IOs than can be accommodated with WLCSP. Build-up layers with RDL and polymer are fanned in over the silicon and out over the mold surface, utilizing processes similar to those used for WLCSP. After the buildup layer processing and the solder ball attachment, the packages can be background, laser marked, and singulated, just like WLCSPs. Polymers with cure temperatures of less than 250 C are required for the buildup layers on WLFO parts, due to the low glass transition temperature of the mold compound in the reconstituted panels. Identifying low cure polymers with good mechanical properties is important to insuring WLFO package reliability. This need has driven material suppliers to develop a number of new low cure polyimides and PBOs which rival the standard high cure materials in terms of mechanical performance. The ability to use a single low cure polymer for fan-in and fan-out applications has several advantages for packaging suppliers. As stated previously, a low cure polymer can facilitate WLCSP packaging of temperature sensitive devices. Enabling packaging suppliers to use the same material for both fan-in and fan-out also provides manu- 12

15 JANUARY/FEBRUARY 2016 facturing benefits, allowing for consolidation of process flows and process development and simplifying material management. The purpose of this study was to qualify a low cure polymer for WLCSP. The polymer selected was a low cure PBO, with a cure temperature in the range of 200 C to 250 C. The mechanical properties of the low cure PBO, measured using stress-strain analyses on lifted-off polymer strips, are shown in Table 1. The elongation of 91% exceeds that of many standard high cure materials. The tensile strength and modulus of this material are also in a suitable range to provide good reliability performance. The board level reliability performance of this polymer has been tested against a standard high cure PBO already in widespread production for WLCSP. The strong performance of this low cure polymer demonstrates the viability of this material and other similar materials for WLCSP applications. Property Measured Value Elongation 91% Tensile Strength 152 MPa Modulus 2.2 GPa Table 1. Measured mechanical properties of low cure PBO polymer. Figure 2. 6mm 6mm daisy chain test vehicle. Figure 3. Illustration of WLCSP solder joint, illustrating key geometric factors for board level reliability: diameters of the under bump via, UBM pad, and PCB pad; and thicknesses of the polymer and RDL layers. lurgy (UBM) pad and the PCB pad, and the thicknesses of the polymer and RDL build-up layers on the WLCSP. Undersizing the polymer via under the bump can improve cycling performance, by providing more stress buffering under the bump edge. Sizing the thick PCB pad about 10% smaller than the UBM pad results in a more spherical bump geometry and tends to delay typical solder fatigue failure at the bump-ubm side of the joint, also improving cycling performance. Finally, thickening up the RDL and polymer 2 layers can produce significant gains in drop performance by delaying a typical drop failure mode, a break in the RDL. In order to realize the above improvements on the 6 6mm 2 test vehicle, the UBM pad size was set at 240um, while the via under the bump was fixed at 180um, 75% of the UBM pad size. The board pad size was targeted at 215um, ~ 90% of the UBM pad. Thick RDL and polymer 2 build-up layers were also employed on the WLCSP, to improve the drop performance of the parts. The 6 6mm 2 WLCSPs were constructed using both low cure PBO and a conventional standard cure PBO. The reliability provided by the two materials was then compared using two standard board level reliability tests, thermal cycling and drop-shock testing. Thermal cycling is used to predict the life of the part as it undergoes temperature variations, which produce stress on the solder joints due to the mismatch between the WLCSP and the PCBs. Drop testing is used to gauge the resistance of the structure to impact failure and is a key test for hand-held applications where the risk of physical impact is high. For the board level testing in this study, the WLCSPs were mounted on 8-layer, 1mm thick boards with nonsolder-mask defined PCB pads. Fifteen parts were mounted on each board. Standard JEDEC conditions were used for the temperature cycling (method G: -40 to 125 C, 1 cycle/hr, 20min ramp, 10min dwell) [6]. JEDEC conditions were also employed for drop testing (condition B: 1500Gs) [7]. All parts were carried to either 1000 cycles Test Vehicle and Test Conditions The test vehicle used in this study is shown in Figure 2. The WLCSP consisted of a 6 6mm 2 die, a large platform for WLCSP applications. The test vehicle contained 196 IOs in a array on a 0.4mm pitch. The inner portion of the array consisted of dumbbells in the RDL layer, while the outer three rows and columns were routed through aluminum pads on the test chip. The IOs were populated with SAC405 (Sn 95.5 Ag 4.0 Cu 0.5 ) solder balls. By attaching to test boards, the connections could be completed on the board side to form a single daisy chain, allowing for real time resistance monitoring during board level reliability testing. Solder joint geometry factors were optimized to improve the reliability of the 6 6mm 2 WLCSP [5]. A nonsolder-mask defined solder joint, typical for WLCSP assembly, is illustrated in Figure 3. Key parameters for joint reliability include the diameter of the polymer via under the bump, the relative sizes of the under bump metalcontinued on page 14 13

16 ADVANCING MICROELECTRONICS continued from page 13 Figure 4. Weibull plot comparing cycling performance for high cure and low cure PBOs for the 6x6 mm2 fan-in WLCSP. First failure for low cure PBO passed at 613 cycles, with a failure mode of solder fatigue. Figure 5. Weibull plot comparing drop test performance for high cure and low cure PBOs for the 6x6 mm2 fan-in WLCSP. First failure for low cure PBO passed at 118 drops, exhibiting a failure mode of RDL fracture. 14 or 1000 drops. Resistance of the daisy chains was monitored during the testing, and failure was defined as a 20% increase in resistance over initial values. Reliability Test Results Thermal cycling results for the standard and low cure PBO polymers are shown in Figure 4. The low cure PBO actually outperformed the standard PBO in cycling tests, exhibiting a first failure at 613 cycles and a characteristic life of 1021 cycles. The failure mode for the low cure parts was solder fatigue, as desired for cycling tests. The standard PBO correspondingly had a first failure at 518 cycles and a characteristic life of 890 cycles, also considered passing results. Drop tests results for the low cure and high cure PBO are shown in Figure 5. In this case, the standard PBO performed better, exhibiting 259 drops to first failure and a characteristic life of The low cure PBO first failure occurred at 118 drops, with a characteristic life of 942 drops. The failure mode was RDL fracture, which is typical mode for drop testing. Both polymers exhibited drop performance in excess of 100 drops to failure, easily meeting typical drop test requirements. The passing performance of low cure PBO on the 6 6mm 2 test vehicle demonstrates the viability of this material for WLCSP applications and suggests that other similar low cure materials may also perform well in this technology space. Conclusions Improvements in materials properties of low cure polymers have made them viable candidates for fan-in WLCSP applications, as demonstrated by the strong board level test performance of the low cure PBO used in this study. This can enable packaging suppliers to realize benefits offered by a lower thermal budget for WLCSP parts and to consolidate on a single polymer for fan-in and for fan-out applications. Acknowledgements The authors would like to acknowledge the assistance of HD Microsystems in performing the mechanical analyses of the low cure polymer used in this study. References [1] P. Garrou, Wafer level chip scale packaging (WL-CSP): An overview, IEEE Trans. of Adv. Packaging, 2000, Vol. 23(2), pp [2] R. Chilukuri, Technology solutions for a dynamic and diverse WLCSP market, IWLPC Proc., San Jose, CA (2010). [3] R. Anderson, R. Chilukuri, T. Y. Tee, C. P. Koo, H. S. NG, B. Rogers, and A. Syed, Advances in WLCSP technologies for growing market needs, IWLPC Proc., San Jose, CA (2009). [4] R. Anderson, T. Y. Tee, R. Moody, L. B. Tan, H. S. NG, J. H. Low, and B. Rogers, Integrated testing & modeling analysis of CSPnl for enhanced board level reliability, IWLPC Proc., San Jose, CA, , (2008). [5] B. Rogers, M. Melgo, M. Almonte, S. Jayaraman, C. Scanlan, and T. Olson, Enhancing WLCSP Reliability Through Build-up Structure Improvements and New Solder Alloys, IWLPC Proc., San Jose, CA, , (2014). [6] JEDEC Standard JESD22-A104C, Temperature Cycling, [7] JEDEC Standard JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products, Biography Boyd Rogers received his PhD in Electrical Engineering from Duke University in He has since held positions at the MCNC Center for Microelectronics, Dow Chemical Company, Unitive Electronics, and Amkor Technology. Boyd currently serves as Vice President of Research and Development for Deca Technologies, where he has been a member of the staff since July 2010.

17 JANUARY/FEBRUARY 2016 Advanced Technology Workshop Chip-Package Interactions with Fan-Out Wafer Level Packaging April DoubleTree, Mission Valley, San Diego, CA CPI 2016 Focus: The International Microelectronics Assembly and Packaging Society (IMAPS) will host an Advanced Technical Workshop in San Diego on CHIP-PACKAGE INTERACTIONS WITH FAN-OUT WAFER LEVEL PACKAGING on 6-7 April, Fan-out wafer level packaging is a rapidly growing segment of the semiconductor packaging industry. Miniaturized mobile and IOT applications are driving the need for thin, low cost packaging with high pincount to chip area ratio. As fan-out packaging is being extended to thinner and larger form factors and applied to 2.5D/3D system-in-package solutions, chip-packaging interactions (CPI) including warpage, mechanical and electrical stress effects, are potential barriers to wide scale adoption of this promising technology. This workshop will provide a venue for papers, poster sessions, and brainstorming discussions, bringing together product designers with the fan-out packaging supply chain to explore cost-effective solutions to the CPI challenges, including new materials, design techniques and EDA tools, and process flows and equipment. Sessions are being planned and abstracts are being requested in the following areas: Process Technologies Effects of process technologies SIP Advanced Processes for enabling fan-out Scaling fan-out - issues and readiness Fan-out as 3D Packaging Approaches to die-last fab, packaging, or substrate New Design/Materials Material/process interaction Novel materials for enabling fan-out Molding compounds Quality & Reliability Warpage effects Form Factor effects CMOS BEOL/FEOL effects Mechanical and Design reliability Fan-out in the Automotive world - reliability requirements Process control of fan-out - inprocess through to test - assuring reliability Reliability in a SIP world Design Tools EDA Tools and readiness for all different fan-out approaches Stress Aware Design Pushing RDL line width and space SUBMISSION: Those wishing to present a paper at the Workshop must submit a word abstract electronically no later than JANUARY 31, 2016, using the on-line submittal form at: All abstracts submitted must represent original, previously unpublished work. The abstracts should highlight the substrate advancements, materials processing/ reliability, design, packaging issues and application. The submission section will aid in grouping the work within these three areas. No formal technical paper is required. Please contact Brian Schieman by at bschieman@imaps.org if you have questions. 15

18 FEATURE ARTICLE Resolution and Resist Profile Considerations for Advanced Packaging Lithography Doug Shelton Canon USA Advanced Packaging technologies complement and enhance leading-edge semiconductor processes and designs to enable improvements in overall electronic system speed, performance, efficiency, bandwidth and form factor. Enabling technologies include monolithic 3D-IC designs, silicon and glass interposers and Fan-Out Wafer Level Packaging (FOWLP) that utilize high-density via layouts requiring reduced interconnect pad pitches as well as finer Redistribution Layer (RDL) line width and space (L/S). Via and RDL scaling for Advanced Packaging requires lithography systems that balance throughput, overlay and imaging resolution while maximizing process robustness and yield. An example of key lithography process requirements for Advanced Packaging applications [1] is provided in Table 1 including processing of severely distorted substrates and wafer stacks, high-accuracy overlay and precise imaging of patterns from 1 µm to 100 µm. This article will focus on imaging-related lithography process factors and stepper design features that improve pattern fidelity on a wafer and substrates. The article highlights the Canon FPA-5510iV stepper that is gaining acceptance as a high-resolution, low-cost lithography solution for Advanced Packaging processes. Designed to deliver a variety of optional functions that can be applied to most processes, the FPA-5510iV delivers precision imaging through thick resist and the ability to perform accurate backside alignment. A comparison of key specifications and features of the Canon Advanced Packaging steppers [1] are provided in Table 2 including information Table 2 on the FPA-5510iZs stepper that provides even superior resolution ( 280 nm w/ Annular Illumination) and overlay ( 200 nm backside overlay w/ TSA Option) to support the most aggressive processes. Canon Advanced Packaging Stepper Table 1 While applications employing Advanced Packaging technology are gaining acceptance, most current processes typically leverage existing back-end-of-the-line technology designed to only support 5 µm RDL L/S patterning. Advanced Packaging designs at this resolution do provide 16

19 JANUARY/FEBRUARY 2016 significant benefits but the overall system improvement is limited. To maximize the beneficial effect of RDL L/S scaling and minimize costs, leading Advanced Packaging applications are seeking to develop high-volume manufacturing capacity that can support 2 µm RDL L/S resolution and lower. Canon s experimental results have shown that the 0.18 NA of the FPA-5510iV can provide 12.2 µm Common DOF for line widths of 1.0 µm as shown in Figure 1 which contains a Line CD vs. Focus plot for horizontal and vertical patterns at 10 locations across a 52 x 34 mm exposure field. Common DOF is the shared focus range for which both horizontal and vertical patterns resolve (Target CD ± 10%) across the entire exposure field. Common DOF is impacted not only by the optical quality of the stepper lens and optical system, but also by the reticle and wafer flatness and stage stability. To minimize these effects, Canon steppers utilize a multi-channel Optical Tilt Focus (OPTF) System that performs die-bydie focus and tilt measurement of the wafer using multiple focus sensors within each shot. Prior to exposure, the wafer stage and fine-drive Theta-Z-Tilt Unit drive the wafer surface to a position calculated to match the stepper bestimage plane and these systems are illustrated in Figure 2. FOWLP processes are especially vulnerable to surface topography and require high focus accuracy and large DOF to enable high-yield processes. FOWLP is an advanced packaging technology that involves creating reconstituted wafers by embedding known good die into a mold compound or substrate [2]. The reconstituted wafer then receives a top-side redistribution layer which must be accurately patterned over the sometimes large topography difference between die and mold compound. In spite of this large topography, the stepper must be able to accurately image fine RDL patterns over the entire exposure field which is why a large DOF and die-by-die focus and tilt compensation are so important. To demonstrate the focus compensation ability of the FPA-5510iV stepper, Canon conducted a joint study [3] with Hitachi Chemical Co., Ltd., where a FOWLP wafer was measured and mapped by the stepper OPTF system as shown by the graphical representation in Figure 3a. The wafer surface map shows a sample FOWLP wafer with 10 mm die placed at a die pitch of 30 mm. Figure 3b shows the topography profile for the FOWLP wafer along the Segment A-A across the wafer. The A-A cross section shows a gap between a mold and the die of about 20 μm and this topography gap must be overcome by the stepper. Figure 3c shows simulation results for focus compensation residual error when applying a die-by-die focus and tilt compensation to the sample FOWLP wafer. This simulation assumed the case where only the field size is 30 mm and there is one die in each exposure field. After die-bydie focus and tilt compensation, the residual error in the shot is reduced to approximately 10 µm. Therefore, given a 12.2 µm DOF for 1 µm features, it can be expected that a FPA-5510iV stepper can provide sufficient focus latitude to support a 1 µm RDL process on the FOWLP wafer. The multi-channel optical Auto-Focus system and large DOF enable the stepper to place a wafer in a focus position where good pattern fidelity can be achieved in both the die and mold areas which can suppress yield issues related to substrate defocus. Canon 10iV steppers also support patterning of wafers covered in thick-photoresist for advanced etching Figure 1 Figure 2 and plating processes. For thick-resist applications, steppers must deliver a large enough DOF that high-aspect ratio target patterns are reproduced accurately to maintain downstream process specifications for via uniformity and coplanarity. Resist pattern critical dimensions must be uniform (CD Uniformity) throughout the entire exposure continued on page 18 17

20 ADVANCING MICROELECTRONICS Figure 3b Figure 3c Figure 3a 18 continued from page 17 area and additionally, thick-resist sidewall angles must be controlled to ensure uniform etching and plating rates. To control pattern CD Uniformity and sidewall angles, the FPA-5510iV stepper relies upon a flexible illumination system that allows the NA of the optical system to be varied according to process conditions [4]. The FPA-5510iV is equipped with a projection lens with a variable NA between that is software selectable and can be optimized for each process and recipe which gives users the ability to maximize process margin and control pattern CD size and sidewall angle for their different processes. An example showing the impact of large NA (0.57) vs. small NA (0.16) imaging is included in Figure 4 showing cross-sections of 40 µm features in 80 µm thick resist. It is clear from this example that for 40 µm imaging, a low-na stepper is preferred over a large-na stepper due to the reduced impact defocus has on the image patterned by the low-na stepper. This extreme example of the impact of NA change illustrates that varying the NA of the stepper does impact resist profiles and that NA optimization can play a role in improving and controlling resist profiles. It is also important to consider that although minimum resolution is an important process parameter, the stepper must reliably reproduce minimum resolution features throughout the entire exposure field of the stepper, while also maintaining imaging fidelity over time as exposure conditions change and energy through the projection lens accumulates. Thick-resist i-line applications typically require high exposure dose and may also demonstrate CD Uniformity deterioration due to intensity changes as the exposure lamp output declines over time. Canon data has shown that even if the exposure dose is maintained at a constant level, pattern profiles will change as the lamp used for exposure deteriorates as illustrated by the example of a Top-to-Bottom resist profile in Figure 5 [1, 5]. To counteract the detrimental imaging effects of variable lamp intensity, Canon has developed the optional Constant Intensity Function that actively controls lamp output to ensure stable intensity during the lifetime of the lamp. When implemented, the Constant Intensity Function can be enabled through the stepper recipe to provide improved pattern profile stability that contributes to downstream yield improvement. Experiments with common novolac-type resist have revealed that resist pattern profiles change relative to the intensity of exposure light source as illustrated in Figure 6 showing the top and bottom CDs for a 20 μm hole pattern in a 20 μm-thick novolac resist (DNQ). Although exposed at a constant exposure dose, with variable light intensity the graph shows that illumination intensity change has little effect on the top of the resist profile, while the bottom CD is affected by intensity change. These results show that even if the exposure dosage is maintained at the same level, the pattern profile and sidewall angle will change as the exposure lamp deteriorates. In order to resolve this issue and stabilize the pattern profile, Canon has developed the Constant Intensity Function that permits stable illumination intensity. This article discusses how Canon addresses the lithography challenges related to Advanced Packaging applications, focusing on key findings related to pattern resolution and imaging optimization and stability. Advanced Packaging imaging solutions including leveraging the large DOF and OPTF System of the FPA-5510iV stepper to accurately process wafers and substrates exhibiting severe

21 JANUARY/FEBRUARY 2016 Figure 4 Figure 5 Biography Doug Shelton is Marketing Manager for Canon USA and he currently works out of the Canon Industrial Products Division Headquarters in San Jose, California. His team provides Canon Industrial Products to customers throughout North and South America including Canon Optical and Nanoimprint Lithography systems, Canon Anelva deposition and etch equipment and Canon Optoelectronics and DC Micro-motors. Doug joined Canon in 1998 and has held positions in sales, marketing, engineering, and training development including a 2-year assignment in Utsunomiya, Japan. Doug received his B.S. and M.S. degrees in Engineering, and M.B.A. from San Jose State University and is an active and loyal member of IMAPS, IEEE and SPIE. Figure 6 warp and topography. The variable low-na of the FPA- 5510iV is also designed to provide maximum flexibility and control of thick-resist profiles and CD Uniformity. Canon Industrial Products remains committed to leading in the field of Advanced Packaging lithography and will continue to support the development of robust, highdensity interconnect solutions. References [1] D. Shelton, T. Kume, C. Wang, A. Hubbard, C. Murray, R. DeLancey, Advanced Process Technology for 3D and Interposer Applications, IMAPS 2014, 48th International Symposium on Microelectronics, October 2014 [2] B. Keser, Fan-Out Wafer Level Packaging, Professional Development Course manual, IEEE Electronic Components and Technology Conference, May 2015 [3] H. Suda, Photolithography Study for High-Density Integration Technologies, SPIE Advanced Lithography 2015, February 2015 [4] D. Shelton, C. Wang, Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks, IMAPS 2012, 46th International Symposium on Microelectronics, September 2012 [5] M. Mizutani, S. Hirai, I. Koizumi, K. Mori, S. Miura, Study of vertical lithography for high-density 3D structures, SPIE Advanced Lithography 2013, February

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24 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS IMAPS 2015 Best Paper Award Winners BEST OF TRACK PACKAGING THE INTERNET OF THINGS and OTHER ADVANCED APPLICATIONS: Engineered Nanocomposites for Additive Manufacturing of Microwave Electronics Juan Castro, University of South Florida (Thomas Weller, Jing Wang) ALSO AWARDED OUTSTANDING STUDENT PAPER BEST OF TRACK INTERPOSERS and 2.5/3D PACKAGING: High Voltage Stacked Diode Package Lauren Boteler, Army Research Laboratory (Miguel Hinojosa, Damian Urciuoli, Alexandra Rodriguez) BEST OF TRACK ADVANCED PACKAGING and ENABLING TECHNOLOGIES: Modeling, Design, Fabrication, and Characterization of Ultra-high Bandwidth 3D Glass Photonic Substrates Bruce Chou, Packaging Research Center at Georgia Tech (William Vis, Ryuta Furuya, Venky Sundaram, Rao Tummala) ALSO AWARDED BEST OVERALL STUDENT PAPER BEST OF TRACK ADVANCED MATERIALS and PROCESSES: Impact of Metallurgical and Mechanical Properties of Sintered Silver Nanoparticles on Die-attach Reliability of High-temperature Power Modules Hiroaki Tatsumi, Mitsubishi Electric Corporation (Sho Kumada, Atsushi Fukuda, Hiroshi Yamaguchi, Yoshihiro Kashiba) BEST OF TRACK DESIGN, MODELING and TEST: Line Coding Methods for High Speed Serial Links Abdelaziz Goulahsen, STMicroelectronics (Julien Saadé, Frédéric Pétrot, Université Grenoble-Alpes) ALSO AWARDED BEST OVERALL PAPER OF SYMPOSIUM BEST OF TRACK POSTER SESSION / INTERACTIVE TRACK: Pure Chemical Reduction of Tin Oxides to Metallic Tin by Atmospheric Plasma to Improve Interconnection Reflow of Pb-free Solders Kang-Wook Lee, IBM Research (Katsuyuki Sakuma, Thomas Lombardi, Jason Rowland, David Lewison, Eric Schulte) ADDITIONAL OUTSTANDING STUDENT PAPERS: Low Temperature, Fast Sintering of Micro-Scale Silver Paste for Die Attach for 300C Applications Fang Yu, Auburn University (R. Wayne Johnson, Tennessee Technological University; Michael Hamilton, Auburn University) Reliability of Manganese Dioxide and Conductive Polymer Tantalum Capacitors under Temperature Humidity Bias Testing Anto Peter CALCE, University of Maryland (Michael Azarian, Michael Pecht) BEST STUDENT POSTER: A Direct Digital Manufactured RFID System Applied to Teaching Antenna Theory to Pre-College Students Eduardo A. Rojas-Nastrucci, University of South Florida (Thomas Weller) BEST OF TRACK RELIABILITY: A New In-line Laser-based Acoustic Technique for Pillar Bump Metrology Michael Kotelyanskii, Rudolph Technologies (Todd Murray, Andrew Bakir, David Stobbe, University of Colorado, Boulder; Robin Mair, Manjusha Mehendale, Xueping Ru, Jonathan Cohen, Priya Mukundhan, Timothy Kryman, Rudolph Technologies; Michelle Schulberg, TEL NEXX) 22

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26 ADVANCING MICROELECTRONICS Something Big is HERE! The NEW IMAPSource enhanced online microelectronics research portal is now available at Featuring: A robust interface with improved functionality for easier searching Instant, easy online access to our archive of thousands of digital documents and research papers from IMAPS publications, conferences and workshops Wider visibility and searchability of your papers through leading search engines, such as Google Scholar Preferred access to the new online library for IMAPS members Exclusive content, focused on the advanced microelectronics packaging industry Start your search today at 24

27 JANUARY/FEBRUARY 2016 Special offer for IMAPSource pricing through 3/31/16 IMAPS members receive unlimited free downloads through 3/31/16 Non-members receive 25 free downloads through 3/31/16 IMAPS members are pre-registered with IMAPSource and receive a profile confirmation from Allen Press. This will help members gain unlimited download access to IMAPSource. Non-members and guests will need to click Register Now at IMAPSource.org. In 2016, free downloads will be subject to membership level below. Non-member downloads will be subject to a per-article charge IMAPSource Membership Plans: Number of downloads Individual/Senior/Lifetime 100 Corporate 300 Premier Corporate/Academic Institutions Unlimited* Associate Corporate 50 Affiliate (International Chapters/Unemployed Members) 50 Student 25 Retired/Senior Retired/Corporate International 25 *Unlimited package allows multiple IP range and unlimited access Contact IMAPS HQ today for more information about IMAPSource registration, member benefits, IP range setup for Premier Corporate and Academic Institution members and more! 25

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30 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS Industry News Heraeus Introduces New Polymer Thick Films, Copper Wire, Sinter Paste Heraeus Introduces New Polymer Thick Film Inks Heraeus new low-temperature inks provide the highest performance and versatility for the printed electronics industry. With these new inks, Heraeus offers unmatched quality, cutting-edge technology and a comprehensive suite of conductive, resistive and dielectric inks. The inks are specially formulated to meet the performance requirements of low-temperature electronic circuit designs. Electronic companies worldwide will find these inks useful in a broad range of demanding applications such as touch screens and displays, biosensors, printed batteries, electroluminescent lighting, membrane touch switches, flexible heaters, and RFID circuits. Heraeus inks are compatible with a variety of substrates including polyester, polyimide, phenolic, glass, and paper. Application methods range from screen printing to flexographic and rotogravure printing processes. These inks were developed and manufactured to meet the competitive cost challenges in the market while delivering superior performance. Every Heraeus low-temperature product is produced to combine excellence, cost efficiency and performance for the manufacturing of flexible circuits. For more information on Polymer Thick Film Inks, please contact your local Heraeus sales representative or to request our latest brochure, please contact Ryan Herrmann at Ryan.Herrmann@Heraeus.com. Copper Wire Offers High Reliability, Robust Bondability Heraeus new GXCu doped copper wire features ultrafine-pitch wire bonding capability with improved bonded ball shape. Along with excellent reliability, GXCu provides enhanced second bond functionality over bare Cu wire. This copper wire offers very good, consistent looping performance and longer floor life for 10 days compared to bare Cu wire. For more information on GXCu Copper Wire, please contact your local Heraeus sales representative. magic Sinter Paste for Power Applications on DBC magic AS- PO43-sinter paste is designed for die attachments on Direct Bonded Copper (DBC) substrates. It increases lifetime by 10 times compared to solder. This sinter paste offers improved thermal conductivity compared to solder, allowing more power at the same die size for system cost reduction. Other benefits include operation temperature up to 250 C and low process pressure compared to other sintering pastes. The simplified application process eliminates the need for flux cleaning, and the paste will not splatter. For more information on magic Sinter Paste, please contact your local Heraeus sales representative. Our People at Work Meet Frank Sandoval, Principal Technical Service Engineer. Frank Sandoval has been employed at Heraeus for four months, but has been involved in the electronics industry for almost 30 years. He brings to Heraeus 10 years of experience in Photovoltaics and 19 years of experience in PCB/Hybrid Microelectronics. His main areas of focus at Heraeus are resistors and sensors. Frank gets up early to check his s before preparing for the rest of the day. Working in a lab environment, his typical day consists of reviewing customer issues and planning respective actions: performing experiments, tests, data collection, and analysis; project review. Frank especially enjoys meeting and working with the talented employees at Heraeus. I believe an organization is only as good as the people it employs and my experience, to this point, has been extremely positive, Frank noted. After working in the PV industry for the last 10 years, Frank s biggest challenge at Heraeus has been to quickly learn a diverse product line and its respective functions in the industry. When asked to comment about an interesting aspect of his job, Frank replied, Printed resistors are 28

31 UPDATES FROM IMAPS JANUARY/FEBRUARY 2016 converted from a dried thick-film paste to a fused film at temperatures in the range of molten lava. In his free time Frank enjoys playing golf and the guitar (although not at the same time!), even though he says he plays neither very well. However, Frank is most proud of his family - his 30-year marriage to his high-school sweetheart, his five children and two grandchildren. i3 Electronics, Inc. Wins Medical Opportunity ENDICOTT, NY i3 Electronics, Inc. (i3) has announced that it has earned the opportunity from a multinational medical imaging conglomerate for the manufacture and advanced assembly of flexible substrates. This technology will be used to non-invasively measure realtime, three-dimensional organ abnormalities. i3 is a true enabler. From design, through fabrication, assembly and test, i3 provides a distinct advantage to our customers and their patients, with our life-saving technologies and world-class reliability, said Dale Kersten, Executive Vice President and Chief Business Officer at i3 Electronics. About i3 Electronics i3 Electronics, Inc., with headquarters in Endicott, NY, is a vertically integrated provider of high performance electronic solutions consisting of: design and fabrication of printed circuit boards and advanced semiconductor packaging; high speed laminate expertise; advanced assembly services; reliability and signal integrity reliability lab services; high speed back plane and press fit assembly; and flex, rigid-flex and 2.5 & 3D die assembly. i3 product lines meet the needs of markets including aerospace and defense, medical, high performance computing, industrial, telecom, semiconductor and test and alternative energy, where highly reliable products built in robust manufacturing operations are critical for success. For more information about i3 and its products, please visit, Kester Launches NP545 Solder Paste For additional information on this product, including technical and safety data sheets, please visit kester.com/products/product/np545-solder-paste Kester is a global supplier of assembly materials for the Electronic Assembly and Semiconductor Packaging industries. Kester is focused on delivering innovative, robust and high-quality solutions to help our customers address their technological challenges. Kester s current product portfolio includes soldering attachment materials such as solder paste, soldering chemicals, TSF (tacky solder flux) materials, and metal products such as bar, solid and flux-cored wire. Kester is an Illinois Tool Works (ITW) company. ITW is a Fortune 200 company that produces engineered fasteners and components, equipment and consumable systems, and specialty products. It employs approximately 49,000 people, and is based in Glenview, Illinois, with operations in 57 countries. NAMICS Corporation Develops Improved Dam-and-Fill Encapsulants San Jose, CA NAMICS Corporation has developed an epoxy dam material (CHIPCOAT G8345D) and an accompanying epoxy fill material (CHIPCOAT G8345-6) for the semiconductor market. Dam-and-Fill materials encapsulate your wire bonded device as an electrically insulating material. Dispensing a high-viscosity dam followed by a low-viscosity fill, will create a completed encapsulated package for your CSP and BGA. CHIPCOAT G8345D and G are fast curing, low CTE (low stress), offer high package reliability and reduced warpage. CHIPCOAT G8345D and G are in full production and are available for sampling. Standard packaging is frozen syringes with 50 grams in a 30cc syringe; larger cartridges are available. To find out more about these NAMICS Dam-and-Fill materials, please visit or contact your local NAMICS sales representative. Kester is proud to announce the launch of NP545, a zero-halogen, lead-free, no-clean solder paste designed for consistency and repeatability. NP545 is extremely stable and has an unrefrigerated shelf life of six months with no print or solderability degradation. Shelf life is one year from the date of manufacture when refrigerated. The paste is also fully capable of printing and reflowing components, even in air reflow, with minimal graping behavior. NP545 is classified as ROL0 per IPC J-STD-004B. G8354D (Dam) G8345D and G (Dam and Fill) NAMICS CORPORATION is a leading source for underfills, encapsulants, adhesives, and insulating and conductive materials used by producers of semiconductor devices, passive components and solar cells. Headquartered in Niigata, Japan, with subsidiaries in the USA, Europe, Singapore, Korea, Taiwan and China, NAMICS serves its worldwide customers with enabling products for leading edge applications. Contact Kevin McLaughlin, Product Manager, (408) , info@namics-usa.com. continued on page 30 29

32 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS continued from page 29 Leading OSAT and FPD Manufacturers Order JetStep Lithography Systems from Rudolph Technologies Lithography stepper gains further traction in advanced packaging and flat panel markets Flanders, New Jersey (December 2, 2015) Rudolph Technologies, Inc. (NYSE: RTEC) announced today that a major outsourced assembly and test facility (OSAT) has placed a repeat order for the JetStep W Series Lithography system, which it will use for both fan-out and fan-in packaging approaches. Additionally, Rudolph received an order from a leading flat panel display (FPD) manufacturer in China for its JetStep G Series Lithography system, which will be used for the development of next-generation processes for high-resolution mobile displays. The JetStep W System will ship in the fourth quarter of 2015 and the JetStep G System will ship in the second quarter of While we are well-established in advanced packaging with our NSX Series of inspection tools, lithography is a fast growing segment for Rudolph, said Rich Rogoff, vice president and general manager of Rudolph s Lithography Systems Group. Our success so far has been a result of our ability to help our customers meet the challenges of the newly-developing processes emerging in the rapidly expanding back-end. The JetStep W Series is a flexible reduction stepand-repeat tool that is specifically designed to meet the technical requirements of advanced packaging applications, which are often quite different from front-end lithography, Rogoff continued. It provides our customers with the flexibility to handle all of the current advanced processes, as well as new ones as they arise. The JetStep System can accommodate complex applications, such as thick resist layers, varying substrate thickness, wafer scaling variation and warped wafers associated with fan-out wafer level packaging (FO-WLP), through silicon vias (TSVs), and copper pillar bumps. In addition, the systems can process either traditional round wafer substrates or larger rectangular panel substrates, which can provide significant increases in productivity. It really can be customized for each of our customers unique requirements. We understand that the JetStep is a paradigm shift for the industry, and we are pleased to see its growing adoption by leading OSATs worldwide. Rudolph has an established lithography footprint in the FPD market, said Elvino da Silveira, vice president of marketing for Rudolph. This latest FPD order reinforces the value of the JetStep system s foundational stepper technology that continues to serve the FPD market, while we expand into the burgeoning advanced packaging arena where Rudolph can offer more complete manufacturing solutions by leveraging our inspection, metrology, and software solutions. The JetStep W Series features a large field of view (52mm x 66mm) to improve exposure efficiency and throughput. The system is unique in its ability to handle a wide range of substrates and accommodate substrate warp. These and other purpose-designed features, such as on-the-fly auto focus and a large automatic magnification compensation range, provide ways to increase throughput and maximize yield in advanced packaging applications that are unavailable from lithography tools designed for front-end processes or conventional packaging applications. The JetStep G Series addresses the demanding lithography requirements of the display industry. The system balances performance with flexibility to achieve optimal cost-of-ownership. It uses high-fidelity optics, with resolution capability down to 1.5 microns, and the largest printable stepper field available, enabling more displays per shot. This feature, combined with on-the-fly auto-focus and magnification compensation, maximizes throughput and yield. The innovative grid stage allows the system to be easily scaled to meet the customer s desired substrate size. For more information about Rudolph s JetStep Lithography systems, please visit 30

33 UPDATES FROM IMAPS JANUARY/FEBRUARY 2016 About Rudolph Technologies Rudolph Technologies, Inc. is a leader in the design, development, manufacture and support of defect inspection, lithography, process control metrology, and data analysis systems and software used by semiconductor and advanced packaging device manufacturers worldwide. Rudolph delivers comprehensive solutions throughout the fab with its families of proprietary products that provide critical yield-enhancing information, enabling microelectronic device manufacturers to drive down costs and time to market of their devices. The Company s expanding portfolio of equipment and software provides comprehensive solutions for front-end wafer processing, final manufacturing and advanced packaging of ICs. Headquartered in Flanders, New Jersey, Rudolph supports its customers with a worldwide sales and service organization. Additional information can be found on the Company s website at Safe Harbor Statement This press release contains forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995 (the Act ) which include the benefits to customers of Rudolph s products, Rudolph s business momentum and future growth, Rudolph s existing market position and its ability to maintain and advance such position relative to its competitors and Rudolph s ability to meet the expectations and needs of our customers as well as other matters that are not purely historical data. Rudolph wishes to take advantage of the safe harbor provided for by the Act and cautions that actual results may differ materially from those projected as a result of various factors, including risks and uncertainties, many of which are beyond Rudolph s control. Such factors include, but are not limited to, delays in shipping products for technical performance, component supply or other reasons, the company s ability to leverage its resources to improve its positions in its core markets and fluctuations in customer capital spending. Additional information and considerations regarding the risks faced by Rudolph are available in Rudolph s Form 10-K report for the year ended December 31, 2014 and other filings with the Securities and Exchange Commission. As the forward-looking statements are based on Rudolph s current expectations, the company cannot guarantee any related future results, levels of activity, performance or achievements. Rudolph does not assume any obligation to update the forwardlooking information contained in this press release. Rudolph Contacts: Investors: Steven R. Roth steven.roth@rudolphtech.com Pasadena Convention Center October Pasadena, California Guerrant Associates Laura Guerrant-Oiye Principal lguerrant@guerrantir.com Trade Press: Amy Shay amy.shay@rudolphtech.com 31

34 ADVANCING MICROELECTRONICS CHAPTER NEWS Your IMAPS Member Benefits at Your Chapter Level Your participation in these IMAPS chapter events greatly increases the value of your member benefits by providing industry insight, technical information, and networking opportunities. See more event information at Chesapeake Fall Technical Symposium 2015 The IMAPS Chesapeake Chapter held its annual Fall Technical Symposium on November 18, 2015, at the Applied Physics Laboratory (APL) of Johns Hopkins University. The symposium focused on the reliability issues and emerging trends in multilayer packages and simulation techniques. This symposium was also jointly organized by the IMAPS University of Maryland (UMD) student chapter. The evening began with three technical presentations the first of which was from Dr. Antonio Orozco from Neocera. Dr. Orozco presented on recent work in electrical fault isolation methods using Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB). The second talk was from Dr. Gil Sharon of DfR Solutions. Dr. Sharon presented on new high fidelity models used in software tools for design and failure analysis of electronic components. UMD student chapter and Chesapeake chapter members at the symposium. Antonio Orozco presenting on novel electrical fault isolation methods. The final speaker was Dr. Lauren Boteler of the Army Research Lab. Dr. Boteler presented on recent advancements on a new high voltage stacked silicon carbide diode capable of withstanding 30kV. The proceedings for the day concluded with a dinner, giving the members of the chapter, the new student officers, and the speakers an opportunity to interact with each other. During the dinner, many students from the IMAPS UMD chapter presented posters on their research and recent results. Speakers and Abstracts: Lauren Boteler Dr. Lauren Boteler has been working as a Packaging and Thermal Management Engineer as part of the Thermal Sciences and Engineering Team at the Army Research Laboratory since She designs thermal and packaging solutions for a wide range of applications including 3D chip stacking, power electronics, RF HEMT devices, top side cooling, phase change materials, MEMS, and thermoelectric modules. She obtained her PhD in 2011 from the University of Maryland where her research focused on microfabrication and analysis of advanced cooling structures to reduce the thermal stack. Abstract of Talk The Army is moving to a more electric force with a number of high voltage applications. To support this transition, there have been efforts to develop high voltage (15-30 kv) single die 4H-silicon carbide (SiC) bipolar switches and diodes. However, packaging these high voltage devices has proven to be challenging since standard packaging methods cannot withstand the high voltages in a compact form. Therefore, this work aims to develop a compact prototype package with improved size, weight, and power density by stacking diodes. The stacked diode approach allows elimination of almost half of the wirebonds, reduces the board size by 45% and reduces the package inductance. A module has been designed, fabricated and tested which is the first 30 kv module reported in literature to stack two high-voltage diodes in a series configuration. The package has a number of features specific to high voltage packaging including two fins that extend the perimeter of the package to mitigate shorting and all the leads were designed with rounded corners to minimize voltage crowding. Hi-pot tests were performed on the unpopulated package and showed the package can withstand 30 kv without breaking down. The completed package with the stacked diodes showed avalanche breakdown occurring at 29 kv. The complete package was then compared to an equivalent discrete diode module and showed a 10X reduction in size. During a clamped-inductive load test the stacked diodes showed lower parasitic capacitance, faster reverse recovery time, and lower turn on energy as compared to the discrete diode packages 32

35 CHAPTER NEWS JANUARY/FEBRUARY 2016 Gil Sharon Dr. Gil Sharon s research focus was mechanical reliability of electronic systems and components. His doctoral research included solder reliability, MEMS structures characterization, embedded components failure analysis and particle beam accelerator mechanical fatigue. Gil worked at Amkor Technology in the Advanced Product Development Group as Senior Engineer. His activity there explored chip-package interactions. Research interests of Dr. Sharon include multidisciplinary reliability of complex electro mechanical systems, characterization and modeling of material behavior, mechanical performance of flip chip packages and the physics of failure of electromechanical and MEMS systems. Abstract of Talk Package technology is constantly improving in order to keep up with the advances in silicon technology. Multilayered packages exhibit several failure modes that can be predicted using modern software tools. This talk provides a methodology for creating a high-fidelity model of the interposer with all the conductor geometries. The two failure modes that are explored with this model are package warpage prediction due to actual copper imbalance and filled microvia delamination. Each layer can be meshed based on the actual geometry in the layout design. Package warpage is caused by copper imbalance between the two sides of the interposer. The CTE mismatch between the two sides can bend the package to such a degree that it becomes impossible to assemble the solder interconnects. The filled microvias have copper structures that can delaminate from the copper traces in the conductor layers. The high-fidelity model provides the predictive tool to allow designers to adjust the layout before any manufacturing has taken place. Antonio Orozco Antonio Orozco is R&D Manager and Scientist at Neocera working on R&D of magnetic microscopy with SQUID and Magnetoresistive sensors. His efforts concentrate on expanding the capabilities of magnetic field imaging for Fault Isolation applications and Neocera s Magma magnetic microscope developments. He received his M.S. in Theoretical Physics from the Universidad Autonoma of Madrid, Spain, in 1992 and his Ph.D. in Condensed Matter physics from the University of Cadiz, Spain, in He has been working on new materials and novel magnetic oxides, superconductors and heterostructures for device applications, spin electronics and magnetic field detection. His experience includes over 20 years in computational physics and electromagnetic modeling, 14 years in failure analysis of integrated circuits, 15 years expertise in magnetic field detection and imaging. He pioneered several Neocera technologic innovations for detecting shorts, leakages, high resistance and dead open failures by magnetic imaging. He has been PI or had leading roles in numerous government and privately-funded research projects. He is the author of numerous scholarly and technical papers, contributed talks and four patents. Abstract of Talk In this talk we will show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work shows that MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB). San Diego Twenty-eight members of the San Diego Chapter attended a Winter Social event on December 1, Rick Sigliano and Ray Petit received plaques for their significant service to IMAPS both locally and nationally. Rick Sigliano receiving Special Plaque from SD Chapters for his years of dedicated service from chapter member Iris Labadie of Kyocera, Rick Sigliano, Ray Petit and Iris Labadie. 33

36 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS IMAPS Reaches Out at the High School Level Each year at the IMAPS Annual Microelectronics Symposium, a local area high school is chosen to be invited to a day at the Symposium and to receive a donation from our Society. The students meet professionals in microelectronics, assembly and electronic packaging, and experience first-hand what a career in this area entails. At IMAPS 2015, Lake Mary High School of Lake Mary, FL, was asked to visit the Symposium in Orlando, view the exhibits, have lunch and receive $2,000 from IMAPS. The photographs show students visiting an exhibit booth with Dr. Benson Chan, IMAPS Director, and all of the students with a mock-up of the check. 34

37 JANUARY/FEBRUARY

38 ADVANCING MICROELECTRONICS 17th Symposium on Polymers for Microelectronics Innovations Driving a Smart and Interconnected World Winterthur 5105 Kennett Pike (Route 52) Winterthur, DE April 25-27, 2016 The International Microelectronics Assembly and Packaging Society (IMAPS) is organizing the 17th Symposium on Polymers for Microelectronics. The theme for the 17th Symposium on Polymers for microelectronics is Innovations Driving a Smart and Interconnected World and will continue the event s focus on polymeric materials for microelectronic applications including traditional and new application areas. Traditional areas covered include stress buffer materials that have evolved from PSB to RDL to fan-out packaging applications for multilayer interconnect for 2D/3D packaging. Other materials to be discussed include substrates, including flex films and encapsulate materials as well as other polymeric materials used in electronics packaging. Applications spaces include wafer/ic packaging (including WSS adhesives and patterning), additive manufacturing, medical/ IoT devices/packages as well as fundamental material and characterization and properties of new/critical materials and new processes that enhance performance and lower cost will also be covered. The 2016 Symposium will also feature several keynote presentations, a panel discussion, and numerous networking opportunities. Keynote Speakers Flexible Hybrid Electronics Manufacturing Technologies as the Foundation for a Connected World Malcolm J. Thompson, Ph.D., Executive Director, Flexible Hybrid Electronics Manufacturing Innovation Institute / Chief Executive Officer, Nano-Bio Manufacturing Consortium / Chief Technology Advisor, FlexTech Alliance Changing Requirements for Thin Film Polymers in the Next Decade of Advanced Packaging Michael Töpper, Business Unit Developer, Fraunhofer Institute for Reliability and Microintegration IZM Sesssions are being planned for the following: Front-End of Line Applications Polyimide & Alternative Polymer Passivation (PSB and RDL) Semiconductor Applications, CMP Pads Low K Dielectric Materials Anti-Reflective/Multi-Layer Coatings Photosensitive Materials Sacrificial Materials /Temporary Bonding Packaging Applications Wafer Bumping Encapsulation (Underfill and Epoxy Molding Compounds) Die Attach, Adhesive & Thermal Interface Materials Organic Substrate Materials & Advanced Laminates Fan-in (Wafer Scale) and Fan-out Packaging (Embedding and RDL) Multi-Chip Packaging Applications SiP & SoP 3D Integration / TSV Structure-Property Relationships & Characterization Synthesis, Applications, Modification & Tailoring Polymeric Characterization & Testing Molecular Modeling Emerging & Novel Materials/ Manufacturing/Applications Medical Applications / Biosensors / Wearable Technologies Sensors / MEMS / Microfluidics Conductive & Ferroelectric Polymers Optoelectronic Packaging & Waveguides New Processing, Equipment & Metrology Technologies Display Technologies Flexible, Transparent, Printable, or Organic Electronics Photovoltaics Additive Manufacturing Materials and Processes Please contact Brian Schieman by at bschieman@imaps.org or by phone at

39 JANUARY/FEBRUARY 2016 IMAPS/ACerS 12th International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT 2016) April 19-21, 2016 Sheraton Denver Downtown Hotel Denver, Colorado - USA Goal The Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT) conference brings together a diverse set of disciplines to share experiences and promote opportunities to accelerate research, development and the application of ceramic interconnect and ceramic microsystems technologies. This international conference features ceramic technology for both microsystems and interconnect applications in a dual-track technical program. The Ceramic Interconnect track focuses on cost effective and reliable high performance ceramic interconnect products for hostile thermal and chemical environments in the automotive, aerospace, lighting, solar, defense/security, and communication industries. The Ceramic Microsystems track focuses on emerging applications and new products that exploit the ability of 3-D ceramic structures to integrate interconnect/packaging with microfluidic, optical, micro-reactor and sensing functions. Tape casting, thick film hybrid, direct write and rapid prototyping technologies are common to both tracks, with emphasis on materials, processes, prototype development, advanced design and application opportunities. Ceramic Interconnect Track Conventional thick and thin film ceramic technologies are being revolutionized and extended through the development of low temperature co-fired ceramics, photo patterning, and embedded passive component materials and processes. These have contributed to increased circuit density, enhanced functionality, and improved performance that are being adopted for leading edge applications in wireless and optical communications, automotive, MEMS, sensors, and energy. Data communications and the Internet are driving the demand for bandwidth, sparking demand for optical communication equipment and new interconnect and packaging applications that perform at 40 Gb/sec and beyond. In under-the-hood electronics (for automotive, engine/transmission control), communications and safety applications continue to drive the growth of ceramic interconnect technology, while collision avoidance systems are creating interest in low loss ceramic materials for frequencies approaching 100 GHz. Ceramic Microsystems Track Enabled by the availability of commercial ceramic, metal and embedded passives materials systems, and the rapid prototyping capabilities of the well established multilayer ceramic interconnect technology, three dimensional (3-D) functional ceramic structures are spawning new microsystems applications in MEMS, sensors, microfluidics, bio-devices, microreactors, and metamaterials. These new devices and applications exploit the ability to integrate complex 3D features and active components (e.g., valves, pumps, switches, light pipes, and reaction chambers). In addition, the Ceramic Microsystems track of the CICMT conference targets new developments in microsystems that include fabricating 3-D micro device structures enhanced with sol-gel, advanced printing and patterning technologies, high temperature materials technologies, and emerging applications like energy harvesting. Many of these innovative applications are taking advantage of the unique ability to integrate the thermal, chemical, mechanical and electrical properties of these multicomponent ceramic-metal systems. Special Features Invited keynote and international presentations on the current status of ceramic technology and future system directions. A focused exhibition for suppliers who support the use of the technologies. A technical poster session to promote student participation. Social events to promote new contacts. Early Registration/Hotel Deadline: March 23,

40 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS International Conference on High Temperature Electronics (HiTEC 2016) Conference Events and Technical Program May 10-12, 2016 May 10-12, 2016 Tabletop Exhibition May 10-11, 2016 Albuquerque Marriott Pyramid North Albuquerque, New Mexico - USA Please join us in Albuquerque, New Mexico for HiTEC Companies wishing to sponsor this conference or exhibit, or individuals interested in submitting an abstract or getting involved as a session chair, please contact Brian Schieman at bschieman@imaps.org for more information. HiTEC 2016 continues the tradition of providing the leading biennial conference dedicated to the advancement and dissemination of knowledge of the high temperature electronics industry. Under the organizational sponsorship of the International Microelectronics Assembly and Packaging Society, HiTEC 2016 will be the forum for presenting leading high temperature electronics research results and application requirements. It will also be an opportunity to network with colleagues from around the world working to advance high temperature electronics. Papers will be presented on, but not limited to, the following subjects: Applications: - Geothermal - Oil well logging - Automotive - Military/aerospace - Space Device Technologies: - Si, SOI - SiC - Diamond - GaN - GaAs - Contacts - Dielectrics MEMS and Sensors: - Vibration - Pressure - Seismic Packaging: - Materials - Processing - Solders/Brazes - PC Boards - Wire Bonding - Flip Chip - Insulation - Thermal management Circuits: - Analog - Digital - Power - Wireless - Optical Energy Sources: - Batteries - Nuclear - Fuel Cells Passives: - Resistors - Inductors - Capacitors - Oscillators - Connectors Reliability: - Failure mechanisms - Experimental and modeling results Early Registration/Exhibit & Hotel Deadline: April 13,

41 UPDATES FROM IMAPS JANUARY/FEBRUARY 2016 Individual Member Benefits Discounts on events, webcasts, publications, and iknow Micro downloads Take discounts on the Annual Symposium and many technical workshops. Take discounts on convenient, informative IMAPS webinars; imap.org/webcasts. Complimentary on-line library downloads, Advancing Microelectronics Magazine Enjoy a one-year subscription to Advancing Microelectronics. IMAPS Chapter Membership Learn from technical and management presentations by local and national experts. Create and build relationships with industry peers through regional programs. Access the Journal of Microelectronics and Electronic Packaging View the Journal of Microelectronics and Electronic Packaging on-line. Access to JOBS Marketplace Post resumes and search for current job openings. Keep records easily - results and actions are conveniently recorded. Enjoy helpful features of many expensive job search engines. Access to Members-Only sections on imaps.org Find individuals and companies that provide products and services. Enter your own professional listing. Visit imaps.org or call

42 ADVANCING MICROELECTRONICS UPDATES FROM IMAPS IMAPS Premier Membership for Microelectronics Companies Many companies active in IMAPS programs and events now enjoy considerable savings on promotional offerings and technical information offered under the new IMAPS Premier Membership. Companies can take advantage of up to $8,300 in member discounts. Please review the table below for a benefits comparison of the two corporate membership types. Corporate Membership Type: Premier Corporate Full Corporate Exhibit Discount Member Discount $450+ Member Discount $450+ IMAPS Individual Memberships 5 $375 2 $150 with Print Magazine IMAPS Individual Membership Benefits without Print Magazine Use of the IMAPS membership mailing list One quarter-page magazine advertisement Additional advertisement in magazines Unlimited $375 Assuming at least 5 Not included $0 3 times per $1,500 Once per membership year $500 membership year Included $590 Not Included $0 15% Discount $500 15% Discount $500 Advertisement on IMAPS website 12 Months Complimentary $1,395 Member Discount $700 Advertisement in the Weekly Bulletin 3 Continuous Months $1,140 Member Discount $300 Press Releases in the Corporate Bulletin Up to 1 PR in each Corp Bulletin (twice monthly) $250 Up to 1 PR in each Corp Bulletin (twice monthly) $250 Downloads from iknow Micro, on-line technical library IP recognition allows unlimited downloads for all computers at one network or office $2,500 2 members may download at no cost. $50 Global Business Council Membership Included $600 Included $600 Webinar Sponsorship 30% discount $600 10% discount $200 JOBS Marketplace Complimentary Job postings $200 Complimentary Job postings $200 On-line Industry Guide Includes company listing, link to website, product & service categories. $250 Includes company listing, link to website, product & service categories. $250 Access to Information Includes iknow Micro, Advancing Microelectronics, on-line Journal, Members Only section $75 Includes iknow Micro, Advancing Microelectronics, on-line Journal, Members Only section $75 Total value of full use $10,800 $4,225 Annual Dues: $2,500 $600 Savings Savings $8,300 Savings $3,625 40

43 UPDATES FROM IMAPS JANUARY/FEBRUARY 2016 Premier Corporate Members IMAPS has introduced a new level of support for corporate members. These companies have decided to participate in our Society at the Premier Corporate Member level. We are extremely grateful for their dedication to the furtherance of our educational opportunities and technological goals. 41

44 ADVANCING MICROELECTRONICS Advanced Technology Workshop & Tabletop Exhibits on Additive Manufacturing & Printed Electronics June 20-21, 2016 UMass Lowell Inn and Conference Center Lowell, MA Abstract Deadline: March 31, 2016 General Chair: Craig Armiento Co-Director Raytheon-U Mass Lowell Research Institute (RURI), Raytheon IDS, The International Microelectronics Assembly and Packaging Society (IMAPS) will host an Advanced Technical Workshop on ADDITIVE MANUFACTURING and PRINTED ELECTRONICS on June 20-21, Printing technology is expected to enable the evolution of electronics from rigid boards to products that are flexible, conformal or wearable. The Printed Electronics Conference will bring together experts to report on the progress and the challenges of this emerging field. This technology is expected to impact the options for integration of active and passive components and will exploit additive approaches to advance microelectronic packaging. Conference sessions will cover the development of printable electronic materials (inks), the options for manufacturing/printing and the applications of printed and flexible electronics. Those wishing to present at the workshop must submit a 500+ word abstract electronically no later than MARCH 31, 2016, using the on-line submittal form at: Please contact Brian Schieman by at bschieman@imaps.org or by phone at if you have questions. Full papers are not required. A post-conference download containing the presentation material as supplied by the presenter onsite will be distributed to all attendees. Speakers are required to pay a reduced registration fee. The Microelectronics Foundation sponsors Student Paper Competitions in conjunction with all Advanced Technology Workshops (ATWs) and Conferences. Students submitting their work and identifying that Yes, I m a full-time student on the abstract submission form, will automatically be considered for these competitions. The review committee will evaluate all student papers/posters and award a total of $1,000 to winning student(s). The selected student(s) must attend the event to present his or her work and receive the award. For more information on the student competition go to Abstract Deadline: March 31,

45 CHAPTER CONTACTS JANUARY/FEBRUARY 2016 CHAPTER NAME MEMBER NAME Angel - Los Angeles Maurice Lowery maurice.lowery@ngc.com Arizona Jody Mahaffey jody@ereach.co Benelux Katrien Vanneste Katrien.vanneste@elis.ugent.be California Orange Bill Gaines William.gaines@ngc.com Carolinas Rex Anderson rexanderson@rti.org Central Texas Rick Prekup rprekup@iondsn.com Chesapeake Erica Folk erica.folk@ngc.com Cleveland/Pittsburgh John Mazurowski jmazurowski@eoc.psu.edu Empire - New York State Andy Mackie amackie@indium.com Florida Mike McEntee Mike.McEntee@PrecisionTestSolutions.com France Florence Vireton Imaps.france@imapsfrance.org Garden State Will Nicholson wnicholson@aitechnology.com Germany Ernst Eggelaar ee@microelectronic.de Indiana Ray Fairchild m.ray.fairchild@delphi.com Italy Marta Daffara info@imaps-italy.it Japan Orii Yasumitsu ORII@jp.ibm.com Metro Scott Baldasserre Scott.Baldassarre@aeroflex.com New England John Blum jbblum1@gmail.com NorCal Anwar Mohammed Anwar.Mohammed@flextronics.com Nordic Terho Kutilainen treasurer@imapsnordic.org Northwest Steve Annas SAnnas2180@aol.com San Diego Casey Krawiec krawiec33@sbcglobal.net Taiwan Wun-Yan Chen wunyan@itri.org.tw United Kingdom Andy Longford Andy.longford@imaps.org.uk Viking - Minnesota and Dakotas Mark Hoffmeyer hoffmeyr@us.ibm.com 43

46 ADVANCING MICROELECTRONICS ADVERTISER HOTLINE ADVERTISER CONTACT TELEPHONE WEBSITE PAGE Amkor Technology, Inc. Debi Polo ASE Group Patricia MacLeod IMAPSource Brian Schieman www. imaps.org Indium Rick Short Master Bond Robert Micheals Mini-Systems, Inc. Craig Tourgee back cover NAMICS Kevin A. McLaughlin Oneida Research Services, Inc. Deborah A. Delluomo (315) , X Advancing Microelectronics 2016 Editorial Schedule Issue Theme Copy Deadline Ad Commitment I/Os Deadline Mar/April 3D including 3DIC and 3D Pkg.(POP) Jan. 8 Jan. 13 May/Jun Internet of Things Mar. 8 Mar. 14 Jul/Aug 2016 Show Issue May 8 May 13 Sept/Oct MEMS and Thermal Management Jul. 8 July 13 Nov/Dec Ceramic Thick & Thin Sep.8 Sep. 13 IMAPS HEADQUARTERS WHO TO CALL Michael O Donoghue, Executive Director, (919) , modonoghue@imaps.org, Strategic Planning, Contracts and Negotiations, Legal Issues, Policy Development, Intersociety Liaisons, Customer Satisfaction, Exhibits, Meetings Brian Schieman, Director of Programs, (412) , bschieman@imaps.org, Development of Society Programs, Website Development, Database Management, Communication Tools and other Technology, Exhibits, Publications Ann Bell, Manager, Managing Editor, Advancing Microelectronics, (703) , abell@imaps.org, Public Relations, Marketing, Fundraising, Advertising Brianne Lamm, Membership & Events Manager, (919) , blamm@imaps.org, Member Relations and Services Administration, Dues Processing, Membership Invoicing, Foundation Contributions, Data Entry, Mail Processing, Address Changes, Telephone Support 44

47 CALENDAR OF EVENTS 2016 JANUARY start end Advanced Technology Workshop on Advanced Packaging for Wireless Medical Devices San Diego, CA FEBRUARY Advanced Technology Workshop & Tabletop Exhibition on Wire Bonding Toll House, Los Gatos, CA MARCH th International Conference and Exhibition on Device Packaging Scottsdale/Fountain Hills, AZ APRIL RaMP Workshop and Tabletop Exhibition San Diego, CA Advanced Technology Workshop on Chip-Package Interactions with Fan-out Wafer Level Packaging 2016 San Diego, CA IMAPS/ACerS 12th International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT 2016) Denver, CO th Symposium on Polymers for Microelectronics Innovations Driving a Smart and Interconnected World Winterthur, DE MAY International Conference on High Temperature Electronics (HiTEC 2016) Albuquerque, NM JUNE Advanced Technology Workshop & Tabletop Exhibits on Additive Manufacturing & Printed Electronics UMass Lowell Inn and Conference Center, Lowell, MA OCTOBER IMAPS 2016 Pasadena, CA Visit for links to all upcoming events including: full event descriptions abstract submissions exhibition information event updates

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