Cross-Layer Approaches for Resilient System Design

Transcription

1 Cross-Layer Approaches for Resilient System esign Mehdi Tahoori INSTITUTE OF COMPUTER ENGINEERING (ITEC) CHAIR FOR EPENABLE NANO COMPUTING (CNC) KIT University of the State of Baden-Wuerttemberg and National Research Center of the Helmholtz Association

2 Robust Computing at Nanoscale Failures, unpredictability and variations CMOS devices/circuits/systems become more unreliable ue to various factors at nanoscale iscussed later in this talk/session More system complexity More failures at manufacturing and during runtime operation Computing systems in all aspect of our daily lives Critical applications: medical, financial, energy, transport, etc Need for higher reliability Robust computing eveloping more reliable hardware and software Based on unreliable nanoscale devices Mehdi Tahoori 2

3 Soft Error Trend Soft Errors caused by radiation-induced particle strikes Strike releases electron & hole pairs Absorbed by source & drain Alter transistor state source Particle Strike drain Transistor evice System Soft Error Rate (SER) grows exponentially with Moore s law [ixit11irps][ibe10te] Number of transistors per system is proportional to SER Recent experiments show that SER ratio of combinational logic become comparable with sequential elements [Mahatme11TNS][Gill09IRPS] SoftError Rate (Normalized) SER vs. esign Rule [adapted from Ibe10TE] esign Rule (nm) Mehdi Tahoori 3

4 Soft Error Masking Architecture Gate-Level Register Masking: Transfer Level Failure Masking Register Branch Soft File Prediction, Combinational Speculative Logic Bit Execution Error Error is only detected (no recovery) etected, but unrecoverable error (UE) Microprocessor Control Unit yes ALU Unit Branch Prediction Bit has error protection yes yes Cache Reg File Error can be corrected (e.g, ECC) no error Read Error no masked System no No Failure yes Silent ata Corruption (SC) benign fault no error oes bit matter? no benign fault no error Mehdi Tahoori 4

5 Power Supply Noise ue to current drawn from power grid V seen by gates < nominal V Sensitivity to Power Supply Noise increases Shrinking technology Increasing functional frequency Increasing density Reduced noise margins elay increase (a.u.) 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% V (V) Mehdi Tahoori 5

6 Transistor Aging Bias Temperature Instability NBTI (PBTI) PMOS (NMOS) Vth circuit delay timing failure Causes SiH + h + Si + + H Trap generation at Si/SiO 2 interface H + H H 2 iffusion of Hydrogen ions from the interface regions Aging depends on Supply voltage, Temperature Usage (signal probability) SubstrateGate Oxide Si H Si H Si H H 2 Poly Mehdi Tahoori 6

7 Transistor Aging Hot Carrier Injection (HCI) Cause Carriers accelerated along conducting channel Collision with substrate atoms Generation of electron / hole pairs Effect Oxide damage due to interface states Shifts Vth ecrease in carrier mobility Aging depends on Supply voltage Temperature Usage: activity factor, frequency Mehdi Tahoori 7

8 Other Wearout Mechanisms Electro-migration Cause: Migration of metal ions over time in interconnects Effects: Increase in trace impedance Open and short circuits (hard faults) Unidirectional current: Power rails Trend: getting worse as wires become smaller and chips become hotter (Electro-migration) Electromigration Mehdi Tahoori 8

9 Other Wearout Mechanisms TB: Time ependent ielectric Breakdown Cause: Accumulation of trapped charges at dielectric Effects: Increase of power consumption Slowing of switching speed Trend: getting worse as gate oxides become thinner only a handful of atoms thick! A major problem for FinFETs TB Mehdi Tahoori 9

10 Variation Variability of transistor structures Channel Length Oxide thickness Randomized opant Fluctiations (RF) Random vs systematic Local (with die) and global (die to die) Mehdi Tahoori 10

11 PVT Variability and Aging Time [years] Mehdi Tahoori 11

12 Bugs vs efects vs Reliability Failures Example of parametric variability causing a hard fault! Making an SRAM cell so asymmetric that it can no longer store one of it s two stable states. Mehdi Tahoori 12

13 The bathtub curve Infant mortality: Increasing time 0 escape defects Normal lifetime: Increasing transient errors Wearout: Acceleration of aging phenomena Mehdi Tahoori 13

14 Traditional way of design margin When designers design they have to build design margin Against environmental and aging mechanisms The margin is inserted at the timing level s.t. the operating frequency of the chip will allow for correct operation esigners either (a) Add independent margins for each mechanism, or (b) Perform some sort of statistical root mean square sum (RSS) Current methodologies are not able to treat systematic relationships between these sources of margin: E.g., between power supply and aging, workload and temperature, and so on Timing failures Source: IBM Mehdi Tahoori 14

15 Challenges: esign Interdependence of various sources of unreliability Process vs. runtime variations Spatial and temporal Process Variation (PV) BTI (V th change) HCI (V th change) Voltage droop Temperature TB Electromigration (EM) Relation to post-silicon debug timing/electrical bugs Reliability Mehdi Tahoori 15

16 Challenges: esign Workload dependency Error generation: workload-dependent timing faults Error propagation: at multiple layers to user-visible failures How to factor workload dependency at design time? Better-than-worst-case design electrical/timing bugs Mehdi Tahoori 16

17 Robust esign: new approach Main approach 1. Cross-layer robust design From circuit to software Reliability as a main design constraint Balance reliability, performance, power, cost 2. Runtime and dynamic adaptation esign-time solutions insufficient Spatial and temporal (aging) variations Lots of sensors, monitors First step Modeling of various reliability factors At different levels of abstraction Interplay of various phenomena To be used in the design flow Mehdi Tahoori 17

18 Cross-layer Approach Noise, Aging, and Variation Aware Resilient System esign using a System-to-Circuit Approach Holistic approach: various noise, aging, and variations Link between device-circuit parameters and system-level runtime usage Cross-layer reliability technique Hierarchical failure models Built on top of EA tool chains Scales very well Circuit-to-system robust design Mehdi Tahoori 18

19 Cross-layer Timing Analysis Incorporate runtime variations into circuit-level timing analysis Workload-dependent ifferent time scales Performing system-level profiling Projecting effects into the circuit-level Consider combined effects of voltage, temperature, and BTI Reduces the inaccuracy w.r.t independent analysis Spatial and temporal variations Accurately handle different time scales Close to transistor level delay characterization Layout and circuit parameters Look-Up Table (LUT) based timing analysis High accuracy and low runtime Built on top of commercial EA tool Scales very well Mehdi Tahoori 19

20 Overall flow Mehdi Tahoori 20

21 NAVA flow System-level workload profiling Usage and input patterns (signal probability and activity of each PI) Power information Using fast high-level simulation to obtain profiles at the inputs of blocks/modules E.g. performance simulators Circuit-level simulation of system-level profiles Link layer between system-level profiles and circuit-level timing analysis Using profiles obtained for the inputs of each block Logic level usage of each individual gate Effective duty cycle of each transistor Hierarchical approach scalable for complex systems Mehdi Tahoori 21

22 Voltage-Temperature profiling & BTI estimation Interdependence of various parameters V TH + Leakage Temperature + + Voltage droop BTI + Mehdi Tahoori 22

23 Voltage-Temperature profiling & BTI estimation Proposed flow consists of two nested loops: Inner loop: Power, temperature, and voltage Outer Loop BTI (V th shift) Temp Leakage Voltage droop BTI Mehdi Tahoori 23

24 Voltage droop model Power grid modeled as an RC network Voltage droop: function of drawn current from each grid V G 1 * I Current of each grid ynamic & leakage power Resistance (R): R r0 (1 c* T ) Mehdi Tahoori 24

25 Temperature model Analogy between thermal and Electrical I V T R E R T Package ivided to several cubes Extracting equivalent thermal circuit (i,j,k+1) (i,j+1,k) (i 1,j,k) (i+1,j,k) (i,j 1,k) (i,j,k 1) Mehdi Tahoori 25

26 Preliminary Results: Setup Benchmark: IWLS and ISP benchmark circuits Library: Nangate 45 nm library Synthesis: Synopsys esign Compiler Place and Route: Cadence SOC Encounter Cell characterization: HSPICE Temperature estimation: HotSpot Voltage droop: Matlab Timing analysis: Synopsys PrimeTime Workstation: Intel Xeon E GHz, 16GB RAM Mehdi Tahoori 26

27 Effect of runtime variations on delay (1) (2) (3) (4) (5) Error Runtime # of cells +V-T-BTI -V+T-BTI-V-T+BTI Proposed of (4) (sec) b17 27k 6% 6% 6% 17% 22% 25% 654 B18 88k 9% 6% 6% 21% 25% 16% 978 B19 165k 8% 7% 8% 22% 32% 29% 1071 B22 40k 9% 7% 6% 17% 23% 24% 658 sp 42k 2% 6% 17% 25% 28% 13% 444 Leon2 995k 3% 9% 11% 23% 29% 20% 3245 Leon3mp 721k 3% 7% 15% 25% 30% 18% 2458 vga_lcd 114k 5% 16% 21% 41% 48% 14% 1059 Risc 61k 10% 10% 13% 33% 39% 16% 754 des_perf 84k 2% 19% 19% 40% 44% 10% 1060 Average 17% V (Voltage), T (Temperature) and BTI 1) +V-T-BTI: Only voltage droop, 2) V+T-BTI: Only temperature 3) -V-T+BTI: Only BTI, 4) Stacking (1+2+3) 5) +V+T+BTI (proposed): Combined effects of 1,2,3 RELATIVE CIRCUIT ELAY INCREASE W.R.T. -V-T-BTI (0) Mehdi Tahoori 27

28 ExtraTime Architecture Level Performance simulator including microarchitectural models for power, temperature and aging ExtraTime is based on the GEM5 simulator Input: processor specification and application; Output: performance statistics Power model (based on McPAT) Input: architecture, technology, performance statistics; Output: area and power Temperature model (based on HotSpot) Input: power, chip floorplan, technology parameters; Output: temperature

29 Aging Architecture Level Clock gating, power gating, Instruction scheduling Pro-active dynamic runtime adaptation (RA), e.g. VFS Mehdi Tahoori 29

30 Cross-layer Soft Error Modeling Mehdi Tahoori 30

31 Layout-aware SER Analysis Mehdi Tahoori 31

32 Correlated Error Propagation (CEP) Analytical reliability modeling for logic-level designs Modeling error propagation with correlation Error propagation function and super gate Unified treatment of correlated error and signal probabilities Correlation coefficient method[ercolani89etc] Mehdi Tahoori 32

33 CEP i = i primary output number Case Study (OpenRISC 1200 ALU) Error statistics for primary outputs running BasicMath application Mehdi Tahoori 33

34 CLASS: Combined Logic Architecture Soft Error Sensitivity Analysis Existing SER estimation methods: Circuit-level techniques irregular structures (controller unit, pipeline) Cannot model architecture and application-level masking factors Architecture-level techniques regular structures (register-file, cache) Cannot model circuit-level masking factors Microprocessors Intense interaction between regular and irregular structures Error may remain latent in a regular structure for long time Mehdi Tahoori 34

35 CLASS: Combined Logic Architecture Soft Error Sensitivity Analysis Irregular Structures Phase III Joint Analysis Regular Structures TMC Mehdi Tahoori 35

36 Conclusions Shortcoming of existing approaches Conservative additive margins from different sources of unreliability Broken link between system-level and circuit-level analysis Runtime variation is highly workload-dependent Our approach Holistic consideration of various sources of noise and unreliability Cross-layer: from system to circuit Impact of workload is considered Robust circuit design Reliability hotspot identification and mitigation Cell-to-array robust design Optimized cells/blocks for different workloads/systems Mehdi Tahoori 36