On-chip Networks in Multi-core era

Transcription

1 Friday, October 12th, 2012 On-chip Networks in Multi-core era Davide Zoni PhD Student webpage: home.dei.polimi.it/zoni

2 Outline 2 Introduction Technology trends and challenges Power, performance, thermal, reliability Towards Multi-core architectures Design issues Current communication subsystems and their limitations

3 Some slides adapted from... 3 Specific References Timothy M. Pinkston, University of Southern California, On-Chip Networks, Natalie E. Jerger and Li-Shiuan Peh Principles and Practices of Interconnection Networks, William J. Dally and Brian Towles Other people Chita R. Das Penn State NoC Research Group Li-Shiuan-Peh, MIT Onur Mutlu, CMU Karen Bergman, Columbia Bill Dally, Stanford Rajeev Balasubramoniam, Utah Steve Keckler, UT Austin Valeria Bertacco, University of Michigan

4 Many-core evolution 1 4 Heterogeneous Processors Performance # of cores 10 0 Intel Polaris(80-core) 4 Sun Intel IBM Cell Intel Single-chip cloud computer Intel Tilera-64 Core i5, i7 Tile-GX Larrabee Gap Performance/Watt Performance Source: Das, C. Interconnection networks. 7th ACACES Summer School, 2011, Fiuggi, July Time

5 Many-core evolution 2 5 Increasing number of cores per chip demands for increasing communication bandwidth and capability Data from ITRS 2008 i7 core ~ 4 Atom cores By 2022, 100 Atom cores on 1 Chip!! Source: International Technology Roadmap for Semiconductors, Design chapter, 2008.

6 Rationale behind Many-core revolution 6 There is a need for even more performance (and of course device portability) Applications Compete for resources QoS specification required Different Priority levels Embedded Systems Limited resources Optimized power consumption

7 Technology scaling 7 Continuous scaling allows for microarchitectural advances, but at the cost of increasing power density and area Source: Borkar, S. Thousand Core Chips A Technology Perspective. Design Automation Conference (DAC) 2007, , June 2007.

8 Computing Power Wall 8 Until early 2000, the right recipe was Increase Frequency to get better performance underpinned by technology scaling but P ~ CV 2 f Thermal Issues (considering area constant due to technology scaling) Power Issues ( towards low power design)

9 Computing Power Wall 9 Until early 2000, the right recipe was Increase Frequency to get better performance underpinned by technology scaling Thermal Issues (considering area constant due to technology scaling) but P ~ CV 2 f Frequency Increasing is not the right solution definitely Power Issues ( towards low power design)

10 Memory and Power Wall 10 We are in a supply voltage plateau P ~ CV 2 f Lower V can reduce P But, speed decreases with V Memory bandwidth: Pin count increases only 4x compared to 25x increases in cores Computational must be sustained by adequate memory subsystems High performance MOS started out with 12V (~1980) Current high-perf. MOS have 1V supply => (12/1) 2 = 144x over 28 years. Multiple write ports on the same memory are quite difficult to design Foreseen Only (1/0.6)2 = 2.77x left in next 12 years!

11 The solution...until now!!! 11 Technology scaling can help performance improvement, paying attention to power densities (Thermal and power consumption) It should be too simple :(

12 Technology scaling drawbacks: Interconnect b FPU 0.015mm 2 64b 1 mm channel 2pJ/word 64b Off-Chip channel (64pJ/word) Operation 64bit Integer Add 1 IFetch 33 Read 64bit register Energy (pj) 3.5 Read 64bit RAM 25 Move 64bit 1mm 8 Move 64bit 20mm Move 64 bit offchip

13 Technology scaling drawbacks: Interconnect 2 13 Global against local wiring delay Global interconnects are not scaling like gate delays 250 nm Gate Delay Global Wiring 32 nm Global Wiring Delay Dominates

14 Technology scaling drawbacks: Reliability 1 14 Small transistor = Big problems Parametric variations Electro-migration Failure due to fragility Soft-errors Small transistor = more transistors in the same chip More complex designs Escaped design bugs

15 Technology scaling drawbacks: Reliability 2 15 Paradox Situations Technology scaling leads to fragile transistors Reliable system design: Providing digital design solutions that deliver the Reliable systems built on an unreliable silicon substrate Electronic devices must be reliable to have value

16 Reliability: Causes of failure 16 Hw/Sw Design Errors (bugs are expensive to detect and expose security holes) Transient Faults (due to cosmic rays and/ or voltage variations) Thermal issues Increasing heat High leakage Parametric Variation (technology scaling increases process variation effects) High power dissipation

17 Reliability: Causes of failure 17 Hw/Sw Design Errors (bugs are expensive to detect and expose security holes) Transient Faults (due to cosmic rays and/ or voltage variations) Thermal issues Increasing heat High leakage Parametric Variation (technology scaling increases process variation effects) High power dissipation

18 Reliability: Fault Classes 18 Transient Faults (soft errors) Permanent Faults (hard faults) Power supply and Interconnect noises Irreversible physical change Electromagnetic interference Latent manufacturing defects Electrostatic discharge Electro-migration Neutron/Alpha particle strikes Thermal and high power supply Thermal issues can induce them Overclocking

19 Reliability: Hard Faults vs Escaped Bugs 19 Escaped design bugs (some distinguish between the two classes) Due to design errors that escape validation Typically 100 in a modern processor design Their number increases with design complexity They are called issue specification updates ( not bugs :)) )

20 Reliability: Bugs vs Validation 20 Escaped design bugs Logic simulation Test all possible input vectors and check the output values Formal methods Write the formal circuit problem and work on this formalization OK, but how these techniques really work?

21 Reliability: Formal Methods vs Simulation 21 Simulation-based solution Very large validation space Visit system configuration individually Formal methods Computationally intensive Can really handle small blocks

22 Reliability: The real problem 22 Growing complexity of digital systems (500M transistors) (5millions latches 2millions states) Static view (design time) Verified (bug free) Possible escaped bugs

23 Reliability: The real problem 23 Growing complexity of digital systems (500M transistors) (5millions latches 2millions states) Dynamic view (run-time) Verified (bug free) Possible escaped bugs

24 Reliability: The real problem 24 Growing complexity of digital systems (500M transistors) (5millions latches 2millions states) Where is the cheat??

25 Reliability: The real problem 25 Growing complexity of digital systems (500M transistors) (5millions latches 2millions states) Where is the cheat?? Only a small fraction of states are really visited at run-time We verify them only ( escaped bugs are still possible!!!!! )

26 Summarize 1 26 Moore's law predicts a doubled number of transistors in the same chip every 18 months This means huge raw computational power

27 Summarize 1 27 Moore's law predicts a doubled number of transistors in the same chip every 18 months This means huge raw computational power The right question is How can we exploit such raw power??

28 Summarize 28 Only a couple of problems... Power Densities Thermal issues Reliability (MTTF) Escaped Bugs (too complex designs) Consumption High Power Consumption

29 Multi-core: Overview Multi-chip cores are not appropriate for power/performance optimization because of the off-chip energy requirements 29 Multi-core chips provide better power management Cache Power 4 Large Core Performance Power = 1/4 Small Performance = 1/2 Core C1 C3 Cache C2 C

30 Multi-core: Benefits 30 Multi-chip cores are not appropriate for power/performance optimization because of the off-chip energy requirements Better power management Easy validation (less escaped bugs) C1 C2 4 4 Easy performance prediction Cache 3 3 Explicit parallelism C3 C Hierarchy design approach (Core multicore FU core )

31 Multi-core: ReThink Design Multi-chip cores are not appropriate for power/performance optimization because of the off-chip energy requirements 31 Better power management new power management techniques Easy validation (less escaped bugs) multicore!=single core Easy performance prediction multicore!=single core Explicit parallelism after Tomasulo...Cuda,OpenCl,OpenMp,MPI Hierarchy design approach more degree of freedom, but multiple design levels (Core multicore FU core )

32 Multi-core: The main issues (for us :)) ) 32 Multi-chip cores need an appropriate communication subsystem What about bus-based architectures??

33 Interconnect design 33 Classical approaches are no longer appropriate for increasing communication requirements Approach Pros Cons bus Standardized Low area Easy to implement Easy cache coherence support Contention increases with cores Global long wires point-to-point Very efficient dedicated links O(n2 ) links What about link failure? Crossbar Non-blocking system Scalable, flexible Power consumption Global/long wires

34 Communication-centric design 34 A flexible, scalable and power-efficient interconnection design is required Network-on-Chip architectures provide a mean to cope with increasing system complexity and communication requirement Within the power envelope Replace global wires with a resource-constrained network Structured inteconnect layout From computation-centric to communication-centric design