Rating Symbol Value Unit Drain Source Voltage VDSS 65 Vdc Drain Gate Voltage (RGS = 1.0 MΩ)

Transcription

1 SEMICONDUCTOR TECHNICAL DATA Order this document by MRF275G/D The RF MOSFET Line N Channel Enhancement Mode Designed primarily for wideband large signal output and driver stages from 1 5 MHz. Guaranteed 5 MHz, 28 Vdc Output Power 15 Watts Power Gain 1 db (Min) Efficiency 5% (Min) 1% Tested for Load Mismatch at all Phase Angles with VSWR 3:1 Overall Lower 28 V Ciss 135 pf Coss 14 pf Crss 17 pf Simplified AVC, ALC and Modulation D 15 W, 28 V, 5 MHz N CHANNEL MOS BROADBAND 1 5 MHz RF POWER FET Typical data for power amplifiers in industrial and commercial applications: Typical 4 MHz, 28 Vdc Output Power 15 Watts Power Gain 12.5 db Efficiency 6% Typical 225 MHz, 28 Vdc Output Power 2 Watts Power Gain 15 db Efficiency 65% G G D S (FLANGE) CASE 375 4, STYLE 2 MAXIMUM RATINGS Rating Symbol Value Unit Drain Source Voltage VDSS 65 Vdc Drain Gate Voltage (RGS = 1. MΩ) VDGR 65 Vdc Gate Source Voltage VGS ±4 Adc Drain Current Continuous ID 26 Adc Total Device TC = 25 C Derate above 25 C PD Storage Temperature Range Tstg 65 to +15 C Operating Junction Temperature TJ 2 C THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Thermal Resistance, Junction to Case RθJC.44 C/W Watts W/ C NOTE CAUTION MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed. 1

2 ELECTRICAL CHARACTERISTICS (TC = 25 C unless otherwise noted) OFF CHARACTERISTICS (1) Drain Source Breakdown Voltage (VGS =, ID = 5 ma) Zero Gate Voltage Drain Current (VDS = 28 V, VGS = ) Gate Source Leakage Current (VGS = 2 V, VDS = ) ON CHARACTERISTICS (1) Characteristic Symbol Min Typ Max Unit V(BR)DSS 65 Vdc IDSS 1 ma IGSS 1 µa Gate Threshold Voltage (VDS = 1 V, ID = 1 ma) VGS(th) Vdc Drain Source On Voltage (VGS = 1 V, ID = 5 A) VDS(on) Vdc Forward Transconductance (VDS = 1 V, ID = 2.5 A) gfs mhos DYNAMIC CHARACTERISTICS (1) Input Capacitance (VDS = 28 V, VGS =, f = 1 MHz) Ciss 135 pf Output Capacitance (VDS = 28 V, VGS =, f = 1 MHz) Coss 14 pf Reverse Transfer Capacitance (VDS = 28 V, VGS =, f = 1 MHz) Crss 17 pf FUNCTIONAL CHARACTERISTICS (2) (Figure 1) Common Source Power Gain (VDD = 28 V, Pout = 15 W, f = 5 MHz, IDQ = 2 x 1 ma) Drain Efficiency (VDD = 28 V, Pout = 15 W, f = 5 MHz, IDQ = 2 x 1 ma) Electrical Ruggedness (VDD = 28 V, Pout = 15 W, f = 5 MHz, IDQ = 2 x 1 ma, VSWR 3:1 at all Phase Angles) 1. Each side of device measured separately. 2. Measured in push pull configuration. Gps db η 5 55 % ψ No Degradation in Output Power 2

3 A B +VGG C14 R1 C15 C16 C22 C17 L5 C18 L6 C V L1 L3 C1 Z1 Z3 D.U.T. Z5 Z7 C1 C2 B1 C5 C6 C7 C8 C3 C9 C11 C12 B2 C4 Z2 Z4 Z6 Z8 C13 L2 L4 A C2 C21 B B1 Balun, 5 Ω,.86 O.D. 2 Long, Semi Rigid Coax B2 Balun, 5 Ω, Coax.141 O.D. 2 Long, Semi Rigid C1, C2, C3, C4, C1, C11, C12, C13 27 pf, ATC Chip Capacitor C5, C pf, Trimmer Capacitor, Johanson C6 22 pf, Mini Unelco Capacitor C7 15 pf, Unelco Capacitor C9 2.1 pf, ATC Chip Capacitor C14, C15, C16, C2, C21, C22.1 µf, Ceramic Capacitor C17, C18 68 pf, Feedthru Capacitor C19 1 µf, 5 V, Electrolytic Capacitor, Tantalum L1, L2 1 Turns AWG #24,.145 O.D., 16 nh Taylor Spring Inductor L3, L4 1 Turns AWG #18,.34 I.D., Enameled Wire Figure 1. 5 MHz Test Circuit L5 Ferroxcube VK2 2/4B L6 4 Turns #16,.34 I.D., Enameled Wire R1 1. kω,1/4 W Resistor W1 W4 2 x 2 x 25 mils, Wear Pads, Beryllium Copper, (See Component Location Diagram) Z1, Z2 1.1 x.245, Microstrip Line Z3, Z4, Z5, Z6.3 x.245, Microstrip Line Z7, Z8 1. x.245, Microstrip Line Board material.6 Teflon fiberglass, εr = 2.55, copper clad both sides, 2 oz. copper. Points A are connected together on PCB. Points B are connected together on PCB. 3

4 TYPICAL CHARACTERISTICS 3 16, OUTPUT POWER (WATTS) Pout MHz Pin, INPUT POWER (Watts) 4 MHz IDQ = 2 x 1 ma VDD = 28 V 2 5 MHz 25, OUTPUT POWER (WATTS) Pout VDS = 28 V IDQ = 2 x 1 ma 2 Pin = Constant f = 5 MHz VGS, GATE SOURCE VOLTAGE (V) 4 Figure 2. Output Power versus Input Power Figure 3. Output Power versus Gate Voltage, DRAIN CURRENT (AMPS) I D VDS = 1 V VGS(th) = 2.5 V, OUTPUT POWER (WATTS) Pout Pin = 14 W 1 W 6 W IDQ = 2 x 1 ma f = 5 MHz VGS, GATE SOURCE VOLTAGE (V) VDD, SUPPLY VOLTAGE (V) Figure 4. Drain Current versus Gate Voltage (Transfer Characteristics) Figure 5. Output Power versus Supply Voltage, OUTPUT POWER (WATTS) Pout Pin = 14 W 12 W W 1 W W Pin = 4 W IDQ = 2 x 1 ma 5 IDQ = 2 x 1 ma f = 225 MHz 2 f = 4 MHz VDD, SUPPLY VOLTAGE (V) VDD, SUPPLY VOLTAGE (V), OUTPUT POWER (WATTS) Pout Figure 6. Output Power versus Supply Voltage Figure 7. Output Power versus Supply Voltage 4

5 TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) Coss Ciss Crss VGS = V f = 1. MHz, GATE SOURCE VOLTAGE (NORMALIZED) VDD = 28 V 3 A ID = 4 A 2 A.1 A VDS, DRAIN SOURCE VOLTAGE (V) 25 3 VGS TC, CASE TEMPERATURE ( C) 2 Figure 8. Capacitance versus Drain Source Voltage* *Data shown applies only to one half of device, MRF275G Figure 9. Gate Source Voltage versus Case Temperature 1, DRAIN CURRENT (AMPS) I D 1 TC = 25 C VDS, DRAIN SOURCE VOLTAGE (V) Figure 1. DC Safe Operating Area 5

6 VDD = 28 V, IDQ = 2 x 1 ma, Pout = 15 W f = 5 MHz f (MHz) Zin Ohms ZOL* Ohms j j j j j j1.3 4 Zin f = 5 MHz 4 ZOL* 225 Zo = 1 Ω ZOL* = Conjugate of the optimum load impedance ZOL* = into which the device operates at a given ZOL* = output power, voltage and frequency. Note: Input and output impedance values given are measured from gate to gate and drain to drain respectively. 225 Figure 11. Series Equivalent Input/Output Impedance 6

7 A B C14 L5 C15 L6 BIAS C1 C11 R1 C12 C13 R2 C18 28 V L3 C1 D.U.T. L1 C8 Z1 Z3 Z5 B1 C3 C4 C5 C6 C7 B2 C2 L2 Z2 Z4 Z6 C9 R3 L4 A C16 C17 B.18 B1 Balun, 5 Ω,.86 O.D. 2 Long, Semi Rigid Coax B2 Balun, 5 Ω,.141 O.D. 2 Long, Semi Rigid Coax C1, C2, C8, C9 27 pf, ATC Chip Capacitor C3, C5, C pf, Trimmer Capacitor C4 15 pf, ATC Chip Capacitor C6 33 pf, ATC Chip Capacitor C1, C12, C13, C16, C17.1 µf, Ceramic Capacitor C11 1. µf, 5 V, Tantalum C14, C15 68 pf, Feedthru Capacitor C18 2 µf, 5 V, Tantalum L1, L2 #18 Wire, Hairpin Inductor L3, L4 12 Turns #18,.34 I.D., Enameled Wire L5 Ferroxcube VK2 2/4B L6 3 Turns #16,.34 I.D., Enameled Wire R1 1. kω, 1/4 W Resistor R2, R3 1 kω, 1/4 W Resistor Z1, Z2.4 x.25, Microstrip Line Z3, Z4.87 x.25, Microstrip Line Z5, Z6.5 x.25, Microstrip Line Board material.6 Teflon fiberglass, εr = 2.55, copper clad both sides, 2 oz. copper..2 Figure MHz Test Circuit 7

8 BIAS 6 V R1 C3 C4 C8 C9 L2 C V R2 D.U.T. T2 L1 T1 C5 C6 C1 C2 C7 C pf, Arco 44 C2, C3, C7, C8 1 pf, Chip Capacitor C4, C9.1 µf, Chip Capacitor C5 18 pf, Chip Capacitor C6 1 pf and 13 pf, Chips in Parallel C1.47 µf, Chip Capacitor, 1215 or Equivalent, Kemet L1 1 Turns AWG #16, 1/4 I.D., Enamel Wire, Close Wound L2 Ferrite Beads of Suitable Material for µh Total Inductance Board material 62 fiberglass (G1), εr 5, Two sided, 1 oz. Copper. Unless otherwise noted, all chip capacitors are ATC Type 1 or Equivalent. R1 R2 T1 T2 1 Ω, 1/2 W 1. k Ω, 1/2 W 4:1 Impedance Ratio, RF Transformer Can Be Made of 25 Ω, Semi Rigid Coax, Mils O.D. 1:9 Impedance Ratio, RF Transformer. Can Be Made of Ω, Semi Rigid Coax, 62 9 Mils O.D. NOTE: For stability, the input transformer T1 should be loaded NOTE: with ferrite toroids or beads to increase the common NOTE: mode inductance. For operation below 1 MHz. The NOTE: same is required for the output transformer. Figure MHz Test Circuit 8

9 L5 B1 C17 C18 + C19 R1 C16 C22 L6 C14 C15 L1 L3 BEADS 1 3 C1 C2 C3 C4 C5 W2 W1 C6 W3 W4 C7 C8 C1 C11 C9 C12 C13 L2 C2 L4 BEADS 4 6 B2 C21 MRF275G JL Figure 14. MRF275G Component Location (5 MHz) (Not to Scale) MRF275G JL Figure 15. MRF275G Circuit Board Photo Master (5 MHz) (Scale 1:1) 9

10 NOTE: S Parameter data represents measurements taken from one chip only. Table 1. Common Source S Parameters (VDS = 12 V, ID = 4.5 A) f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ 3 Á Á 6.34 Á Á Á ÁÁ ÁÁ ÁÁ ÁÁ Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ Á Á Á Á Á 3.93 Á Á Á Á Á Á Á Á Á Á Á 18 Á Á Á 9 1. Á 18 Á ÁÁÁ Á Á 178 Á ÁÁÁ Á Á 18 Á ÁÁÁ Á Á 18 Á ÁÁÁ Á Á 18 Á ÁÁÁ Á Á 18 Á ÁÁÁ Á Á Á Á Á Á Á Á Á ÁÁÁ Á Á 179 Á ÁÁÁ Á Á Á ÁÁ 1

11 Table 1. Common Source S Parameters (VDS = 12 V, ID = 4.5 A) continued f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á Á Á 19 Á.1 46 Á Á Á 12.7 Á 49 Á Á Á Á 61 Á Á Á Á 51 Á Á Á Á 72 Á Á Á Á 57 Á Table 2. Common Source S Parameters (VDS = 24 V, ID =.35 ma) f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á ÁÁÁ Á Á Á Á Á Á Á ÁÁÁ Á Á ÁÁÁ Á Á Á Á Á Á Á Á 11

12 Table 2. Common Source S Parameters (VDS = 24 V, ID =.35 ma) continued f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ 28 Á.925 Á.73 Á Á Á 29 Á.927 Á.65 Á Á Á Á.929 Á.62 Á Á Á Á.931 Á.6 Á 34.1 Á Á Á Á.57 Á 33.1 Á Á Á Á.53 Á 34.1 Á Á Á Á.56 Á 33.1 Á Á Á Á.53 Á 3.1 Á 1.9 Á 36 Á Á.5 Á 25.1 Á 1.11 Á 37 Á Á.46 Á 23.9 Á 1.8 Á 38 Á Á.44 Á 22.9 Á Á 39 Á Á.41 Á 24.8 Á Á 4 Á Á.4 Á 27.8 Á Á 41 Á Á.38 Á 26.9 Á 2 1. Á Á Á.38 Á 26.9 Á Á Á Á.37 Á 23.9 Á Á Á Á.36 Á 21.9 Á Á Á Á.36 Á 18.9 Á Á Á Á.31 Á 17.9 Á Á Á Á.3 Á 17.9 Á Á Á Á.29 Á 19.9 Á Á 49 Á Á.29 Á 2.1 Á Á 18 5 Á Á.28 Á 2.1 Á Á Á Á.24 Á 12.6 Á Á Á Á.16 Á Á Á Á Á.14 Á 1.23 Á Á Á Á.12 Á Á Á Á Á.9 Á 7.25 Á 7 1. Á 169 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á ÁÁ Table 3. Common Source S Parameters (VDS = 28 V, ID =.39 ma) f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ 3 Á Á 1.8 Á Á 4.87 Á Á Á 6.91 Á Á Á 17 5 Á Á 5.79 Á Á 5.83 Á Á Á 4.86 Á Á Á Á Á 4.41 Á Á 1.97 Á Á Á 3.87 Á 8.22 Á Á Á Á 3.49 Á Á Á Á Á 3.3 Á Á Á Á Á 2.68 Á Á Á Á Á 2.31 Á Á Á Á Á 2.3 Á Á Á 175 Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á ÁÁ 12

13 Table 3. Common Source S Parameters (VDS = 28 V, ID =.39 ma) continued f S11 S21 S12 S22 MHz S11 φ S21 φ S12 φ S22 φ ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á ÁÁÁ Á Á Á 45 Á Á Á Á Á 13 Á Á Á Á 15 Á Á Á Á 13 Á Á Á Á 1 Á Á Á Á 12 Á Á Á Á 15 Á Á Á Á 16 Á Á Á Á 16 Á Á Á Á 1 Á Á Á Á 5 Á Á Á Á 16 Á Á Á 35.9 Á 14 Á Á Á 34.9 Á 3 Á Á Á 31.1 Á 4 Á Á Á 26.1 Á 8 Á Á Á 24.9 Á 11 Á Á Á 23.8 Á 17 Á Á Á 25.8 Á 24 Á Á.946 Á Á 27.7 Á 2 Á Á.947 Á Á 26.1 Á 19 Á Á.949 Á Á Á 29 Á Á.95 Á Á 24.1 Á 41 Á Á.951 Á Á 21.8 Á 4 Á Á.953 Á Á 19.8 Á 34 Á Á.953 Á Á 17.9 Á 26 Á Á.954 Á Á 18.1 Á 3 Á Á.955 Á Á Á 43 Á Á.956 Á Á 2.12 Á 6 Á Á.957 Á Á 21.1 Á 65 Á Á.955 Á Á Á 67 Á Á.958 Á Á Á 64 Á Á.963 Á Á 9.2 Á 89 Á Á.966 Á Á 9.28 Á 81 Á Á.968 Á Á 6.33 Á 73 Á Á Á 13

14 Figure 16. MRF275G Test Fixture RF POWER MOSFET CONSIDERATIONS MOSFET CAPACITANCES The physical structure of a MOSFET results in capacitors between the terminals. The metal oxide gate structure determines the capacitors from gate to drain (Cgd), and gate to source (Cgs). The PN junction formed during the fabrication of the MOSFET results in a junction capacitance from drain to source (Cds). These capacitances are characterized as input (Ciss), output (Coss) and reverse transfer (Crss) capacitances on data sheets. The relationships between the inter terminal capacitances and those given on data sheets are shown below. The Ciss can be specified in two ways: 1. Drain shorted to source and positive voltage at the gate. 2. Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case the numbers are lower. However, neither method represents the actual operating conditions in RF applications. GA TE Cgd Cgs DRAIN Cds SOURCE Ciss = Cgd + Cgs Coss = Cgd + Cds Crss = Cgd The Ciss given in the electrical characteristics table was measured using method 2 above. It should be noted that Ciss, Coss, Crss are measured at zero drain current and are provided for general information about the device. They are not RF design parameters and no attempt should be made to use them as such. DRAIN CHARACTERISTICS One figure of merit for a FET is its static resistance in the full on condition. This on resistance, VDS(on), occurs in the linear region of the output characteristic and is specified under specific test conditions for gate source voltage and drain current. For MOSFETs, VDS(on) has a positive temperature coefficient and constitutes an important design consideration at high temperatures, because it contributes to the power dissipation within the device. GATE CHARACTERISTICS The gate of the MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The input resistance is very high on the order of 19 ohms resulting in a leakage current of a few nanoamperes. Gate control is achieved by applying a positive voltage slightly in excess of the gate to source threshold voltage, VGS(th). Gate Voltage Rating Never exceed the gate voltage rating (or any of the maximum ratings on the front page). Exceeding the rated VGS can result in permanent damage to the oxide layer in the gate region. Gate Termination The gates of this device are essentially capacitors. Circuits that leave the gate open circuited or floating should be avoided. These conditions can result in turn on of the devices due to voltage build up on the input capacitor due to leakage currents or pickup. Gate Protection These devices do not have an internal monolithic zener diode from gate to source. If gate protection is required, an external zener diode is recommended. Using a resistor to keep the gate to source impedance low also helps damp transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate drain capacitance. If the gate to source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate 14

15 may be large enough to exceed the gate threshold voltage and turn the device on. HANDLING CONSIDERATIONS When shipping, the devices should be transported only in antistatic bags or conductive foam. Upon removal from the packaging, careful handling procedures should be adhered to. Those handling the devices should wear grounding straps and devices not in the antistatic packaging should be kept in metal tote bins. MOSFETs should be handled by the case and not by the leads, and when testing the device, all leads should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it is designed for, soldering should be done with grounded equipment. DESIGN CONSIDERATIONS The MRF275G is a RF power N channel enhancement mode field effect transistor (FETs) designed for HF, VHF and UHF power amplifier applications. M/A-COM RF MOSFETs feature a vertical structure with a planar design. M/A-COM Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. The major advantages of RF power FETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal. DC BIAS The MRF275G is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain current flows when a positive voltage is applied to the gate. RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF275G was characterized at IDQ = 1 ma, each side, which is the suggested minimum value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate bias system. GAIN CONTROL Power output of the MRF275G may be controlled from its rated value down to zero (negative gain) by varying the dc gate voltage. This feature facilitates the design of manual gain control, AGC/ALC and modulation systems. 15

16 PACKAGE DIMENSIONS R E K D U G N 5 Q RADIUS 2 PL B J.25 (.1) M T A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E G H J K N Q R U 1.1 BSC BSC H A C T SEATING PLANE STYLE 2: PIN 1. DRAIN 2. DRAIN 3. GATE 4. GATE 5. SOURCE CASE ISSUE D Specifications subject to change without notice. North America: Tel. (8) , Fax (8) Asia/Pacific: Tel , Fax Europe: Tel. +44 (1344) , Fax+44 (1344) 3 2 Visit for additional data sheets and product information. 16