50V/5.3A P-Channel Power MOSFET MSS5P05D / MSS5P05U. General Description. Features. Pin Configuration DPAK (TO-252) IPAK (TO-251) MSS5P05U MSS5P05D
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1 50V/5.3A P-Channel Power MOSFET 50V/5.3A P-Channel Power MOSFET General Description Low on resistance Improved inductive ruggedness Fast switching time Rugged polysilicon gate cell structure Lower input capacitance Extended safe operating area Improved high temperature reliabillty DPAK (TO-252) Features IPAK (TO-251) VDSS= -50V, ID= -5.3A RDS(ON) 0.5 VGS= -10V Pin Configuration MSS5P05D MSS5P05U 1: GATE 2: DRAIN 3: SOURCE 1: GATE 2: DRAIN 3: SOURCE DPAK (TO-252) IPAK (TO-251) TAITRON COMPONENTS INCORPORATED Tel: (800)-TAITRON (800) (661) Fax: (800)-TAITFAX (800) (661) Page 1 of 11
2 Absolute Maximum Ratings Symbol Description P-Channel Unit VDSS Drain-Source Voltage (1) -50 Vdc VDGR Drain-Gate Voltage (RGS =1.0MΩ) (1) -50 Vdc VGS Gate-Source Voltage ± 20 Vdc ID Drain Current Continuous Tc=25 C -5.3 Adc ID Drain Current Continuous Tc=100 C -3.3 Adc IDM Drain Current - Pulsed (2) -21 Adc IGM Gate Current - Pulsed ± 1.5 Adc EAS Single Pulsed Avalanche Energy (3) 240 mj IAS Avalanche Current -5.3 A PD Total Power Dissipation T C=25 ºC Derate above 25 ºC W W/ C TJ Junction Temperature +150 C TSTG Storage Temperature Range -55 to +150 C TL Maximum Lead Temp. for Soldering Purposes, 1/8 from case for 5 seconds 300 C Note: (1) T J=25 C to 150 C (2) Repetitive rating: Pulse width limited by max. junction temperature (3) L=9.7mH, Vdd=-25V, R G=25Ω, Starting T J=25 C Electrical Characteristics (Tc =25ºC unless otherwise specified) Off Characteristics V(BR)DSS Drain-Source Breakdown Voltage V VGS=0V, ID=-250µA IDSS Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current - - ±100 na VGS=±20V On Characteristics ua VDS=-Max. Rating, VGS=0V VDS=-0.8 Max. Rating, VGS=0V,Tc=125 C VGS(th) Gate Threshold Voltage V VDS=VGS, ID=-250μA Page 2 of 11
3 RDS(ON) Static Drain-Source On-State Resistance (4) Ω VGS=-10V, ID=-2.7A g FS Forward Transconductance (4) S VDS=-50V, ID=-2.7A Note: (4) Pulse test: Pulse width 300us, Duty cycle 2% Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance pf VDS=-25V, VGS=0V, f=1mhz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge (Gate- Source Plus Gate-Drain) Qgs Gate-Source Charge Qgd Gate-Drain Charge ns nc VDD=-05BVDSS, RL=24Ω, ID=-5.3A, (MOSFET switching times are essentially independent of operating temperature) VGS=-10V, ID=-5.3A, VDS=0.8 Max. Rating, (Gate charge is essentially independent of operating temperature) Drain-Source Diode Characteristics and Maximum Ratings Is IsM Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) (note) A A Vsd Diode Forward Voltage V Trr Reverse Recovery Time ns Modified MOSFET symbol showing the integral reverse P-N junction rectifier- IS=-5.3A, VGS=0V,TJ=25 C IF=-5.3A, dif/dt=100a/μs, TJ=25 C Note: Repetitive rating: Pulse width limited by max. junction temperature Page 3 of 11
4 50V/5.3A P-Channel Power MOSFET Thermal Resistance Symbol Description Typ. Max. Unit Remark RθJC Junction-to-Case K/W RθCS Case-to-Sink K/W Mounting surface flat, smooth and greased RθJA Junction-to-Ambient K/W Free air operation Typical Characteristics Curves Fig.1- Typical Output Characteristics Fig.2- Typical Transfer Characteristics Drain-Source Voltage VDS (V) Gate-Source Voltage VGS (V) Page 4 of 11
5 Normalized Transient Thermal Resistance 50V/5.3A P-Channel Power MOSFET Fig.3- Typical Saturation Characteristics Fig.4- Maximum Safe Operation Area Drain-Source Voltage VDS (V) Drain-Source Voltage VDS (V) Fig.5- Maximum Effective Transient Thermal Response Junction-Case VS. Pulse Duration Square Wave pulse Duration t1(s) Page 5 of 11
6 Drain-Source Breakdown Voltage (V) Normalized ON Resistance RDS(ON) Gfs Transcounductance (S) Reverse Drain Current IS (A) 50V/5.3A P-Channel Power MOSFET Fig.6- Typical Transcounductance Vs. Drain Current Fig.7- Typical Source-Drain Diode Forward Voltage Source-Drain Voltage VDS (V) Fig.8- Breakdown Voltage Vs. Temperature Fig.9- Normalized On-Resisitance Vs. Temperature Junction Temperature TJ ( C) Junction Temperature TJ ( C) Page 6 of 11
7 Fig.10- Typical Gate Charge Vs. Gate-Source Voltage Fig.11- Typical Capacitance Vs. Grain-Source Voltage Gate Charge Qg (nc) Drain-Source Voltage VGS (V) Fig.12- Typical On-Resistance Vs. Drain Current Fig.13-Maximum Drain Current Vs. Case Temperature Normalized ON Resistance RDS(ON) (Ω) Gate-Source Voltage VGS (V) Capacitance (pf) Case Temperature Tc ( C) Page 7 of 11
8 Fig.14-Power Vs. Temperature Derating Curve Power Dissipation (W) Case Temperature Tc ( C) Equivalent Circuit Page 8 of 11
9 Dimensions in mm DPAK (TO-252) Page 9 of 11
10 IPAK (TO-251) Page 10 of 11
11 How to Order MS S 5 P 05 D SM T Packing Code T: 13 Tape & Reel C: Tube Factory Location Code Package Code: D: DPAK, U: IPAK Voltage Rating: 05: 50V Channel Code: P: P-Channel Ampere Code: 5.3A Technology TAITRON MOSFET How to contact us: US HEADQUARTERS WEST HARRISON PARKAWAY, VALENCIA, CA Tel: (800) TAITRON (800) (661) Fax: (800) TAITFAX (800) (661) taitron@taitroncomponents.com TAITRON COMPONENTS MEXICO, S.A.DE C.V. BOULEVARD CENTRAL 5000 INTERIOR 5 PARQUE INDUSTRIAL ATITALAQUIA, HIDALGO C.P MEXICO Tel: Fax: TAITRON COMPONENTS INCORPORATED TAIWAN, TAIPEI 5F-2, NO. 77, SEC. 1, HSIN TAI WU ROAD, HSI-CHIH, TAIPEI HSIEN, TAIWAN R.O.C. Tel: Fax: TAITRON COMPONETS INCORPORATED, SHANGHAI REPRESENTATIVE OFFICE METROBANK PLAZA, 1160 WEST YAN AN ROAD, SUITE 1503, SHANGHAI, , CHINA Tel: Fax: Page 11 of 11
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DESCRIPTION The is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. This high density process is especially tailored
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DESCRIPTION The SPP6506 is the Dual P-Channel enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored
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1 3 FEATURES RDS(ON) 110mΩ@VGS=-4.5V RDS(ON) 150mΩ@VGS=-2.5V Super high density cell design for extremely low RDS(ON) APPLICATIONS Power Management in Note book Portable Equipment Battery Powered System
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DESCRIPTION The is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to
More informationInternational В Rectifier IRFZ44
International В Rectifier IRFZ44 HEXFET Power MOSFET PD-9.510C Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Ease of Paralleling Simple Drive Requirements VDSS = 60V ^DS(on) - 0.028Q
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500V N-Channel MOSFET General Description This Power MOSFET is produced using Maple semi s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state
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DESCRIPTION The SPN166T04 is the N-Channel logic enhancement mode power field effect transistor which is produced using super high cell density DMOS trench technology. This high density process is especially
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DESCRIPTION The is the N-Channel logic enhancement mode power field effect transistor is produced using high cell density. advanced trench technology to provide excellent RDS(ON). low gate charge and operation
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