AM9435 MOSFET -30V P-CHANNEL ENHANCEMENT MODE
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- Joel Lucas
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1 DESCRIPTION The is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. This is particularly suited for low voltage application, notebook computer power management and other battery powered circuits where high-side switching. The A9435 is available in SOP8 Package ORDERING INFORMATION Package Type Part Number M8R SOP-8 M8 M8VR R: Tape & Reel Note V: Green Package AiT provides all Pb free products Suffix V means Green Package FEATURES -30V/-5.2A, R DS(ON) < 60mΩ@V GS = -10V -30V/-4.5A, R DS(ON) < 90mΩ@V GS = -6.0V -30V/-4.0A, R DS(ON) < 120mΩ@V GS = -4.5V Super high density cell design for extremely low R DS(ON). Exceptional on-resistance and maximum DC current capability. Available in SOP8 Package APPLICATION Power Management in Notebook Portable Equipment Battery Powered System DC/DC Converter Load Switch DSC LCD Display inverter P-CHANNEL REV1.0 - MAR 2010 RELEASED - 1 -
2 PIN DESCRIPTION Top View Pin # Symbol Function 1 S Source 2 S Source 3 S Source 4 G Gate 5 D Drain 6 D Drain 7 D Drain 8 D Drain REV1.0 - MAR 2010 RELEASED - 2 -
3 ABSOLUTE MAXIMUM RATINGS (TA = 25 Unless otherwise noted ) VDSS, Drain-Source Voltage -30V VGSS, Gate-Source Voltage ±20V ID, Continuous Drain Current (TJ=150 ), VGS = -10V IDM, Pulsed Drain Current -5.2A -20A IS, Continuous Source Current (Diode Conduction) 2.4A TJ, Operation Junction Temperature -55 ~150 TSTG, Storage Temperature Range -55 ~150 PD, Power Dissipation TA=25 o C 2.8W TA=70 o C 1.8W RθJA, Thermal Resistance-Junction to Ambient 70 /W Stresses above may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL INFORMATION Parameter Symbol Package Max Unit Thermal Resistance RθJA SOP-8 70 /W (Junction to Ambient) Power Dissipation, PD SOP W PD@TA=25 PD@TA=25 PD@TA=70 SOP PD@TA=70 REV1.0 - MAR 2010 RELEASED - 3 -
4 ELECTRICAL CHARACTERISTICS TA=25 unless otherwise specified. Parameter Symbol Conditions Min Typ Max Unit Drain-Source V(BR)DSS V GS =0V V Breakdown Voltage I D =-250 A Gate Threshold Voltage VGS(th) VDS =VGS,ID =-250μA V Gate Leakage Current IGSS VDS =0V,VGS=±20V - - ±100 na Zero Gate Voltage Drain Current IDSS VDS =-30V,VGS =0V VDS =-30V,VGS =0V - - µa -5 TJ =55 On-State Drain Current ID(ON) VDS -5V,VGS -10V A Drain-source On-Resistance RDS(ON) VGS =-10V,ID=-5.2A VGS =-6.0V, ID=-4.5A VGS =-4.5V, ID=-4.0A mω Forward Transconductance Gfs VDS =-10V,ID =-5.2A S Diode Forward Current (Max.) Is A Diode Forward Voltage VSD IS=-2.0A,VGS=0V V Total Gate Charge Qg VDS =-15V,VGS =-10V Gate-Source Charge QGS ID =-5.0A Gate-Drain Charge QGD Input Capacitance Ciss VDS =-15V,VGS =0V Output Capacitance Coss f =1MHz Reverse Transfer Capacitance Crss Turn-On Time td(on) Turn-Off Time Tr td(off) VDD =-15V,RL =15Ω ID =-1.0A,VGEN =-10V RG =6Ω Tf Note : 1. Pulse test: pulse width <= 300us, duty cycle<= 2% 2. Static parameters are based on package level with recommended wire-bonding nc pf ns REV1.0 - MAR 2010 RELEASED - 4 -
5 TYPICAL CHARACTERISTICS 1. On-Resistance vs. Drain Current 2. Capacitance 3. Output Characteristics 4. Transfer Characteristics 5. Gate Charge 6. On-Resistance vs. Junction Temperature REV1.0 - MAR 2010 RELEASED - 5 -
6 7. Source-Drain Diode Forward Voltage 8. On-Resistance vs. Gate-to-Source Voltage 9. Threshold Voltage 10. Single Pulse power, Junction-to-Ambient 11. Normalized Thermal Transient Impedance, Junction-to-Foot REV1.0 - MAR 2010 RELEASED - 6 -
7 PACKAGE INFORMATION Dimension in SOP-8 (Unit: mm) Symbol Min Nom Max A B C D E F G 1.27TYP H J 0.375REF K 45 L M REV1.0 - MAR 2010 RELEASED - 7 -
8 IMPORTANT NOTICE AiT Semiconductor Inc. (AiT) reserves the right to make changes to any its product, specifications, to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AiT Semiconductor Inc.'s integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT products in such applications is understood to be fully at the risk of the customer. As used herein may involve potential risks of death, personal injury, or servere property, or environmental damage. In order to minimize risks associated with the customer's applications, the customer should provide adequate design and operating safeguards. AiT Semiconductor Inc. assumes to no liability to customer product design or application support. AiT warrants the performance of its products of the specifications applicable at the time of sale. REV1.0 - MAR 2010 RELEASED - 8 -
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N-Channel IRLML (KRLML) SOT-2 2.9 -. +..4 -. +. Unit: mm Features VDS (V) = V ID =.6A (VGS = V) RDS(ON) < 22mΩ (VGS = V) RDS(ON) < 25mΩ (VGS = 4.5V) G 2.4 -. +. 2.95 -. +..9 -. +.. -. +. 5.4. -. +.5 S
More informationSymbol Parameter Rating Units VDS Drain-Source Voltage 30 V VGS Gate-Source Voltage ±20 V
% EAS Guaranteed Green Device Available Super Low Gate Charge Excellent CdV/dt effect decline Advanced high cell density Trench technology Product Summary BVDSS RDSON ID 3V mω A Description TO Pin Configuration
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More informationFeatures. Symbol Parameter Typ. Max. Unit RθJA Thermal Resistance Junction to ambient /W RθJC Thermal Resistance Junction to Case
General Description These N-Channel enhancement mode power field effect transistors are planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance,
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DESCRIPTION The SPN65T10 is the N-Channel enhancement mode power field effect transistor which is produced using high cell density DMOS trench technology. This high density process is especially tailored
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WPM9435 P-Channel Enhancement Mode MOSFET www.willsemi.com escription The WPM9435 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, MOS trench
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Power MOSFET 30V, 215mΩ, 2.0A, Single P-Channel This Power MOSFET is produced using ON Semiconductor s trench technology, which is specifically designed to minimize gate charge and low on resistance. This
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