Wafer-Level Packaging and Wafer-Scale Assembly Technologies

Transcription

1 Wafer-Level Packaging and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH Workshop 6 Portland OR Patty Chang-Chien Northrop Grumman Aerospace Systems

2 Acknowledgement Multi-center effort at NGAS: Microelectronics, RF Product Center, Manufacturing, Product Engineering, Materials, Antenna Product Kelly Hennig, Xiang Zeng, David Eaves, Phil Hon, Peter Chou, Gerry Mei, Roger Tsai, David Farkas, John Chen, Keang Kho, Mike Battung, Yun Chung, Pei-Lan Hsu, Jeff Yang, Wendy Lee, Matt Nishimoto, Tony Long, Greg Rowan, Sean Shih, Dah-Weih Duan, Jose Padilla, Pin-Pin Huang, Minhdao Truong, Richard To, K.K. Loi, Hui Ma, Jeremy Ou-Yang, Craig Geiger, Gershon Akerling, Chi Cheung, Sujane Wang, Jane Lee, Danny Li, Peter Nam, Peter Ngo, Martin IIyama, Ging Wang, Tom Chung, Gary Gurling, Randy Duprey, Cesar Romo, Ben Heying, Randy Sandhu, Ben Poust, Matt Parlee, Denise Leung, David Eng, Eric Kaneshiro, Rich Kono, Jansen Uyeda, Mike Barsky, Jennifer Gan, Ke Luo, Fred Dai, Edna Yamada, Mike Wojtowicz, Rich Lai, Augusto Gutierrez, Aaron Oki and many more! 2

3 Agenda Overview Technology description Benefits 2-Layer WLP/WSA Process description Examples Interconnects & Transitions Package Performance Multi-Layer WLP/WSA Process description Examples Higher Order Integration 3

4 What is Wafer-Level-Packaging? Wafer-Level Packaging (WLP) AKA: Micro Packaging AKA: Wafer-Scale Assemlby (WSA) 4 State-of-the-art MMIC Wafer Add inter-cavity interconnects and cavity ring Stack and bond multiple wafers, then dice Forms a hermetically packaged 3-D integrated circuit Enables integration of different MMIC technologies 3-D Wafer Scale Assembled IC WLP provides low cost, high volume, hermetic packaging

5 Advanced Capabilities for Next-Generation Systems Next-generation system needs performance superiority & affordability WLP performance superiority Advanced integration best semiconductor technology for the function Ultra-compact, light weight packaging size & weight savings High functional density & low loss interconnects Superior circuit performance Hermetic MMIC packaging Enhanced circuit reliability Large Aperture Phased Arrays Military Systems WLP Affordability Batch fabrication processes Low cost, high volume Fully compatible with NGAS MMIC production processes Existing & proven MMIC technologies Next-generation MMIC technologies Reduce higher order assembly cost, relax module assembly requirement 5 Satellite Comm. Restricted

6 WLP Benefits Superiority Hermetic compact MMIC packaging Performance enabler High functional density Superior circuit performance Heterogeneous Integration using WLP Affordability Batch fabrication processes, low cost, high volume Combine multiple MMIC wafers by wafer bonding technology Reduce higher order assembly cost, relax module assembly requirement Integrated Microwave Assembly (IMA) Wafer-Level- Package (WLP) Size reduction 1 1,000X Weight reduction 1 1,000X Cost reduction X Tri-layer WLP TR Module X-band operation Mass: <15mg Size: 2.5mm x 2mm x 0.46mm WLP content: 3 bit PS, LNA, PA 6 WLP offers superiority in performance and affordability in cost

7 Integrated Microwave Assembly Packaging GaAs GaN InP CMOS IMA 7

8 Wafer-Level Integration Benefits Hermetic Ultra-light weight, ultra-compact Low cost, high volume Performance enhancement IMAs Weight: g to >1000g Size: cm x cm x cm Assembly: serial, manual Package near a thumb tack Wafer-Level Integrated Package Weight: < 50 mg Size: mm x mm x mm Assembly: mass parallel, wafer scale 8

9 ) Integration Using Wafer-Level Packaging WLP is assembled using a low temperature wafer bonding process WLP technology is fully compatible with NGAS MMIC production processes a. Diagram and photograph of WLP LNA Through Via Bonding Ring (wafer 1) Low-Noise Circuit with Amplifier Wafer Bonding Ring Wafer Bonding 9 Low temperature wafer bonding process is 20 key to MMIC compatible, robust WLP b. Measured data from WLP LNA circuits 10 Circuit (low-noise amplifier) Bonding Ring (wafer 2) Bonding Ring

10 10 2-LAYER WLP

11 2-Layer WLP Wafers are individually processed prior to bonding No changes to standard MMIC processes ICIC = Intra-Cavity InterConnections 2-layer Bonding Process Flow ICIC BICIC = Backside ICIC 2-layer Bonding Process Flow Wafer 1 Wafer 2 Flip & align BICIC ICIC (Front side) BICIC (backside) Bonding Layer Wafer Bonding Bonded pair 11 2-Layer WLP is constructed by bonding 2 individually processed wafers

12 WLP Demonstrations WLP is fully compatible with NGAS s MMIC production processes Frequency bands w/ WLP X-band Ka-band Ku-band Q-band V-band W-band Different circuit types w/ WLP LNAs PAs Oscillators Phase shifters Shift registers Switches Substrate combinations w/ WLP GaAs + GaAs InP + GaAs InP + InP Quartz + Quartz Si + InP Glass + Glass GaAs + Duroid GaAs + InP + GaAs GaAs + InP + InP SiC + SiC Multiple GaAs integrations Multiple InP integrations 12 Different compound-semiconductor technologies w/ WLP InP HEMTs InP HBTs ABCS HEMT GaAs HEMTs MEMS switches GaAs HBTs Passives GaAs Schottky diodes GaN HEMTs InP diodes NGAS has extensive experience in heterogeneous integration using WLP

13 S21 (db) S21 (db) S21 (db) S21 (db) Examples of Packaged MMICs Ku Band PA, WLP GaAs HEMT circuit Ku Band LNA, WLP GaAs HEMT circuit Frequency (GHz) Q-Band WLP LNA, Q-Band WLP LNA GaAs (IRFFE) HEMT Circuit Frequency (GHz) W-Band PA, WLP GaAs HEMT circuit LNA Bonding Ring Frequency (GHz) Frequency (GHz)

14 Wafer Level Packaging (WLP) MMICs Proven across the bands 4-bit PHSH -Chip size: x=3.3mm, y=2.7mm -TTL compatible -avg RMS Amp Error=1.08dB -avg RMS Phase Error=16.5º 2-Stage, self-biased LNA -Chip size: x=3.3mm, y=2.7mm -bias: 4V, 26 ma -Gain > 26.5 db at 16 GHz 2-Stage PA -Chip size: x=3.3mm, y=2.7mm -bias: 4V, 120 ma -Gain > 19 db at 16 GHz 3-Stage, self-biased LNA -Chip size: x=4.2mm, y=4.2mm -bias: 4V, 45 ma -Gain > 24 db at 35 GHz KU KA Q 3-Stage, self-biased LNA -Chip size: x=4.2mm, y=4.2mm -bias: 4V, 60 ma -Gain > 11.8 db from GHz 14 Miniaturized WLP T/R modules for large arrays

15 GaN WLP Technology Developed world s first GaN wafer level package process for record power density Demonstrated >99% GaN WLP interconnect yield Passive Cover Wafer Active GaN Wafer GaN WLP chip Photo of GaN WLP MMIC GaN WLP TEG chip 15

16 W-Band WSA Oscillator W-Band oscillator with built-in on chip resonant cavity 2-layer active MMIC integration: InP HEMT + GaAs HBT Measured spectrum of Oscillator 1 st and 2 nd Half of Resonant Cavity Coupling Slot Through Wafer RF Transition Active Device Through Wafer RF Transition (Backside Probe Location) Photo of the integrated oscillator chip 16 Demonstrated 2-Layer WSA Oscillator

17 S21 (db) Comparison of WLP and non-wlp circuits 1.4mm 1.9mm ALH mm ALH 140V3 (WLP) ALH140 vs. ALH140V3 : Conventional ALH140 (FIDR1/A-J A-031) : ALH140V3 with WLP cover (WLP5/1/P ) ALH140_1 ALH140_2 ALH140_3 ALH140_4 ALH140_5 ALH140_6 ALH140_7 ALH140_8 ALH140_9 ALH140_10 ALH140_11 ALH140_12 ALH140_V3_1 ALH140_V3_2 ALH140_V3_3 ALH140_V3_4 ALH140_V3_5 ALH140_V3_6 ALH140_V3_7 ALH140_V3_8 ALH140_V3_9 ALH140_V3_10 ALH140_V3_11 ALH140_V3_12 3.2mm Frequency (GHz) RF performance similar for WLP and non-wlp circuits 17

18 2-LAYER INTEGRATED WLP/WSA EXAMPLES 18

19 Heterogeneous Integration Example Integrated RF front end module with antenna Amplifier (GaAs HEMT) 3 bit phase shifter (GaAs HEMT) Interconnections (ICICs) Antenna WLP bottom side Integrated RF Front-End Module WLP top side (antenna) Wafer 1 antenna Sealing Ring (Wafer 2) Wafer Bonding Wafer 2 ICIC Amplifier Sealing Ring (Wafer 1) Phase shifter Wafer 1 Ground Fence Through wafer via 19

20 Magnitude (db) Phase (deg) On-Wafer Measured Data WLP technology - Wafer1=passive, 4-mil GaAs - Wafer2=0.1um, 4-mil GaAs 2-stage balanced Amplifier 3-bit reflective phase shifter 20 Amplifier S-Parameter Phase Shifter Phase States S22 S11 S Frequency (GHz) Phase States 20

21 E-Field Magnitude (db) WLP Linear Array Demonstration Demonstrated fully functional front-end modules with a linear 4-element array GaAs HEMT + passive Amplifier + 3bit PS + antenna in an integrated Q-Band WLP package Successful integration to BFN board Demonstrated electronic beam steering Measured Beam Pattern = 0 =15 Integrated RF front-end modules w/ antenna (deg) Beam Forming Network (board) WLP bottom side WLP top side (antenna) 21

22 INTERCONNECTS & TRANSITIONS 22

23 S21 (db) RF ICICs 23 RF ICIC 50 Ohm Coaxial Transition Designed to provide minimal mismatch between 50 Ohm microstrip line (wafer 1) and 50 Ohm CPW line (wafer 2) Measured Data from RF ICIC Structure (2 RF ICIC transition + thru line) (a) (b) Wafer 2 ICIC Coaxial transition to CPW transmission line Wafer 1 Microtransmission line to ICIC Coaxial transition Frequency (GHz) Demonstrated Low Loss, RF ICICs

24 Low Loss RF Vias RF via transitions Low loss up to 50GHz <0.1dB insertion loss up to 30GHz RF Via Test Structure DC interconnects > 99% yield Calibration structures To ensure accurate measurement RF calibration and Test Structures Measured Data Simulation 24 Demonstrated Low Loss RF Vias for WLP devices

25 High Frequency RF Interconnects First-of-a-kind W-band WLP RF interconnect Insertion Loss < 0.2 db Return Loss > 20 db 20 db isolation Electro-Magnetic Simulation of Transition ~0.2 mm Input Top Wafer Bottom Wafer Output Measured Transition-Line-Transition Response Ground Vias connecting top and bottom ground planes Bottom Wafer Back-to-Back Interconnect Cross Section 25 Demonstrated Low Loss, High Isolation W-Band WLP Interconnects

26 Isolation (db) Isolation Loss (db) Isolation (db) Loss (db) Isolation Using Ground Fence Isolation fence can be built using 3D interconnects within WSA Demonstrated 30dB isolation improvement in W-band using ground fence 3D WSA offers design flexibility and performance improvement Thru-Wafer Via ICIC Isolation Fence RF Transition Line Simulated Isolation Fence Response Blue: no via fence Red: with via fence Frequency 94 (GHz) Frequency (GHz) Measured Isolation Fence Response -20 DB( S(2,1) ) DF_MS22_ISO_0_1a -30 DB( S(2,1) ) DF_MS22_ISO_1_1a Frequency (GHz) Frequency (GHz) RF Isolation Design For WSA MMIC No via fence Single via fence

27 27 PACKAGE PERFORMANCE

28 Package Mechanical and Thermal Integrity WLP chips Passed the many military standard tests: Vibration-Sine MIL-STD 883F, Method , condition B Mechanical Shock (Pyroshock) MIL-STD 883F, Method , condition B Die Shear MIL-STD 883F, method Temperature Cycling MIL-STD 883F, Method , condition B -55ºC to 125ºC, 50 cycles, MEMS -55ºC to 85ºC, 300+ cycles, W-Band GaAs circuits -55ºC to 125ºC, 500 cycles, GaAs PA Hermeticity MIL-STD 883F, Method He fine leak, condition A2, flexible Radioisotope fine leak, condition B Penetrate dye gross leak, condition D Mechanical Robustness Seal Robustness Thermal Robustness Environmental test: 85C 85% humidity 7 days Ku band GaAs MMICs 28 WLP packages are hermetic, thermally and mechanically robust

29 S21 (db) S11 (db) Thermal Robustness 24 to 40 GHz GaAs HEMT LNA Thermal cycling, -55 C to 125 C 500+ cycles Photo of WLP GaAs LNA Measured s21 response as function of thermal cycles R6C6M Frequency (GHz) (GHz) Post_500 Cycles Post_300 Cycles Post_100 Cycles Post_10 Cycles Pre_Cycle

30 30 MULTI-LAYER WLP/WSA

31 Advanced Integration: Multiple Layer WLP Example: 4-layer construction Use bonded pair as starting units 4-layer Bonding Process Flow Bonded Pair 1 Bonded Pair 2 Multiple Layer WSA Flow Bonded Pair 1 Bonded Pair 2 or single wafer Process Bonding layer if necessary (backside) ICIC (Front side) BICIC (backside) Bonding Layer Wafer Bonding 31 4-Layer Construction is Achieved By Bonding 2 bonded WLP pairs

32 X-Band Tri-Layer Tx/Rx Modules WLP Tx/Rx Module ABCS HEMT LNA Average mass: 12.9mg Size: 2.5mm x 2mm x 0.46mm Next-Generation Large Aperture Array T/R Module Ultra light weight (<15 mg) Extremely compact (<5 mm 2 ) Transceiver Module Performance FOM > 10,000 Reliability: MTTF >10 6 Hours ABCS HEMT Power Amplifier Shift Register InP HBT Phase SwitchShifter GaAs HEMT Low Noise Amplifier Switch InP HBT PA & digital control GaAs HEMT PS & Switches 32 Demonstrated X-Band Integrated T/R Module

33 Tri-Layer T/R Demo Tri-layer T/R module demonstration GaAs HEMT + InP HBT + InP HEMT Demonstrated excellent yield and T/R circuit performance Measured NF (Rx) of the tri-layer WLP T/R module 33

34 Measured Angle (Deg) Measured Angle (Deg) CMOS + III-V Integration Demo WLP 8-bit VAP 5-mil solder ball 8-bit shift register 8-bit CMOS Shift Register WLP 8-bit VAP Input Digital CTRL Waveform Measured Phase Ideal Shifter Measured Data CLK Ideal Measured 135 ENB Data Set Angle (Deg) Demonstrated heterogeneously integrated CMOS flip-chip to WLP MMICs

35 35 HIGHER ORDER ASSEMBLY

36 WLP Higher Order Integration Demonstrations Fixture Alumina Organic Board Assembly Technologies integrated GaAs-GaAs GaAs-InP InP-InP ABCS-InP-GaAs Techniques demonstrated Epoxy to Fixture/Board Bump to Board Manual Auto assembly Demonstrations CMOS to III/V Integration Direct WLP to Board Attach 16-element Ku-band Rx Array 8-element Ku-band Rx Sub- Array 4-element Q-band Tx Array Benefit SWaP reduction SWaP, cost reduction Near term insertion Design to manufacturing mmw array implementation 36 Demonstrated WLP-to-Board Integration

37 Microbump: Chip-Board Integration Developed microbump technologies for WLP to-board attachment and integration Cu stud microbump Microbumps on backside of the package Sn/Pb microbump array 37 Microbumps enable direct WLP-to-Board Integration

38 Direct Board Attach Using Microbumps chip board Cu studs X-ray result showing good board to chip interface 38 Excellent Chip-to-Board Microbump Interface

39 Example of Epoxy Attach and Ribbon Bonds Implementation Normalized Amplitude Ku Band subarray board with WLP chips Integrated Subarray Antenna Board Measured Far Field Pattern 5 WLP MMIC fixture for environmental testing Azimuth ( ) 39 WLPs are compatible with epoxy attachment

40 WLP on Interposer Boards on PWB Front Side: WLP on Interposer Back Side (Solder Ball) WLP on Interposer WLP Interposer board attachment to PWB 40

41 Higher Order Integration Using WLP/WSA Demonstrated thermal cycling robustness of WLP-board assembly with underfill >200 cycles from -40C to 100C Pass without failure Successfully demonstrated dual side WLP chip-to-board attachment Dual-Sided Assembly WLP chips Dual sided board WLP chips 5mil Solder Balls 2-layer WLP chip WLP cavity 5mil solder balls underfill PWB Chips on the front side of PWB after backside assembly Chips on the backside of PWB 41

42 Summary WLP technology offers performance superiority and affordability for next-generation systems WLP offers significant size, weight and cost savings for future systems Demonstrated multiple advanced technology integration with WLP Verified robustness of WLP packaging by MIL-STD tests Demonstrated WLP integrated MMICs & modules across the bands NGAS is committed to mature and improve wafer-scale integration technology for system insertion 42

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