INF4420 Lecture Notes

Transcription

1 INF4420 Lecture Notes Jørgen Andreas Michaelsen Spring 2012

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3 INF4420 Introduction Spring / 32 Outline Practical information about the course. Context (placing what we will learn in a larger context) Outline of the curriculum. 2 / 32 INF4420 Spring 2012 Introduction

4 Lectures Jørgen Andreas Michaelsen Room: 5405, Phone: Lectures on mondays in OJD 2453, Perl 3 / 32 Problem solving class Kin Keung Lee (Kody) Room: 5122, Phone: kklee@ifi.uio.no Assignments for each week (not mandatory) Fridays in OJD 2465, Prolog 4 / 32 INF4420 Spring 2012 Introduction

5 Labs Weekly labs to learn design tools Details are not yet available... 5 / 32 Webpage Course webpage: important mesages will be posted on the course webpage. Slides for the lectures and assigments for the problem solving class are posted. 6 / 32 INF4420 Spring 2012 Introduction

6 Teaching and examination Lectures (2-3 hours) Problem solving class (2 hours) Lab exercises (2 hours) 4 hour written exam (60 %) Project (design, layout, 40 %) 7 / 32 Course content From the course webpage: "The course provides the know-how and skills needed to design analogue and mixed-signal integrated circuit modules using modern program tools. The main focus of the course is complex systems such as data converters (A/D, D/A) and phase-locked loops (PLL). An introduction is given to CMOS technology and methods in order to implement passive components such as transistors, condensers and coils. In addition, matching, optimisation and noise deflection are all key aspects. The execution of project tasks will be a central part of the teaching." 8 / 32 INF4420 Spring 2012 Introduction

7 Learning outcomes From the course webpage: "Students will have the skills needed to design an integrated mixed-signal circuit in CMOS using modern design tools." 9 / 32 Student reference group 1 or 2 students 10 / 32 INF4420 Spring 2012 Introduction

8 What is expected of you? Basic understanding of analog CMOS (INF3410). We will build on this for most of the circuits and systems we discuss. Linear circuits (transfer functions, Laplace). Important to ask questions. 11 / 32 Integrated circuits Integrated circuits are found everywhere in our daily lives. Cost is a driver. Reduced feature size, smaller dies, CPF decreases, more features on the same die (SoC). Larger wafers. Reduced feature size also helps performance. Is scaling good for analog? 12 / 32 INF4420 Spring 2012 Introduction

9 Mixed-signal in DSM Digital content dominate. Process development is geared towards reducing cost-per-function (CPF). Analog and RF functions have to keep up (cost benefits of placing all functions on one die) 13 / 32 Mixed-signal circuits What are mixed-signal circuits? Analog + Digital? Time/Value Discrete Continuous Discrete Digital? Continuous? Analog 14 / 32 INF4420 Spring 2012 Introduction

10 Why mixed-signal circuits? Digital circuits are more robust and can be designed more systematically. Usually, most of the system and signal processing will be digital content. We need circuits for regulating supply voltage, clocking digital circuits, interfacing with the (analog) world (filtering and converting to/from digital), communication circuits. 15 / 32 Uses of mixed-signal Analog and mixed-signal circuits are prevalent even in "digital" systems clocking and timing circuits digital i/o (high speed bus) supply voltage regulation wireless communication sensor interfacing / 32 INF4420 Spring 2012 Introduction

11 Mixed-signal in DSM New ideas and different designs are needed to keep up with new process technology, and new trends (e.g. portable applications). Important to have a good understanding of analog and mixed-signal circuits. Know what the limitations are and what can be improved. DALLAS, Aug. 23 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced a dual-channel, single-lane serial-ata (SATA) redriver and signal conditioner, featuring the lowest active power and lowest automatic low-power (ALP) mode of any 6-Gbps redriver/equalizers available today. The SN75LVCP601 has a maximum active power consumption of 290 mw, or approximately 50 percent less than the nearest competitor, extending critical battery life in portable electronics, such as notebook PCs / 32 Design flow Top-down design Specification + different levels of abstraction Meeting specs accross PVT with min power Usually, big savings are in the architecture 18 / 32 INF4420 Spring 2012 Introduction

12 Levels of abstraction System level (block diagrams, MATLAB) Schematics (SPICE) Layout (CAD, DRC, ERC, LVS) 19 / 32 Curriculum 20 / 32 INF4420 Spring 2012 Introduction

13 Reference circuits Every analog and mixed signal circuit needs biasing and/or a reference independent of PVT. 21 / 32 Layout and mismatch Drawing layout needs careful attention in order to get predictable results. Ensuring drawn layout is manufactureable (DRC). Ensuring drawn layout is coherent with schematics (LVS, post layout simulation, but this does not reveal every problem, assumptions made by schematics) Ensuring drawn layout is robust against manufacturing imperfections. 22 / 32 INF4420 Spring 2012 Introduction

14 Switched capacitor Very important technique for analog signal processing. Discrete time, continuous value. 23 / 32 Data converters Converting between analog and digital representations of the signal. General data converter considerations Different architectures suited to different specifications (speed, resolution). Oversampling and noise shaping 24 / 32 INF4420 Spring 2012 Introduction

15 Oscillators and PLLs Clock and data recovery (from serial data) Clock generation (from external crystal reference) Demodulation (e.g. frequency modulated signals) 25 / 32 Project Counts 40 % towards the final grade Final report is very important Last year: SAR ADC This year: Bandgap + Current steering DAC Work in groups of two Kody will follow up on the project More details to follow 26 / 32 INF4420 Spring 2012 Introduction

16 Design tools Hands on with high quality IC design tools in the labs and for completing the project. Virtuoso IC6.1.4 (Cadence) Virtuoso Spectre (Cadence) Calibre (Mentor Graphics) 27 / 32 Process design kit (PDK) TSMC 90 nm MS/RF LP 1.2 V with 2.5 V I/O Provides simulation models PCells for generating component layout Rule decks for DRC, ERC, and LVS 28 / 32 INF4420 Spring 2012 Introduction

17 Final exam 7. June, 14:30, 4 hours written exam Counts 60 % towards the final grade. 29 / 32 Schedule 30 / 32 INF4420 Spring 2012 Introduction

18 References In addition to the curriculum, these references have been consulted when preparing the lectures. CMOS: Circuit design, Layout, and Simulation (Baker, IEEE Press). Analog Design Essentials (Willy Sansen, Springer). IDESA ( Analog Integrated Circuit Design (Johns and Martin, Wiley). 31 / 32 Next lecture 23. January Reference circuits ("Bandgaps") 32 / 32 INF4420 Spring 2012 Introduction

19 INF4420 Reference circuits Spring / 47 Outline Reference circuits and bias circuits Uses of reference circuits and bias cicuits MOSFET based references Parasitic diode based references (bandgaps) 2 / 47 INF4420 Spring 2012 Reference circuits

20 Reference circuits "Bandgaps". Why? Every analog and mixed-signal system needs a stable reference. The reference circuit presents some physical quantity (voltage, current, frequency, other?) Image courtesy of Texas Instruments 3 / 47 Biasing an analog circuit Analog circuits need a current source to set the operating point. Circuit performance very dependent on the biasing. 4 / 47 INF4420 Spring 2012 Reference circuits

21 Data converters Binary word input is dimensionless. Need to multiply the dimensionless input with a dimensioned (physical) reference. 5 / 47 Voltage supply regulation 6 / 47 INF4420 Spring 2012 Reference circuits

22 Temperature behaviour Predictable behaviour across temperature Constant Proportional (PTAT) Additionally, insensitive to supply voltage and process variations (PVT). 7 / 47 A very simple reference Careful layout gives good matching between resistors Temperature affects resistors equally, good TC Precisely defined Vref as ratio of Vdd Precise value of Vdd is not known (bad) Poor PSRR! (bad) 8 / 47 INF4420 Spring 2012 Reference circuits

23 MOSFET-R reference Can be used to generate a bias voltage or reference voltage. Better PSRR than the voltage divider. 9 / 47 MOSFET-R reference 10 / 47 INF4420 Spring 2012 Reference circuits

24 MOSFET-R reference 11 / 47 Beta multiplier reference Deriving Iref from Iout Less dependence on Vdd Can be used for biasing and reference 12 / 47 INF4420 Spring 2012 Reference circuits

25 Beta multiplier reference 13 / 47 Beta multiplier reference 14 / 47 INF4420 Spring 2012 Reference circuits

26 Beta multiplier reference As a voltage reference, take Vgs1 to be the reference voltage, Vref. We know the current, Iref. Use this to find Vgs1=Vref We must find the sensitivity of Vref to Vdd and T 15 / 47 Beta multiplier reference 16 / 47 INF4420 Spring 2012 Reference circuits

27 Bandgaps It turns out, we can make references with less temperature dependence using bipolar transistors. 17 / 47 Temperature independence 18 / 47 INF4420 Spring 2012 Reference circuits

28 Parasitic diode CTAT and PTAT Need elements with well defined temperature behaviour. We will use diode connected BJTs. CTAT from Vbe (biased with constant current) PTAT from "delta Vbe" (biased with ratioed current or emitter area), result is the thermal voltage, Vt 19 / 47 Bipolar transistor diodes Current sinked by the device is affected by temperature Vt is the thermal voltage (proportional to T), 26 RT Is is also a function of termperature 20 / 47 INF4420 Spring 2012 Reference circuits

29 PTAT voltage 21 / 47 PTAT voltage To find temperature behaviour, we take the derivative wrt. temperature (assume the first derivative is constant) Delta Vbe is proportional to absolute temperature. Defined by two physical constants and emitter ratio, n. 22 / 47 INF4420 Spring 2012 Reference circuits

30 PTAT voltage 23 / 47 CTAT voltage For the full bandgap circuit, we need both PTAT and CTAT. Is exhibits temperature dependence. In the delta Vbe, Is is canceled. By looking at a single junction Vbe, we get a contribution from Is. dvbe/dt assuming constant current Ic. In this case, the overall TC is CTAT. 24 / 47 INF4420 Spring 2012 Reference circuits

31 CTAT voltage 25 / 47 CTAT voltage Silicon bandgap energy as a function of temperature 26 / 47 INF4420 Spring 2012 Reference circuits

32 CTAT voltage 27 / 47 Bandgap circuits We know how to generate PTAT and CTAT, and how we should combine these contributions for temperature independence (I. e. scale and add to acheive temperature independence). How do we make a circuit that realizes this system? 28 / 47 INF4420 Spring 2012 Reference circuits

33 Bandgap circuits 29 / 47 Bandgap circuits Need a circuit that can sense V1 and V2 and adjust the current sources so that V1=V2 V2 = Vbe2 + Vt ln n ln n must be 17.2 for V2 to be independent of T 30 / 47 INF4420 Spring 2012 Reference circuits

34 Bandgap circuits 31 / 47 Bandgap circuits 32 / 47 INF4420 Spring 2012 Reference circuits

35 Bandgap circuits This circuit is used for illustration purposes. Working with CMOS, there are a number of issues with this circuit which we will discuss in the following slides. We will try to find circuits which are more practical and CMOS compatible. 33 / 47 A more CMOS friendly BJT Instead of the diode connected npn that we have used so far, we will use a pnp. This is so that we can implement the device in a CMOS process without any special processing. 34 / 47 INF4420 Spring 2012 Reference circuits

36 BJT in a CMOS process 35 / 47 CMOS bandgap 36 / 47 INF4420 Spring 2012 Reference circuits

37 CMOS bandgap 37 / 47 Low-voltage bandgap 38 / 47 INF4420 Spring 2012 Reference circuits

38 Low-voltage bandgap The core circuit is (again) the PTAT current generator. Although the delta Vbe gives rise to a PTAT voltage (dropped accross R1), the absolute Vbe of Q1 and Q2 is CTAT. Vbe1 controls the current through R2 and R3. The result is a temperature independent current if the currents are scaled correctly. 39 / 47 Low-voltage bandgap 40 / 47 INF4420 Spring 2012 Reference circuits

39 41 / 47 Stability Stability is a concern for any system with feedback. Must make sure that we have more negative feedback than positive. 42 / 47 INF4420 Spring 2012 Reference circuits

40 Transient response Transients may capacitively couple to circuit nodes. Faster opamp Decoupling (opamp stability) 43 / 47 Startup circuit In the discussion so far, we have assumed the circuits are at the desireable operating point. We must add circuitry to make sure the circuit is not stuck at a "zero" operating point. Typically a circuit to inject some current if we are at or close to the undesireable operating point. (Power on reset.) This is very important. Simulator does not neccessarily reveal this problem. 44 / 47 INF4420 Spring 2012 Reference circuits

41 Curvature correction In our analysis we have asumed the PTAT and CTAT to be constant. This assumption will lead to a non-linearity of the TC (curvature), approximately parabolic shape. Possible to design some function to try to mitigate this effect. Even possible to use Vos constructively (Cabrini, ESSCIRC 2005). Not curriculum. 45 / 47 Bandgap circuit issues Collector current variation CMOS compatibility (BJTs) Opamp offset voltage Opamp resistive loading Stability Startup Transient response PSRR Curvature Limited supply voltage Noise Resistor TC 46 / 47 INF4420 Spring 2012 Reference circuits

42 Online resources This is not part of the curriculum org/details/apaulbro198 9 A Paul Brokaw 47 / 47 INF4420 Spring 2012 Reference circuits

43 INF4420 Layout and CMOS processing technology Spring / 76 Outline CMOS Fabrication overview Design rules Layout of passive and active componets Packaging 2 / 76 INF4420 Spring 2012 Layout and CMOS technology

44 Introduction As circuit designers we must carefully consider how to draw layout for critical/sensitive parts of the circuit in order to get robust and predictable performance. To be sucessfull at this, we must have a basic understanding of how circuits are manufactured, packaged, tested, and even how the circuit eventually is used on a PCB (e.g. external parasitics that we need to drive off chip). 3 / 76 Physical design The physical circuit is built on a disc of silicon (wafer) layer by layer. Some layers are implanted in the substrate, other layers are stacked on top. 4 / 76 INF4420 Spring 2012 Layout and CMOS technology

45 Physical design How do we go from a layout (GDS2) to a physical circuit? For each step in the processing, we must get the relevant part of the design onto the wafer, do the processing (implant, etch, or grow), and ready the wafer for the next step. 5 / 76 Physical design Layout is "encoding" the physical realization of circuits. CMOS processing (manufacturing) is done in layers, so is layout. 6 / 76 INF4420 Spring 2012 Layout and CMOS technology

46 Photolithography Photolithography (litho) is used to define regions for each layer. For each processing step, we need to transfer the mask onto the wafer (selectively coat/shield part of the wafer). Light source and a mask defines patterns on photoresist. Photoresist hardens when exposed to light. 7 / 76 Lithography system We create layout. The mask (or reticle) used for photolithography is derived from the layout. 8 / 76 INF4420 Spring 2012 Layout and CMOS technology

47 Photoresist (1) Photoresist hardens when exposed to light (negative photoresist), leaving a developed mask on the wafer. Remaining photoresist is removed. (2) Do processing. (3) After processing step, hardened resist is also removed. Repeat for all processing steps required for full circuit. 9 / 76 Diffraction Slits in the reticle cause diffraction (pattern spreads out). Wavelength of light is a limitation for feature size. Images illustrating diffraction from Wikipedia. org. 10 / 76 INF4420 Spring 2012 Layout and CMOS technology

48 Resolution Resolution is limited by the wavelength of light and numerical aperture (NA) of the lens (angle of light captured by the lens, and refractive index n). 11 / 76 Depth of focus As the wafer is built layer by layer, geometry becomes uneven. Wavelength of light and NA will limit the allowed topology difference. Planarize wafer between processing steps (before imaging) with chemical mechanical polishing (CMP). Unfortunately, inherent tradeoff between DOF and resolution (better NA, finer pitch, more narrow DOF). 12 / 76 INF4420 Spring 2012 Layout and CMOS technology

49 Reducing k1 Optical proximity correction (OPC), sub resolution assist features (SRAF). Modelling the lithography as a non-linear low-pass 2D spatial filter, try to come up with an inverse. 13 / 76 Reducing k1 Phase shifting masks (PSM) Instead of "binary" on/off masks, masks alter the phase of the light. Double patterning Split layout accross two (or more) masks Off-axis illumination Optimizing the shape of the light source 14 / 76 INF4420 Spring 2012 Layout and CMOS technology

50 Reducing k1 Result: k1=0.25 instead of k1=0.5 Restricting allowed pitch may be neccessary for pattern fidelity. Additionally, NA is improved through immersion lithography (water between lens and wafer, higher refractive index, n). 15 / 76 Extreme UV source 20 nm process with 193 nm light source? It can be done without defying the laws of physics! Why not use 13.5 nm (EUV) instead? / 76 INF4420 Spring 2012 Layout and CMOS technology

51 Front end of line (FEOL) Process modules that form the active devices Active area Channel doping Gate Source/drain extension Spacer Junction Silicide 17 / 76 Active area definition Shallow trench isoloation (STI) Insulation between active devices Etch trenches in the substrate Filled with SiO2 18 / 76 INF4420 Spring 2012 Layout and CMOS technology

52 Channel doping Define p- and n-type regions for NMOS and PMOS 19 / 76 Gate electrode Gates made of polysilicon 20 / 76 INF4420 Spring 2012 Layout and CMOS technology

53 Source/drain extension Mitigate short-channel effects source/drain resistance leakage current, drive current 21 / 76 Spacers Avoid bridging S/D and gate due to silicide Offset junctions (next step) 22 / 76 INF4420 Spring 2012 Layout and CMOS technology

54 Junctions Source and drain junctions Implant arsenic/phosphore (n-type) or boron (p-type) 23 / 76 Silicide Lower resistance, better Ion. Avoid current crowding. Self aligned silicide = salicide 24 / 76 INF4420 Spring 2012 Layout and CMOS technology

55 Back end of line (BEOL) Back end of line adds connection between devices, contacts and metal layers with vias between layers Parasitic resistance and capacitance is challenging for scaled technology. In modern CMOS, copper (Cu) metallization and low k dielectric is used. 25 / 76 BEOL modules Pre Metal Dielectric (PMD) Contacts to source, drain, and gate (tungsten) Inter Level Dielectric (ILD) Vias and metal lines (copper) 26 / 76 INF4420 Spring 2012 Layout and CMOS technology

56 Dual Damascene Metallization used to be etching away aluminum. Impossible with copper. Instead: Damascene. Used throughout the BEOL. Image: wikipedia.org (1) Etch trenches in oxide, (2) deposit copper, (3) polish away the overfill (CMP) 27 / 76 Dual Damascene 1. Trenches are etched in the oxide (to the barrier) 2. Metal (Cu) is deposited through electroplating (leaving excess Cu) 3. CMP to remove excess metal. Dual = via and metal formed simultaneously INF4420 Spring 2012 Layout and CMOS technology 28 / 76

57 Dual Damascene Why should we as designers care? CMP polish rate is pattern dependent, i.e width and spacing of metal lines matter. Poor layout results in metal lines that are too thin and/or less dielectric separation of metal layers. Layout dependent delay. Post-layout simulation does not neccessarily reveal these problems. 29 / 76 Dishing and erosion Dishing affecting wide metal lines (Cu polishes faster than dielectric) Erosion affecting high density metal pattern 30 / 76 INF4420 Spring 2012 Layout and CMOS technology

58 Drawing layout Layout is drawing the masks used in the manufacturing process. As we have seen, the layout we draw is not perfectly reproduced on the wafer. We must comply with a set of rules to ensure that the layout we draw is manufacturable. 31 / 76 Design rule examples Rule name (minimum) P.1 Poly width P.2 Space poly and active P.3 Poly ext. beyond active P.4 Enc. active around gate P.5 Spc. field poly to active P.6 Spc. field poly 32 / 76 INF4420 Spring 2012 Layout and CMOS technology

59 Design rule examples Poly rules example (FreePDK45) Rule name (minimum) Length P.1 Poly width 50 nm P.2 Space poly and active 140 nm P.3 Poly extension beyond active 55 nm P.4 Enclosure active around gate 70 nm P.5 Space field poly to active 50 nm P.6 Space field poly 75 nm 33 / 76 Design rule examples Metal1 rules example (FreePDK45) Rule name (minimum) Length M1.1 Metal1 width 65 nm M1.2 Space metal1 65 nm M1.3 Enclosure around contact (two opposite sides) 35 nm M1.4 Enclosure around via1 on two opposite sides 35 nm M1.5 Space metal1 wider than 90 nm and longer than 900 nm 90 nm M1.6 Space metal1 wider than 270 nm and longer than 300 nm 270 nm M1.7 Space metal1 wider than 500 nm and longer than 1.8 um 500nm / 76 INF4420 Spring 2012 Layout and CMOS technology

60 Density design rules In addition to spacing and area rules. There are density rules. Ref. dishing and erosion resulting from CMP. Typically, the layout will undergo dummy fill to comply with density rules (automatic). Neccessary for manufacturability, but increases capacitance. 35 / 76 Antenna design rules Large area metal connected to a MOSFET gate can collect ions during manufacturing and irreversibly break down gate oxide. 36 / 76 INF4420 Spring 2012 Layout and CMOS technology

61 Design rule switches Different set of rules can be invoked for different parts of the circuit. E.g. Minimum rules for high density generic digital circuitry Analog or DFM rules for sensitive circuits. 37 / 76 Design Rule Check, DRC Design Rule Check (DRC) Large number of rules to comply with. Difficult to keep track of. Automated by design tools with foundry rule set. Used to be pass/fail, more recently reporting level of severity. Some rules can be waived. 38 / 76 INF4420 Spring 2012 Layout and CMOS technology

62 Litho friendly design, LFD Design rules does not guarantee a robust design or good yield. Possible to simulate and analyze how the layout will print on the wafer. Difficult to get access to data. Non-linear 2D spatial filter. 39 / 76 Lithography simulation Litho simulation using FreePDK45 and Calibre ( 40 / 76 INF4420 Spring 2012 Layout and CMOS technology

63 Lithography simulation Litho simulation using FreePDK45 and Calibre ( 41 / 76 Layout vs. schematics, LVS Recognizing shapes in the layout (transistors and passive devices), and how they are connected. Comparing layout netlist to schematics. 42 / 76 INF4420 Spring 2012 Layout and CMOS technology

64 Post layout simulation Extracts layout dependent parasitics (capacitance and resistance), and some layout dependent transistor parameters (e.g. LOD which we will discuss in the short-channel lecture). More accurate simulation results (but does not include all effects). Also, parasitics have fast/slow corners, temperature dependence. Results in slow simulation due to large netlists. 43 / 76 Interconnect Drawing metal "wires" in the layout is not like wires in the schematic. Must think about resistance, capacitance, and inductance. (E.g. 0.1 Ω/ for metal, and 10 Ω for via) Crosstalk and ground bounce. Decoupling. 44 / 76 INF4420 Spring 2012 Layout and CMOS technology

65 Interconnect Single via approximately 10 Ω. Worse, single via failure. Not only resistance, but limitaions on current capability (electromigration). Process documentation should list actual values for a given process. 45 / 76 Interconnect Overlap capacitance low-k dielectric helps reduce interconnect capacitance Additionally, fringe capacitance also important. 46 / 76 INF4420 Spring 2012 Layout and CMOS technology

66 Interconnect Sizing metal lines is a tradeoff between capcitance vs resistance (and current handling capability). Wide lines, fewer squares, less resistance, but potentially more overlap capacitance. Finally, to make it even more complicated, resistance and capacitance will vary due to dishing and erosion. 47 / 76 Passive components Mixed signal and analog require passive components (resistors, capacitors). RF needs inductors. Why not use parasitic resistance and capacitance? Possible in some cases. 48 / 76 INF4420 Spring 2012 Layout and CMOS technology

67 Resistors Several possibilities. Need to consider: Ω/ (area, practical limit for large R) Temperature dependence (TC) Voltage dependence (linearity) Mismatch (ΔR/R, abs value +/- 20 %) Parasitic capacitance The TC and voltage dependence is not only linear, but also quadratic in the simulator. E.g. R(T) = R(T0) [1 + TC1(T-T0) + TC2(T-T0)^2]. Similar for voltage dependency. 49 / 76 Resistors Realistic alternatives for large resistors: N-well: Large R, poor TC (> 2000 ppm/c), poor linearity (< 1 %), low mismatch, parasitic capacitance from pn-depletion. Always available. Poly with silicide block: Large R, good TC (~ 100 ppm/c), reasonable linearity (< 0.1 %), low mismatch. Extra layer needed. 50 / 76 INF4420 Spring 2012 Layout and CMOS technology

68 Capacitors Need to consider: F/m^2 Temperature dependence (TC) Voltage dependence (linearity) Mismatch (ΔR/R) Cost 51 / 76 Capacitors MOSCAP, using a mosfet as a capacitor (Cox). High capacitance per area, very non-linear, good e.g. for decoupling, but gate leakage current is problematic. PiP, using two poly layers. Usually not available in modern CMOS processes. 52 / 76 INF4420 Spring 2012 Layout and CMOS technology

69 Capacitors MiM (Metal-insulator-Metal). Requires extra mask. ~ 1 or few ff/um^2. Good option if available. Thin separation of metal layers and special dielectric. Usually available in RF process flavours. Cost issue. MoM (Metal-oxide-Metal). Exploit fine pitch in CMOS. No extra processing required. 53 / 76 MoM Capactiors 54 / 76 INF4420 Spring 2012 Layout and CMOS technology

70 Matching passives Systematic vs. random Different absolute values between runs Layout dependent problems Stress, thermal, or doping gradients Good layout practice helps Unit elements Dummies (each unit element should see the exact same surroundings) Interdigitation or common centroid 55 / 76 Unit elements Instead, make identical unit elements. Less systematic mismatch. 56 / 76 INF4420 Spring 2012 Layout and CMOS technology

71 Dummy elements Dummies to make sure matching elements see the same surroundings 57 / 76 Interdigitated layout Process gradient are spread more evenly between the two elements. Proximity helps with matching! 58 / 76 INF4420 Spring 2012 Layout and CMOS technology

72 Common centroid Better process gradient cancelation than interdigitated layout. Perfect cancelation of linear gradients. 59 / 76 Drawing transistors Unit elements, dummy, and common centroid also applies to layout of transistors. However, there are additional issues that need attention when laying out transistors. Multi-finger devices S/D symmetry WPE and LOD Latch-up 60 / 76 INF4420 Spring 2012 Layout and CMOS technology

73 Multi-finger devices 61 / 76 Device orientation Devices with different orientation do not match! 62 / 76 INF4420 Spring 2012 Layout and CMOS technology

74 Source/drain asymmetry Source and drain may not be symmetric due to ion implantation angle, neccessary to avoid implant depth issues (channeling). 63 / 76 Well proximity effect High energy ion implants to form the well. Scattering from the edge of the photoresist mask, and embedding in the silicon surface (near well edge). Transistors close to the well edge will therefore have different properties. This is known as the well proximity effect (WPE). Important for matching. 64 / 76 INF4420 Spring 2012 Layout and CMOS technology

75 Well proximity effect As with S/D, implantation angle may render the scattering and doping asymmetric 65 / 76 STI stress (LOD) Shallow trench isolation strains the active area of the transistor. Influcences mobility and threshold voltage (stress induced enhancement or suppression of dopant diffusion). Distance between gate and STI impacts perfomance. Important for matching. (Parameters SA and SB in BSIM). Also known as LOD (length of diffusion), LOD = SA + SB + L 66 / 76 INF4420 Spring 2012 Layout and CMOS technology

76 STI stress (LOD) 67 / 76 Transistor interconnect Unbalanced metal routing will cause the transistors to see different source voltage. Also, distribute reference as current, not bias voltage. 68 / 76 INF4420 Spring 2012 Layout and CMOS technology

77 Matching This discussion about matching was about minimizing systematic mismatch. We will discuss random mismatch later. 69 / 76 Shielding Substrate ties circuits together. Digital switching couples to the substrate. Guard rings around the circuit: Substrate ties and n-well (preferably deep n-well) Separate Vdd for digital and analog Fully differential signals See sect in Razavi's book. 70 / 76 INF4420 Spring 2012 Layout and CMOS technology

78 Latch-up As we saw with bandgap references. Parasitic BJTs are readily available in CMOS. Parasitic BJTs may inadvertently turn on due to a large injection of current into the substrate. Typical design rules make sure that substrate and n-well contacts have sufficiently small spacing. However, latchup is an important problem, and requires careful consideration. 71 / 76 Bond pads Used for connecting bond wires between die and package. Mechanical stability ESD protection (very important, and adds C) Aluminum (while other metal is Cu) Pad frame usually contains supply nets (also used by ESD circuitry) 72 / 76 INF4420 Spring 2012 Layout and CMOS technology

79 Bond pads Bonding gone wrong / 76 Seal ring A seal ring is a structure to enclose the die (outside the pad frame). Protects the die from moisture and sawing. Also contains scribe (where to saw the die). 74 / 76 INF4420 Spring 2012 Layout and CMOS technology

80 Packaging Packaging adds very significant parasitics. Bond wires introduce inductance. Rule of thumb is 1 nh/mm. Inductors like to keep current constant. Voltage will change to make this happen. Important to balance with decoupling capacitors. However, transients will remain. 75 / 76 References Hastings, The Art of Analog Layout, Prentice Hall, 2001 Orshansky, et al., Design for Manufacturability and Statistical Design, Springer, 2008 Wong, et al., Nano-CMOS Circuit and Physical Design, Wiley, / 76 INF4420 Spring 2012 Layout and CMOS technology

81 INF4420 Short-channel effects and models Spring / 32 Outline MOSFET scaling Short-channel effects MOSFET models 2 / 32 INF4420 Spring 2012 Short-channel effects and models

82 Introduction Scaling continues for the benefit of digital. For analog this is not neccessarily beneficial, but desirable to have everything on one die (SoC). Designing ananlog and mixed-signal circuits, we need to be aware of the implications so that we can design circuits that perform well despite short-channel effects. 3 / 32 Why CMOS scaling? Reducing feature size is very attractive for digital circuits Higher density (lower cost) Reduced power consumption Faster (less capacitance) 4 / 32 INF4420 Spring 2012 Short-channel effects and models

83 Why CMOS scaling? Can be beneficial for analog, depending on the application Reduced Vdd, increased current Gain is low because because output resistance is decreased Higher speed (ft) opens up for new applications in CMOS (e.g. mm-wave) 5 / 32 Short- vs long-channel A loose definition: Typically, a long-channel device will behave according to the square-law model The behaviour of a short-channel device will not be accurately predicted by the square-law model 6 / 32 INF4420 Spring 2012 Short-channel effects and models

84 Long-channel transistor Gate has good control over channel Square-law equations are sufficiently accurate for predicting drain current. 7 / 32 Short-channel transistor Drain region has more influence on channel behaviour Short-channel effects become significant. 8 / 32 INF4420 Spring 2012 Short-channel effects and models

85 Constant field scaling Constant field 9 / 32 Constant field scaling P=F*C*Vdd^2 Similar for SD depletion capacitance 10 / 32 INF4420 Spring 2012 Short-channel effects and models

86 Constant field scaling Implications for analog. gm and ro does not change. However, kt/c is the noise floor. Lower Vdd requires larger C to maintain SNR. Larger current needed to drive C. 11 / 32 Constant voltage scaling 12 / 32 INF4420 Spring 2012 Short-channel effects and models

87 Practical scaling Practical issues makes scaling less than ideal tox scaling leads to reliability concerns and gate current tunneling. Practical limit to reducing Vdd and Vth, and Vdd/Vth-ratio decreases Devices must handle higher fields 13 / 32 Charge sharing 14 / 32 INF4420 Spring 2012 Short-channel effects and models

88 HALO implants Used to make threshold voltage more constant vs. gate length. Non-uniform channel doping. Reverse short channel effect (RSCE). Overcompensating droop in threshold voltage results in increasing threshold voltage with shorter gate lengths. Trade-off Ion/Ioff (digital) vs. gain (analog). Halo reduces Ro. DITS (Drain-Induced Threshold Shift) 15 / 32 Vertical field Higher gate channel field pulls carriers closer to the oxide interface. Degrades effective mobility. Effective mobility becomes a function of Vgs (mobility reduces with increasing Vgs) 16 / 32 INF4420 Spring 2012 Short-channel effects and models

89 Velocity saturation Increasing Vds will increase the electric field in the channel. If field is too large, velocity will saturate (vsat = 10^7 cm/s). 17 / 32 Channel length modulation Channel length modulation (CLM) is present even in long-channel transistors, but less prominent. Pinch-off changes with Vds. 18 / 32 INF4420 Spring 2012 Short-channel effects and models

90 DIBL Drain induced barrier lowering Drain voltage (Vd) contributes to inverting the channel, effecively reducing Vth. Increasing current with increasing Vd 19 / 32 Hot carriers Velocity overshoot due to high electric field from source to drain. Impact ionization near drain, electron hole pair. Carriers may get trapped in the gate oxide. 20 / 32 INF4420 Spring 2012 Short-channel effects and models

91 SCBE Substrate current induced body effect Electron hole pair from impact ionization generates a drain substrate current. Current will increase exponentially with drain voltage Substrate resistance IR drop. 21 / 32 Short channel Ro CHM DIBL SCBE 22 / 32 INF4420 Spring 2012 Short-channel effects and models

92 Gate tunneling current Thinner gate oxide increases probability of carriers tunneling through the oxide. Also GIDL (Gate induced drain leakage) / 32 MOSFET device models As circuit designers we need to accurately predict circuit performance. Circuit simulators can use much more sophisticated device models than we use for hand calculation and analysis. As technology scale, models evolve to take new effects into account in order to predict device behaviour with sufficient accuracy. 24 / 32 INF4420 Spring 2012 Short-channel effects and models

93 Shichman Hodges Model Also known as a "level 1 model" because of SPICE. Approximately the simple equations we use for hand analysis of circuits. (Id and capacitance). Usually not sufficiently accurate, except for several um gate length techology. 25 / 32 BSIM Berkeley Short-Channel IGFET Model BSIM3v BSIM (currently BSIM4.7.0, 2011) BSIM4 includes all short channel effects we have discussed. Significantly better Ro prediction (which has been a problem). 26 / 32 INF4420 Spring 2012 Short-channel effects and models

94 BSIM Increasing number of non-physical parameters to fit measured device characteristics. Finding parameters to accurately model devices is challenging. Currently more than 200 parameters (binning, and several transistor flavours in one process). 27 / 32 Binning and corners Different sets of parameters for different device sizes (binning). Simulator selects parameter set automatically. Different sets of parameters for process corners (FF, SS, FS, SF). Statistical parameters for monte-carlo analysis. 28 / 32 INF4420 Spring 2012 Short-channel effects and models

95 EKV model Charge-based compact model. Not widespread adoption for simulation, but can be useful for hand analysis. Possible to extract parameter set e.g. from BSIM parameters supplied by the foundry. 29 / 32 PSP MOSFET model From "PSP is a surface-potential based MOS Model, containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping gradient effects, STI stress, etc.) to model present-day and upcoming deep-submicron bulk CMOS technologies." accurate higher order derivatives more physics based modelling rather than threshold voltage 30 / 32 INF4420 Spring 2012 Short-channel effects and models

96 Models Device modeling is difficult. Parameter extraction is difficult. Do not blindly trust models. Sophisticated device models offer little intuition for design. Square law equations can not be used for design. Instead, chart based design (gm/id). Corner simulation also helps robustness against model parameters. 31 / 32 Online resources As usual, not curriculum: BSIM manual: edu/~bsim3/bsim4/bsim470/bsim470_manual.pdf BSIM parameter fitting: org/r5/denver/sscs/references/2003_03_assenmacher.pdf Check list for device models: com/whitepapers/determine%20foundry-model%20problems%20without%20touching%20a% 20Wafer.pdf Chart based design: 32 / 32 INF4420 Spring 2012 Short-channel effects and models

97 INF4420 Random mismatch Spring / 23 Outline Systematic vs. random mismatch Hand calculation of random mismatch Sources of random mismatch Offset and calibration 2 / 23 INF4420 Spring 2012 Mismatch

98 Matching Previously we have discussed systematic mismatch. Systematic mismatch can be minimized by careful layout or trimming. Binning is also used. When "identical" devices are manufactured, random fluctuations cause electrical parameters of devices on the same die to have a statistical distribution. (Random mismatch) 3 / 23 Matching Need good matching between devices in input pair. And devices in current mirror. Both systematic and random. Trimming can help both. Typically want to minimize inherent effect of both. 4 / 23 INF4420 Spring 2012 Mismatch

99 Systematic mismatch Desired mean value Systematic mismatch 5 / 23 Random mismatch Better = more devices will be closer to the desired (mean) value Better Worse 6 / 23 INF4420 Spring 2012 Mismatch

100 Worst-case analysis Assuming a normal distribution (reasonable assumption from central limit theorem). Worst case minimum value: μ - 3σ Worst case maximum value: μ + 3σ 3σ would capture % 6σ would capture % 7 / 23 Monte-carlo simulation Fab provides statistical parameters for device models. Run a large number of simulations with different permutations of parameters. Does not neccessarily give insight into which devices are causing problems, or how to improve yield. 8 / 23 INF4420 Spring 2012 Mismatch

101 Hand calculation Manufacturing devices with different W/L, distance, orientation to see how this affects matching. A systematic study of mismatch between parameters of two identical MOSFETs. 9 / 23 Hand calculation Matching of parameter, P, between two identically drawn devices Area proportionality constant Distance Size Variation with spacing SpDx can be made small with good layout 10 / 23 INF4420 Spring 2012 Mismatch

102 Hand calculation Mismatch between two identically drawn transistors. Will do hand calculation to find ΔVth and Δß/ß. Use this to find ΔId/Id, Vos, etc. 11 / 23 Sources of randomness Line edge roughness (LER) Random dopand fluctuation (RDF) Gate oxide thickness... Some effects due to the manufacturing process may not be truly random, but will appear random to us as designers, because it's outside our control. We will count this as "random". 12 / 23 INF4420 Spring 2012 Mismatch

103 Line edge roughness "LER is caused by a number of statistically fluctuating effects at these small dimensions such as shot noise (photon flux variations), statistical distributions of chemical species in the resist such as photoacid generators, the random walk nature of acid diffusion during chemical amplification, and the nonzero size of resist polymers being dissolved during development. It is unclear which process or processes dominate in their contribution to LER." [ 13 / 23 Random dopant fluctuation As features scale, fewer dopant atoms in the channel. The relative contribution of one atom increases. Single atom affects electrical parameters. 14 / 23 INF4420 Spring 2012 Mismatch

104 Basic rule of matching Big devices match better. Randomness averages out more over a larger area. Big devices, more capacitance, more area. Reducing random mismatch comes at a cost. Important to know how much mismatch we can live with to avoid costly overdesign. 15 / 23 Threshold voltage Important contributions are tox and dopant concentration in channel region Improves with scaling in tox Technology parameter Best guess 16 / 23 INF4420 Spring 2012 Mismatch

105 Beta variability Relative current factor mismatch, Δß/ß [%] Best guess for A ß is 2 % µm 17 / 23 Drain current mismatch 18 / 23 INF4420 Spring 2012 Mismatch

106 ΔId/Id vs Vgs 19 / 23 Current mirror example One standard deviation! 20 / 23 INF4420 Spring 2012 Mismatch

107 Input referred offset 21 / 23 Digital offset calibration 22 / 23 INF4420 Spring 2012 Mismatch

108 References Orshansky, et al., Design for Manufacturability and Statistical Design, Springer, 2008 Pelgrom, Component matching: best practices and fundamental limits, IDESA. Pastre and Kayal, Methodology for the Digital Calibration of Analog Circuits and Systems, Springer, / 23 INF4420 Spring 2012 Mismatch

109 INF4420 Non-linearity Spring / 18 Outline Non-linearity and harmonic distortion Differential circuits Feedback Improving linearity 2 / 18 INF4420 Spring 2012 Non-linearity

110 Introduction Linear distortion from filtering (not considered) Soft non-linearity (expanding, compression) Hard non-linearity (clipping) 3 / 18 Introduction Amplification and non-linearity depends on the biasing point. Biasing point Amplifier DC transfer function Soft non-linearity Hard non-linearity (clipping) 4 / 18 INF4420 Spring 2012 Non-linearity

111 Introduction Measure deviation from ideal straight line approximation 5 / 18 Common source amp 6 / 18 INF4420 Spring 2012 Non-linearity

112 Taylor series Using Taylor series allows studying distortion independent of the specific shape of the nonlinearity. Generic expression for total harmonic distortion (THD). 7 / 18 Taylor series 8 / 18 INF4420 Spring 2012 Non-linearity

113 Harmonic distortion 9 / 18 Harmonic distortion 10 / 18 INF4420 Spring 2012 Non-linearity

114 Harmonic distortion 11 / 18 Common source linearity Large signal current: Input signal Harmonic distortion: 12 / 18 INF4420 Spring 2012 Non-linearity

115 Differential pair Harmonic distortion: 13 / 18 Differential pair Differential circuits exhibit much less distortion (5 % vs % for V m = 0.2(V GS - V TH ) Linearity is also better when accounting for 2x current. 14 / 18 INF4420 Spring 2012 Non-linearity

116 Feedback 15 / 18 Resistive degeneration 16 / 18 INF4420 Spring 2012 Non-linearity

117 Resistive degeneration Resistive degeneration also works for diff pairs 17 / 18 Post correction Cascade non-linear stage with inverse non-linearity. Ideally gives overall linear transfer funciton 18 / 18 INF4420 Spring 2012 Non-linearity

118

119 INF4420 Switched capacitor circuits Spring / 54 Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators 2 / 54 INF4420 Spring 2012 Switched capacitor

120 Introduction Discrete time analog signal processing Why? 3 / 54 Introduction The arrangement of switches and the capacitor approximates a resistor. Analyze each clock phase separately 4 / 54 INF4420 Spring 2012 Switched capacitor

121 Introduction Assuming steady-state, and arbitrarily assume V A > V B. T is one clock cycle. 1. At the beginning of ϕ 1, node V C is at V B Volt 2. During ϕ 1, V C is charged to V A. Charge transfer from V A to C: ΔQ = C(V A - V B ) 3. During ϕ 2 : ΔQ transfered from C to V B Net charge transfer, ΔQ, from V A to V B in T sec. I AVG = C(V A - V B )/T, R AVG = T/C 5 / 54 Introduction RC accuracy (matching). Large time constants. 6 / 54 INF4420 Spring 2012 Switched capacitor

122 Introduction Resistive loading is not ideal for CMOS 7 / 54 Introduction Capacitive feedback. DC issues. 8 / 54 INF4420 Spring 2012 Switched capacitor

123 Switch-cap amplifier Analyze ϕ 1 and ϕ 2 separately! 9 / 54 Switch-cap amplifier Phase ϕ 1 : C 1 tracks V in, Q = C V 1 in Phase ϕ 2 : Charge transfer from C 1 to C 2 10 / 54 INF4420 Spring 2012 Switched capacitor

124 Switch-cap amplifier 1. During ϕ 1, C 1 is charged to Q = C 1 V in 2. During ϕ 2, the charge, Q, is transferred to C 2. If C 1 and C 2 are of different value, the same charge will give a different voltage drop 11 / 54 Sampling Discrete time, continuous amplitude Signal, x(t), sampled at discrete time points, nt 12 / 54 INF4420 Spring 2012 Switched capacitor

125 MOSFET analog switch During ϕ 1, V out tracks V in After ϕ 1 the switch is closed and V in (from the end of ϕ 1 ) is held on C H. However, the MOSFET "switch" is not perfect / 54 MOSFET analog switch Finite resistance (settling) Charge injection Clock feed-through 14 / 54 INF4420 Spring 2012 Switched capacitor

126 Large signal behaviour NMOS can discharge effectively from Vdd to 0 (compare to a digital inverter). Saturation, then triode. However, the NMOS can not charge from 0 to Vdd. The MOSFET will enter subthreshold and current through the switch will be low. Output will settle to Vdd - Vth. If we wait for a long time, output will slowly approach Vdd. 15 / 54 Finite switch resistance Complimentary switch resistance, still problems for low Vdd PMOS NMOS 16 / 54 INF4420 Spring 2012 Switched capacitor

127 Finite switch resistance The RC time constant will define the sampling time, therefore the maximum frequency of operation. 17 / 54 Finite switch resistance Even if we restrict the input voltage range so that we avoid subthreshold. The settling speed will still be limited by the finite switch resistance. Signal dependent 18 / 54 INF4420 Spring 2012 Switched capacitor

128 Finite switch resistance Settling behaviour introduces an error in the final value. Need to wait several time constants for accurate settling. 19 / 54 Finite switch resistance t s ε 3RC 5 % 7RC 0.1 % 9RC 0.01 % Faster settling: Smaller C (more noise and parasitics more prominent) or smaller R (wider transistor, more channel charge) 20 / 54 INF4420 Spring 2012 Switched capacitor

129 Clock feed-through Capacitive voltage divider (hold capacitor and parasitic overlap capacitor) Signal independent! Increasing C H helps but degrades settling speed 21 / 54 Charge injection Channel charge, Q ch, when switch is "on". Released when switch turns off. Common assumption: Half the channel charge goes to source and other half to drain. 22 / 54 INF4420 Spring 2012 Switched capacitor

130 Charge injection Q ch is a function of V in and (worse) V TH is a function of V in through body effect (non-linear). Charge distribution is complex and poorly modelled Signal dependence 23 / 54 Charge injection Figure of merit (FoM) to study speed vs. precision trade-off. Larger C H makes charge injection less prominent but also increases the time constant and therefore ΔV from settling error. 24 / 54 INF4420 Spring 2012 Switched capacitor

131 Charge injection Dummy switch will ideally cancel the injected channel charge. Because the charge distribution is complex, finding the optimal size of the dummy switch is difficult. The purpose of the dummy switch is to soak up channel charge from the main switch. Best guess size Dummy 25 / 54 Charge injection Bottom plate sampling: ϕ 1a turns off slightly before ϕ 1, injecting a constant channel charge. Signal dependent charge from ϕ 1 will ideally not enter C H (no path to ground). 26 / 54 INF4420 Spring 2012 Switched capacitor

132 Bootstrapped switch Include extra circuitry to generate a clock voltage that takes V in into account to generate a constant V GS. Reliability concerns. Complexity. Better R ON independent of V in. High clock V in + V dd 27 / 54 Amplifier specification C in (contributes to gain error) Slew rate DC gain (loop gain, determines static error) GBW (determines dynamic error) Phase margin (stability) Offset (can be compensated, CDS) Noise (offset compensation helps 1/f noise) 28 / 54 INF4420 Spring 2012 Switched capacitor

133 Sampling and z-transform For continuous time circuits the Laplace transform is very convenient as it allows us to solve differential equations using algebraic manipulation. Analyzing SC circuits in terms of charge transfer, and charge conservation, results in difference equations. Need a similar tool for this case. 29 / 54 Sampling and z-transform Laplace transform: Input signal Fourier transform: 30 / 54 INF4420 Spring 2012 Switched capacitor

134 Sampling and z-transform Circuit and waveforms for illustrating sampling theory 31 / 54 Sampling and z-transform Modelling the sampled output, f * (t) Step function: Laplace transforms: 32 / 54 INF4420 Spring 2012 Switched capacitor

135 Sampling and z-transform assuming f(t) = 0 for t < 0 33 / 54 Sampling and z-transform Impulse sampling: Choose τ "infinitely narrow" and the gain, k = 1/τ (area of the pulse equal to the instantaneous value of the input, f(nt)). In this case, we find: A very convenient notation: 34 / 54 INF4420 Spring 2012 Switched capacitor

136 Sampling and z-transform The z-transform is very convenient for sampled data systems: Delay by k samples (k periods): Important! 35 / 54 Sampling and z-transform We have assumed infinitely narrow pulses. Most switched capacitor systems will have sample and hold (S&H) behaviour. 36 / 54 INF4420 Spring 2012 Switched capacitor

137 Sampling and z-transform Use the same equation as before, but instead of letting τ be infinitely narrow, we let τ = T. Sample & hold: 1 for impulse sampling 37 / 54 Sampling and z-transform Comparing F * (s) and F SH (s), we define the transfer function of the sample and hold as: 38 / 54 INF4420 Spring 2012 Switched capacitor

138 Frequency response Comparing the z-transform to the Fourier transform, we can find the frequency response from the z-domain expression, s = jω gives z = e jωt. 39 / 54 Frequency response z-transform: z e st. Mapping between s-plane and z-plane. Points on the imaginary axis of the s-plane map to the unit circle in the z-plane, periodic with 2π For a sampled data system, frequency response is z-domain expression evaluated on the unit circle in the z-plane. Poles must be inside unit circle for stability. 40 / 54 INF4420 Spring 2012 Switched capacitor

139 Frequency response Spectrum of an input signal Sampling introduces images 41 / 54 Frequency response Multiplying by the transfer function of the sample and hold, we find the frequency spectrum of F SH (jω) (sin(x)/x, sinc-response). Linear distortion from droop. 42 / 54 INF4420 Spring 2012 Switched capacitor

140 Frequency aliasing If the signal contains frequencies beyond f s /2 when sampled, aliasing will occur (non-linear distortion). Images of the original signal interfere. 43 / 54 Frequency aliasing A continuous time low-pass filter (anti-aliasing filter) on the input to the sampled data system will ensure that the input signal is band limited to a frequency below the Nyquist frequency. Need to take some margin to account for the transition band of the filter (usually first or second order). 44 / 54 INF4420 Spring 2012 Switched capacitor

141 Switch-cap integrator C j parasitic capacitance 45 / 54 Switch-cap integrator Charge on C 1 is proportional to V in, Q 1 = C 1 V in. Each clock cycle, Q 1, is transferred from C 1 to C 2. C 2 is never reset, so charge accumulates on C 2 (indefinitely). We are adding up a quantity proportional to the input signal, V in. This is a discrete time integrator. In the following, we assume the output is read during ϕ / 54 INF4420 Spring 2012 Switched capacitor

142 Switch-cap integrator Output at ϕ 1 Delaying 47 / 54 Switch-cap integrator Approx frequency response: z = e jωt 1 + jωt Valid when ωt is close to zero. I.e. when signal frequency is low compared to sampling freq. Compare to continuous time 48 / 54 INF4420 Spring 2012 Switched capacitor

143 Switch-cap integrator Insensitive to non-linear parasitic cap, C j Critical wrt. performance Turn off first (bottom plate sampling) 49 / 54 Switch-cap integrator During ϕ 1 C 1 tracks V in and V out is constant. 50 / 54 INF4420 Spring 2012 Switched capacitor

144 Switch-cap integrator During ϕ 2 charge is transferred from C 1 to C 2. V out settles to the new value. 51 / 54 Switch-cap integrator Analysis similar to the parasitic sensitive integrator, however, polarity of the capacitor changes because of the switching. So gain is not inverting. Looking at the output during ϕ 1 we have a delaying non-inverting integrator. 52 / 54 INF4420 Spring 2012 Switched capacitor

145 Switch-cap integrator By changing the switching we get a nondelaying inverting int. 53 / 54 References Gregorian and Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, 1986 Baker, Mixed Signal Circuit Design, IEEE Wiley, 2009 Sansen, Analog Design Essentials, Springer, 2006, Ch. 17 Johns and Martin, Analog Integrated Circuit Design, Wiley, / 54 INF4420 Spring 2012 Switched capacitor

146

147 INF4420 Data Converters Spring / 30 Outline Quantization Sampling jitter DFT and windowing Data encoding 2 / 30 INF4420 Spring 2012 Data Converters

148 Introduction Digital signal processor (DSP) Signal processing can be more efficient, robust, and convenient in the digital domain (algorithms in digital circuits and software). Need to convert to and from analog to interface with the world. 3 / 30 Introduction Anti-alias filter Reconstruction filter Digital processing Continuous time input and output, but with digital processing. 4 / 30 INF4420 Spring 2012 Data Converters

149 Introduction Data conversion accuracy limits system performance. In-depth understanding of data converter performance is important for the design of mixed-signal systems. How do we quantify data converter performance? 5 / 30 Introduction Important to pay attention to mixed signal layout issues. Data converters combine sensitive high accuracy circuits for generating reference levels (bandgaps) with digital switching (current spikes). For high resolution converters, the external environment (e.g. PCB) is very important. 6 / 30 INF4420 Spring 2012 Data Converters

150 Quantization Data converters must represent continuous values in a range using a set of discrete values. A binary code is used to represent the value. Information is lost! Open Clipart Library (openclipart.org) Hot or cold Freezing, cold, warm, or hot. -20 C, C,..., 20 C. 7 / 30 Quantization Number of bits, N 8 / 30 INF4420 Spring 2012 Data Converters

151 Quantization The quantization error is restricted to the range -Δ/2 to Δ/2. The quantization process is non-linear! 9 / 30 Quantization noise Model the quantization error as noise added to the original signal. Enables linear analysis. 10 / 30 INF4420 Spring 2012 Data Converters

152 Quantization noise Quantization noise assumptions: All quantization levels have equal probability Large number of quantization levels, M Uniform quantization steps, constant Δ Quantization error uncorrelated with input Quantization noise is white! 11 / 30 Quantization noise Time average power (variance): 12 / 30 INF4420 Spring 2012 Data Converters

153 Quantization noise Assuming sine wave input SNR due to quantization noise 13 / 30 Sampling jitter Uncertainty in the timing of the sampling clock due to circuit electrical noise (white noise + 1/f). Reference sampling edge 14 / 30 INF4420 Spring 2012 Data Converters

154 Sampling jitter Sampling clock timing jitter translates to an error in the sampled value. Impacts SNR. 15 / 30 Sampling jitter Worst-case full scale sine wave at the Nyquist frequency. Error due to jitter should be less than half the quantization step. 16 / 30 INF4420 Spring 2012 Data Converters

155 Discrete Fourier Transform Many data converter performance metrics are carried out more straightforward in the frequency domain. The Discrete Fourier Transform (DFT) is used to analyze a set of N samples. Assumes the N samples are one period of an infinitely repeating signal. Result is a set of N complex numbers, the frequency domain representation of the signal. 17 / 30 Discrete Fourier Transform The DFT can be efficiently computed using the Fast Fourier Transform (FFT). 18 / 30 INF4420 Spring 2012 Data Converters

156 Windowing The DFT assumes periodic input. Window functions are used to introduce artificial periodicity. Time domain Freq. domain Trade-offs Amplitude accuracy Sidelobes Width of signal peak 19 / 30 Binary data coding Alternatives for representing the quantized value in binary Unipolar Bipolar Two's complement / 30 INF4420 Spring 2012 Data Converters

157 Static specifications 21 / 30 Static specifications Gain Offset INL DNL Missing codes (output code which can not be reached by any input value) Monotonicity (increasing input value will always produce equal or higher output code) / 30 INF4420 Spring 2012 Data Converters

158 Dynamic specifications Obtained from the DFT (FFT) SNR SINAD SFDR THD DR 23 / 30 SFDR Spurious free dynamic range. Relative to highest spur (not only harmonics) 24 / 30 INF4420 Spring 2012 Data Converters

159 SNR Signal to noise ratio. Signal power, divided by noise power (exclude harmonics) 25 / 30 THD Total harmonic distortion A measure of the distortion excluding noise. 26 / 30 INF4420 Spring 2012 Data Converters

160 SINAD Signal to noise and distortion ratio. 27 / 30 Dynamic specifications Other dynamic specifications: Intermodulation distortion (IMD) Settling time Glitching 28 / 30 INF4420 Spring 2012 Data Converters

161 Figure of merit (FoM) Equivalent number of bits: Figure of merit (FoM): 29 / 30 Resources Not part of the curriculum Converter Passion (blog covering many aspects of data converters) Kester, The Data Conversion Handbook, Analog Devices, 2004 Heinzel et al., Spectrum and spectral density estimation..., Max-Planck-Institut für Gravitationsphysik, / 30 INF4420 Spring 2012 Data Converters

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163 INF4420 Digital to analog converters Spring / 25 Outline Resistive DACs Capacitive DACs Current steering 2 / 25 INF4420 Spring 2012 Digital to Analog Converters

164 Introduction Digital to analog converters (DACs), takes a digital input word, and converts it to a voltage or current proportional to the input value. Usually the DAC will use an arrangement of switches and resistors, capacitors, or current sources, to generate an output that is a fraction of or proportional to some reference current or voltage (bandgap). 3 / 25 Introduction Proper layout (to reduce mismatch) is critical for performance. Switches are also critical (signal dependent R on, clock feed-through, and charge injection). DACs find numerous applications, from trimming and adjustment circuits to high-end video DACs (12 bit, 150 MSPS), and communication circuits. 4 / 25 INF4420 Spring 2012 Digital to Analog Converters

165 Introduction Outline of the full digital to analog converter. 5 / 25 Resistive divider (Kelvin divider) DAC 6 / 25 INF4420 Spring 2012 Digital to Analog Converters

166 Kelvin divider Different switching schemes are possible. Tree X-Y 7 / 25 Output settling There is inherent resistance in the resistive divider. Switches have both R on and parasitic capacitance (also for switches turned off). Resistance is code dependent. Capacitance is approximately constant. Gives rise to exponential settling. 8 / 25 INF4420 Spring 2012 Digital to Analog Converters

167 Output settling Output buffer will have finite slew rate (large signal) and gain bandwidth (small signal). Slewing Exponential settling from finite gain bandwidth 9 / 25 Mismatch Resistors are affected by systematic and random mismatch, causing a deviation from their ideal value. Linear gradient in resistor values gives rise to a parabolic INL. Harmonic distortion! Good layout is important. Trimming or calibration may be necessary. 10 / 25 INF4420 Spring 2012 Digital to Analog Converters

168 R-2R resistor ladder DAC 11 / 25 Deglitch Glitches are likely to occur when the DAC is switching (overshoot resulting in more settling and slewing). A track and hold (T&H) amplifier can be used to avoid glitches on the output of the DAC. Timing of the T&H relative to the DAC input is critical (track while the output is constant, and hold when the output is transitioning). Noise and linearity of the T&H must be sufficient. 12 / 25 INF4420 Spring 2012 Digital to Analog Converters

169 Capacitive divider DAC Array of binary weighted capacitors. We program which capacitors are connected between out and gnd, or between out and ref. 13 / 25 Capacitive divider DAC Capacitive divider where we program which capacitors belong to C 1 or C 2. Digitally programming the fraction of V ref. 14 / 25 INF4420 Spring 2012 Digital to Analog Converters

170 Capacitive divider DAC Samples amplifier offset (and 1/f noise) during reset. Avoids rail-to-rail buffer input. 15 / 25 Current source DAC 16 / 25 INF4420 Spring 2012 Digital to Analog Converters

171 Current source DAC Current source with finite output resistance, switch resistance, and resistive loading. Norton equivalent. 17 / 25 Current source DAC α must be small for acceptable INL and distortion. Current sources with large output impedance Differential output (cancels even harmonics) Amplifier virtual ground (speed issues) 18 / 25 INF4420 Spring 2012 Digital to Analog Converters

172 Current source DAC Using cascode (M 1 ), the output resistance is approximately g m r o 2. Depending on biasing of the cascode, V cp, we need 2V DS,sat + V TH or 2V DS,sat. Active cascode also possible. 19 / 25 Current source DAC Random variation of drain current is an important limitation. Need to design current sources with sufficient area and overdrive. Gate current can be problematic. 20 / 25 INF4420 Spring 2012 Digital to Analog Converters

173 Current source DAC Addressing unity current sources in a 2D array. Sequential selection Common centroid Random (several possibilities) Segmenting the array with a local current replica is also useful. 21 / 25 Current source DAC Switch driver must ensure switches are not off at the same time to avoid triodeing the current source (recovery time). 22 / 25 INF4420 Spring 2012 Digital to Analog Converters

174 Ideal reconstruction filter The DAC output has a S&H response. Need an output filter to further attenuate frequency images and smooth out the time domain waveform. 23 / 25 Ideal reconstruction filter The ideal reconstruction filter is not realizable (infinite impulse response without recursion), we must use an approximation of the ideal brick wall filter instead. 24 / 25 INF4420 Spring 2012 Digital to Analog Converters

175 Resources Not part of the curriculum Mercer, Digital to Analog Converter Design Baker, CMOS: Circuit Design, Layout, and Simulation, IEEE Wiley, 2010 Sansen, Analog Design Essentials, Springer, 2006, Ch / 25 INF4420 Spring 2012 Digital to Analog Converters

176

177 INF4420 Analog to digital converters Spring / 28 Outline Comparators Circuit topologies for analog to digital Flash Interleaved Folding Interpolation Two-step Pipelined Algorithmic SAR Integrating 2 / 28 INF4420 Spring 2012 Analog to Digital Converters

178 Introduction ADCs are used in numerous applications with differing requirements on speed, accuracy, and energy efficiency. ADC architectures have different strengths and weaknesses with respect to these trade offs. It is therefore important to understand not only how each converter works, but also its limitations and key aspects for performance. 3 / 28 Comparators Basic quantization element. Propagation delay Metastability Resolution limited by offset and noise Kickback noise Memory, hysteresis 4 / 28 INF4420 Spring 2012 Analog to Digital Converters

179 Comparators Improve resolution/ sensitivity of the comparator Amplify the decision of the comparator Buffer result to digital levels 5 / 28 Comparators Comparator example Decision circuit Preamplifier Buffer not shown 6 / 28 INF4420 Spring 2012 Analog to Digital Converters

180 Comparators Clocked (latched) comparator example Pos. output Van Elzakker, ISSCC, / 28 Flash ADC The Kelvin divider is used to generate 2 N reference voltages, and comparator s are used for quantization V sh is V in sampled and held 8 / 28 INF4420 Spring 2012 Analog to Digital Converters

181 Flash ADC Resistive divider string imposes the same limitations as for the DAC case. Linear gradient results in a parabolic shape of the INL curve. Additionally, the comparators (preamplifiers) have offset, which must be less than ½ LSB. Auto-zero and fully differential (also 1/f-noise). 9 / 28 Flash ADC Bandgap stability and loading Dynamic gain (not full settling in the comparator preamplifier) Sample and hold loading from an exponential number of comparators 10 / 28 INF4420 Spring 2012 Analog to Digital Converters

182 Time interleaved ADC Run N ADCs in parallel to increase conversion rate. Offset and gain mismatch between channels. Clock misalignment (fixed). 11 / 28 Time interleaved ADC Example: Monolithic 40 Gs/s ADC in an SiGe process 12 / 28 INF4420 Spring 2012 Analog to Digital Converters

183 Folding Fold the input signal into regions. Folder determines MSBs. Need fewer comparators. 13 / 28 Interpolation Reducing number of comparator preamplifiers. Reduced loading of the sample and hold. 14 / 28 INF4420 Spring 2012 Analog to Digital Converters

184 Two-step ADC Combine output from the MSB ADC (M bits) and the LSB ADC (N bits) for the full output. The MSB ADC must be linear to M + N bits (< ½ LSB for INL and DNL) 15 / 28 Two-step ADC Performance constraints for the opamp used for gain and summing: Open loop gain, A OL, to achieve the desired closed loop gain, A CL. GBW to settle fast enough to the desired accuracy. Amplifier linearity Again, errors must be less than ½ LSB. 16 / 28 INF4420 Spring 2012 Analog to Digital Converters

185 Pipelined ADC More than 1 bit per stage is possible. Error correction 17 / 28 Algorithmic ADC A variation of the pipeline ADC is the algorithmic ADC, which reuses a single stage for all bits. Each conversion now takes N (number of bits) clock cycles. 18 / 28 INF4420 Spring 2012 Analog to Digital Converters

186 SAR ADC The successive approximation register (SAR) tests each bit sequentially (MSB first, one clock period per bit), and decides whether too keep the bit or not based on the comparator's output. 19 / 28 Charge redistribution SAR Examples of energy efficient (FoM) ADCs / 28 INF4420 Spring 2012 Analog to Digital Converters

187 Charge redistribution SAR Ref. capacitive divider DAC Inherent sample and hold function SAR not shown 21 / 28 Charge redistribution SAR Reset and sampling: In the first clock phase, V in and V os are sampled. Next, the bottom plates are switched to ground, and V x = -V in. Then, each bit is tested (MSB first) by switching each capacitor between ground and V ref. V x is compared for each bit (SAR). 22 / 28 INF4420 Spring 2012 Analog to Digital Converters

188 Charge redistribution SAR Suitable for low-power. No amplifiers needed (except for the comparator). Comparator and charging of the capacitive array decides power consumption. Capacitor mismatch limits resolution. Speed limited by τ = R total 2 N C, e -t/τ < 1 / 2 N+1 (½ LSB), t > τ (N+1) ln 2 23 / 28 Integrating ADC Dual slope integrating ADC. c 0 and c 1 are control signals V x Counter and control logic not shown. 24 / 28 INF4420 Spring 2012 Analog to Digital Converters

189 Integrating ADC In phase 1, -V in is integrated during a fixed interval (T 1 ). In phase 2, V x is integrated (discharged) by V ref. A digital counter is running from the start of phase 2 while V x > 0. The counter value is the digital output. 25 / 28 Integrating ADC Need many clock cycles to complete the conversion (slow), but can achieve high accuracy. A simpler alternative is the single slope ADC, which counts how long it takes to integrate V ref to V in. (Less accurate). 26 / 28 INF4420 Spring 2012 Analog to Digital Converters

190 Resources B. Murmann, ADC performance survey , [Online]. Available: IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std (Revision of IEEE Std ) / 28 References Baker, CMOS: Circuit Design, Layout, and Simulation, IEEE Wiley, 2010 Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997 Sansen, Analog Design Essentials, Springer, 2006, Ch / 28 INF4420 Spring 2012 Analog to Digital Converters

191 INF4420 ΔΣ data converters Spring / 31 Outline Oversampling Noise shaping Circuit design issues Higher order noise shaping 2 / 31 INF4420 Spring 2012 Delta Sigma data converters

192 Introduction So far we have considered so called Nyquist data converters. Quantization noise is a fundamental limit. Improving the resolution of the converter, translates to increasing the number of quantization steps (bits). Requires better component matching, A OL > β -1 2 N+1, and GBW > f s ln 2 N+1 π -1 β / 31 Introduction ΔΣ modulator based data converters relies on oversampling and noise shaping to improve the resolution. Oversampling means that the data rate is increased to several times what is required by the Nyquist sampling theorem. Noise shaping means that the quantization noise is moved away from the signal band that we are interested in. 4 / 31 INF4420 Spring 2012 Delta Sigma data converters

193 Introduction We can make a high resolution data converter with few quantization steps! The most obvious trade-off is the increase in speed and more complex digital processing. However, this is a good fit for CMOS. We can apply this to both DACs and ADCs. 5 / 31 Oversampling The total quantization noise depends only on the number of steps. Not the bandwidth. If we increase the sampling rate, the quantization noise will not increase and it will spread over a larger area. The power spectral density will decrease. 6 / 31 INF4420 Spring 2012 Delta Sigma data converters

194 Oversampling Take a regular ADC and run it at a much higher speed than twice the Nyquist frequency. Quantization noise is reduced because only a fraction remains in the signal bandwidth, f b. 7 / 31 Oversampling Doubling the OSR improves SNR by 0.5 bit Increasing the resolution by oversampling is not practical. We can do better! Oversampling is almost always used with noise shaping. 8 / 31 INF4420 Spring 2012 Delta Sigma data converters

195 Noise shaping The idea behind noise shaping is to suppress the noise in the signal band, at the expense of increasing noise at higher frequencies. The ΔΣ modulator does noise shaping. 9 / 31 Noise shaping Linear discrete time model Two independent inputs, u and e. We derive a transfer function for the signal and quantization noise separately. 10 / 31 INF4420 Spring 2012 Delta Sigma data converters

196 Noise shaping Signal transfer function (STF), H s 11 / 31 Noise shaping Noise transfer function (NTF), H n 12 / 31 INF4420 Spring 2012 Delta Sigma data converters

197 Noise shaping 13 / 31 Noise shaping NTF frequency response 14 / 31 INF4420 Spring 2012 Delta Sigma data converters

198 Noise shaping First order ΔΣ modulator based data converter NTF OSR Assuming full-scale sine wave input (as before) Doubling OSR improves SNR by 1.5 bits 15 / 31 Circuit example First order ΔΣ ADC (sampled data single bit quantizer) implementation. 16 / 31 INF4420 Spring 2012 Delta Sigma data converters

199 Single-bit quantization Quantizer nonlinearity is shaped by the NTF, but still needs to be less than the inherent quantization noise. Feedback signal does not undergo shaping and adds directly to the input. Needs linearity better than the equivalent resolution of the ADC. Single bit quantizer: Only two levels, inherent linearity. (Second order effects: switching, etc.) 17 / 31 Single-bit quantization Linear analysis assumed quantization noise is white, however input signal may give rise to patterns in the quantization noise. Quantization noise energy will be clustered at some frequencies. Tones in the output signal. Idle tones or pattern noise for DC input. Intentionally add noise to decorrelate the quantization noise pattern, dithering. 18 / 31 INF4420 Spring 2012 Delta Sigma data converters

200 Multi-bit quantization Single bit quantization will introduce significant (out of band) quantization noise which must be attenuated by a filter. We have assumed a brick-wall filter in our analysis. Multi-bit quantization will reduce the inherent quantization noise, and performance is better predicted by the linear analysis. Linearity is challenging (no shaping). 19 / 31 Multi-bit quantization Several techniques for linearizing the DAC (not discussed further, see Schreier, 2005): Dual quantization Mismatch shaping Digital correction 20 / 31 INF4420 Spring 2012 Delta Sigma data converters

201 Integrator In the analysis so far, we have assumed an ideal integrator. Real integrators can only approximate the ideal integrator, because the amplifier has finite gain, bandwidth, offset, etc. 21 / 31 Finite gain NTF affected by finite gain Finite gain will shift the pole of the integrator from DC (z = 1), to inside the unit circle (approximately z = 1-1 / A 0 ). 22 / 31 INF4420 Spring 2012 Delta Sigma data converters

202 Finite bandwidth Assuming the amplifier has one dominant pole and negligible non-dominant poles. Must allow sufficient time for settling, the settling error is proportional to Gain error due to bandwidth and passives introduce poles in both STF and NTF 23 / order noise shaping Introduce one more integrator to achieve better noise suppression (at low frequencies). NTF is now a second order differentiator. 24 / 31 INF4420 Spring 2012 Delta Sigma data converters

203 2. order noise shaping Doubling the OSR improves the SNR by 2.5 bits. Compared to 1.5 bits for 1. order. 25 / 31 Higher order noise shaping Noise shaping can be improved even further by using a 3. order (or higher) modulator. Possible to design the gain of each integrator to shape the NTF. Difficult to guarantee stability. Instead we can build a higher order modulator from a cascade of lower order modulators: Multi-stage noise shaping (MASH). 26 / 31 INF4420 Spring 2012 Delta Sigma data converters

204 Multi-stage noise shaping Y 1 (z) Y 2 (z) 27 / 31 Multi-stage noise shaping Choose H 1 (z) and H 2 (z) such that E 1 (z) is canceled. E.g. H 1 (z) = k H s2 (z) and H 2 (z) = k H n1 (z). 28 / 31 INF4420 Spring 2012 Delta Sigma data converters

205 Multi-stage noise shaping Cascading an L-th order and an M-th order modulator results in an overall L + M order modulator, but prone to instability. Non-ideal effects because H s2 (z) and H n1 (z) are in analog, while H 1 (z) and H 2 (z) are in digital. Imperfections in the analog circuitry (offset, gain, etc.) will deteriorate the noise suppression. 29 / 31 Oversampling DAC Interpolation Interpolation increases the sampling rate ΔΣ modulator quantizes and shapes noise (digital integrator) 30 / 31 INF4420 Spring 2012 Delta Sigma data converters

206 Resources Schreier and Temes, Understanding Delta- Sigma Data Converters, IEEE Wiley, 2005 Johns and Martin, Analog Integrated Circuit Design, Wiley, / 31 INF4420 Spring 2012 Delta Sigma data converters

207 INF4420 Ring oscillators Spring / 31 Outline Barkhausen criterion Ring oscillators Voltage controlled oscillators Oscillator phase model 2 / 31 INF4420 Spring 2012 Ring oscillators

208 Introduction Oscillators are used for synchronizing computation in a digital system, timing the sampling in a data converter, carrier synthesis and LO in RF systems, etc... Image: Openclipart.org 3 / 31 Introduction Different applications have very different requirements on accuracy and stability (e.g. jitter in data converters, timing violations, BER, etc.) Crystal oscillators are used for demanding applications. Excellent stability and frequency accuracy. Speed limitation and cost issues. 4 / 31 INF4420 Spring 2012 Ring oscillators

209 Feedback system Usually, we want the feedback system (amplifier) to be stable (difficult to guarantee stability). Now we want to ensure sustained oscillation at a fixed frequency (also difficult). 5 / 31 Feedback system Phase shift of 180 degrees at some frequency, ω0, gives positive feedback. Each time the signal "goes around the loop". Amplifier input, Vx, grows indefinitely if H(jω0) > 1 6 / 31 INF4420 Spring 2012 Ring oscillators

210 Barkhausen criterion The Barkhausen stability criterion is necessary but not sufficient for oscillation. The criteria for oscillation is not well understood, there is no known sufficient criteria for oscillation. 7 / 31 Oscillators LC oscillator, inductor, L, and capacitor, C, to generate resonance Used mostly for RF (inductors are expensive and impractical). Relaxation oscillators typically relies on charging and discharging a capacitor. Some active circuit will monitor and switch charging at a threshold. INF4420 Spring 2012 Ring oscillators 8 / 31

211 Ring oscillator Ring oscillators are made from gain stages, or delay stages, in feedback. We will first do a linear analysis of these oscillators with common source (CS) elements. 9 / 31 Ring oscillator A single CS stage in feedback will not oscillate, because it does not fulfill the Barkhausen criteria. The CS stage is inverting (180 ) and has one pole (90 ), 270 phase shift in total. 10 / 31 INF4420 Spring 2012 Ring oscillators

212 Ring oscillator Using two CS stages gives the required phase shift, but it is stable at either rail. 11 / 31 Ring oscillator Still no sustained oscillation because the gain is much less than one when phase is inverted. Ideal 12 / 31 INF4420 Spring 2012 Ring oscillators

213 Ring oscillator Three CS stages are enough for sustained oscillation provided the gain of each stage is sufficient (in this case, A0 2). 13 / 31 Ring oscillator If the gain of each stage is larger than necessary, A0 > 2, the output will saturate and linear analysis becomes difficult. 14 / 31 INF4420 Spring 2012 Ring oscillators

214 Ring oscillator The frequency of oscillation becomes 1 / (2n τ), where n is the number of elements, and τ is the delay due to each element (inverter in this case). 15 / 31 Fully differential oscillator Single ended oscillators are power efficient and capable of rail-to-rail output. However, as we now know, in mixed signal circuits there is supply and substrate noise which couples directly into the oscillator, or modulates its supply voltage. Causing undesirable fluctuations in the period time of the output signal. Fully differential circuits have CMRR and PSRR to combat this! 16 / 31 INF4420 Spring 2012 Ring oscillators

215 Fully differential oscillator The trip point for each stage is now the crossing of the inputs rather than a fraction of Vdd. Ideally, coupled noise will only affect the common mode. However, swing is not rail-torail. In addition to rejecting coupling noise, the fully differential oscillator allows the number of stages to be even, which is a significant advantage if we need to generate a number of output phases. 17 / 31 Fully differential oscillator Constant bias current. In most cases, the resistors will be implemented by MOS transistors, requiring a bias circuit. 18 / 31 INF4420 Spring 2012 Ring oscillators

216 Symmetric load delay cell Popular choice for implementing the fully differential delay cell. The symmetric load approximates a voltage controlled resistor Maneatis, JSSC, / 31 Symmetric load delay cell 20 / 31 INF4420 Spring 2012 Ring oscillators

217 Pseudo differential Pseudo differential elements are common in many applications. Rail-to-rail swing. Trip point defined by Vdd (worse CMRR). 21 / 31 Tuning output frequency So far, the oscillators have a "fixed" output frequency. Deviation from the ideal output frequency is undesirable (modulated by the PVT condition, and perturbed by external and internal noise sources). VCOs have an input terminal that allows external control of the frequency. 22 / 31 INF4420 Spring 2012 Ring oscillators

218 Voltage controlled osc. 23 / 31 Voltage controlled osc. Different schemes for controlling the output frequency. Modulating the driving strength Modulating the load Control signal is usually a voltage (VCO) or a current (CCO). Sometimes a V/I converter is used to interface a CCO with a voltage signal. 24 / 31 INF4420 Spring 2012 Ring oscillators

219 Ring oscillator VCO Several possibilities for implementing the delay stages and tuning circuit. 25 / 31 Ring oscillator VCO Starved inverter delay element Starved inverter bias circuit 26 / 31 INF4420 Spring 2012 Ring oscillators

220 Ring oscillator VCO Several specifications to consider Tuning range Linearity (ωout vs. Vctl) Amplitude Power CMRR, PSRR Jitter (phase noise) / 31 Mathematical model 28 / 31 INF4420 Spring 2012 Ring oscillators

221 Mathematical model Phase is not directly observable in a real oscillator. However, from observing the zero crossings of the output, we see when the phase has increased by π. The rate of change of the phase, ϕ, is the frequency, ω. Phase is the integral of frequency. Conversely, frequency is the derivative of the phase. 29 / 31 Mathematical model 30 / 31 INF4420 Spring 2012 Ring oscillators

222 Resources McNeill and Ricketts, The Designer s Guide to Jitter in Ring Oscillators, Springer, / 31 INF4420 Spring 2012 Ring oscillators

223 INF4420 Phase locked loops Spring / 28 Outline "Linear" PLLs Linear analysis (phase domain) Charge pump PLLs Delay locked loops (DLLs) Applications 2 / 28 INF4420 Spring 2012 Phase locked loops

224 Introduction Phase locked loops (PLLs) are versatile building blocks found in a variety of applications Frequency multiplication Frequency synthesis Clock deskew (PLL or DLL) Clock recovery (from serial data) Demodulation... 3 / 28 Introduction Feedback system for aligning (a fraction of) the phase of the VCO clock with an (external) reference clock. The VCO control voltage is adjusted to achieve this. 4 / 28 INF4420 Spring 2012 Phase locked loops

225 Introduction We will analyze the PLL in terms of phase. The objective of the feedback loop, the PLL, is to keep ϕ ref - ϕ out small and constant. In this state, the PLL is said to be in lock. This implies ω ref = ω out which is what we care about in many applications. 5 / 28 "Linear" PLL Phase detector Loop filter We will first analyze a PLL with a simple phase detector (PD) first. 6 / 28 INF4420 Spring 2012 Phase locked loops

226 Phase detector Phase is not directly observable. We have to infer the phase difference from the output of the oscillators. An XOR gate can be used as a phase detector. 7 / 28 Phase detector When ϕ ref and ϕ out is 90 out of phase, the XOR output will have 50/50 duty cycle, and the average output will therefore be V dd / 2. If ϕ ref and ϕ out is at 0 or 180 phase difference, the average output will be 0 or V dd respectively. 8 / 28 INF4420 Spring 2012 Phase locked loops

227 Phase detector 9 / 28 PLL with XOR PD With the XOR PD, to generate the required V ctl, ϕ ref and ϕ out must be out of phase. 10 / 28 INF4420 Spring 2012 Phase locked loops

228 Loop dynamics Linear analysis of the PLL in terms of phase, H (s) = ϕ out (s) / ϕ in (s). 11 / 28 Second order TF Generic second order transfer function applied to the PLL: Natural frequency Damping ratio 12 / 28 INF4420 Spring 2012 Phase locked loops

229 Loop dynamics By choosing PLL parameters, K VCO, K PD, and τ LF, we can design ω n and ζ, to obtain the desired loop dynamics. Magnitude response Step response 13 / 28 Large signal behaviour An important point for PLLs is the large signal behaviour when the system is not in lock. When the PLL starts up, ϕ ref and ϕ out may be very different. We must make sure that the system is able to achieve lock. Another concern is whether the PLL will lock to a harmonic instead. The PLL with XOR based PD is not robust in this case. In most applications, a so called charge pump (CP) PLL is preferred. 14 / 28 INF4420 Spring 2012 Phase locked loops

230 Charge pump PLL Tracks whether the reference edge or the VCO clock edge comes first (for every period), and adjusts the VCO control voltage accordingly to keep the PLL in lock. When the PLL is in lock, out and ref will be in phase. Phase frequency detector Charge pump Loop filter 15 / 28 Phase Frequency Detector In the Charge Pump (CP) PLL, a more elaborate PD with state is used, a Phase Frequency Detector (PFD). 16 / 28 INF4420 Spring 2012 Phase locked loops

231 PDF/CP and loop filter The PFD generates control signals for the CP to ramp up or down the VCO control voltage. 17 / 28 PFD/CP gain When the PLL is in lock, a small phase difference between the VCO clock (out) and the reference clock (ref) turns on the CP for a fraction of the clock period injecting a charge proportional to the phase error to the loop filter every period. Looking at several periods, an average current flows. K PFD is the combined gain of the PFD and the CP: 18 / 28 INF4420 Spring 2012 Phase locked loops

232 CP loop filter The loop filter is driven by I avg from the PFD/CP In many cases, a second capacitor, C 2, is added in parallel to reduce glitches. C 2 is usually chosen to be approximately 10 % of C 1 or less. 19 / 28 Transfer function The open loop transfer function from ϕ ref to ϕ out The closed loop CP PLL transfer function 20 / 28 INF4420 Spring 2012 Phase locked loops

233 Transfer function R gives rise to a zero at -1/(RC). It is required as system would be unstable with R = / 28 Non-ideal effects in PLLs PFD/CP will exhibit zero gain when the phase difference is small because of finite rise and fall times Up/down current mismatch due to timing or current source impedance Jitter from power supply, coupling, electronic noise, reference phase noise / 28 INF4420 Spring 2012 Phase locked loops

234 Delay locked loop (DLL) A DLL is similar to a PLL, but instead the delay through a voltage controlled delay line (VCDL) is locked. 23 / 28 Delay locked loop (DLL) Noise (jitter) does not accumulate in the delay line like it would in a VCO. As there is no VCO, the order of the loop is one less than the PLL. Stability and settling issues are less prominent. The DLL is not the same as a PLL and only relevant for some PLL applications. DLLs are usually preferred where applicable. 24 / 28 INF4420 Spring 2012 Phase locked loops

235 Frequency multiplication Frequency multiplication is a common application for PLLs. High speed clocks can be generated from a stable and precise (but slow) reference clock. N can be programmable. 25 / 28 Frequency demodulation The VCO performs frequency modulation (FM). The PLL can be used to find the inverse. The VCO control voltage becomes the output. 26 / 28 INF4420 Spring 2012 Phase locked loops