Department of Electrical and Information Engineering. Electronic Research Group

Transcription

1 University of Cassino and southern Lazio Department of Electrical and Information Engineering Electronic Research Group Laboratory of Industrial Electronics Contact: prof. Giovanni Busatto

2 ELECTRONICS Group STAFF Laboratory of Industrial Electronics Department of Electrical and Information Engineering Full Professor: Giovanni Busatto Associate Professors: Francesco Iannuzzo Annunziata Sanseverino Researchers: Francesco Velardi Carmine Abbate Ph.D. Student: Valentina De Luca Laboratory Technician: Tomasino Iovini

3 Main Activities Experimental (NDT) characterization of Power Devices Overvoltage, overcurrent, high and low temperature, short circuit stresses on power devices and modules Cosmic Ray effects on Power Devices (Burnout & Total dose) 2D/3D Devices FEM Simulation Devices Modeling & Simulation Lumped-Charge approach High-Voltage/high-current/picoampere PCB layout design

4 Recent Active collaborations ANSALDOBREDA Naples Italy STMicroelectronics Catania Italy Fairchild Munich Germany ECPE European Centre for Power Electronics Nuremberg - Germany INFN Italian Institute for Nuclear Physics Rome - Italy

5 The laboratory is an ECPE Competence Center specialized in non destructive testing of discrete and power modules

6 Non-Destructive Tester NDT Facility Tester control panel Features: High voltage Area Voltage: V (8000V) Current: A Applications: SOA Tests Sort circuit Unclamped Temperature Aging Principle Schematic

7 High Voltage NDT High voltage Devices: 1700V Vcc 6500V Ls = 110 nh Cs = 5nF

8 High Current NDT High current Devices: Ic 8000A Vcc 1700V Ls < 50 nh Cs = 12nF

9 Very Low Inductance NDT Very Fast Devices: Vcc 1700V, Ls < 30 nh, Cs < 300pF Detail of busbar

10 Temperature Characterization Railway inverter under test -50 C +200 C Special Fluid

11 Static Characterization Curve Tracer kV, 20A pulsed Agilent B1500A w/ 2 SMUs: High current and voltage junction BV High precision (pa) oxides percolation Ad hoc set-ups: high voltage and current, high precision (e.g. 3kV 1nA) Keithley Measurement System w/2 SMUs: High current and voltage 2410 High precision (pa) 2601

12 Post Failure Analysis Inspection microscope NISENE decapsulation system

13 Development of high voltage, high performances switch Marx modulator High voltage bridge leg For railway applications

14 Cosmic Ray effects on Power Devices

15 Single Event Burnout: Experiment

16 3-µm resolution Ion Impact Mapping

17

18 Operations of power devices in highly stressing electrical conditions C. Abbate, G. Busatto, F.Iannuzzo DIEI Università di Cassino e del Lazio Meridionale Via G. di Biasio, 43, Cassino, Italy busatto@unicas.it

19 Outline Introduction Failure mechanisms under extreme electrical stresses: In the device linear operating region During the device switching In avalanche conditions External causes (eg. cosmic rays impacts) Non destructive techniques for electrical testing of power devices The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities Cosmic rays impact Conclusions

20 A power device in a switching circuit Buck converter Test circuit Switch On Off

21 Switching Waveforms

22 Electrical limits of a power semiconductor switch Collector Voltage SOA Collector Voltage

23 Elementary cells of a Power MOSFET Double Diffused Planar Structure Trench Gate Structure

24 Power MOSFET parasitic BJT Source Emitter Gate Body Base N + P _ R P+ P + N _ A possible cause of failure! N + Drain Collector

25 IGBT (Insulated Gate Bipolar Transistor) Planar Structure Trench Gate Structure

26 IGBT (Insulated Gate Bipolar Transistor) Planar Structure Trench Gate Structure

27 IGBT parasitic thyristor A further possible cause of failure!

28 Outline Introduction Failure mechanisms under extreme electrical stresses: In the device linear operating region During the device switching In avalanche conditions External causes (eg. cosmic rays impacts) Non destructive techniques for electrical testing of power devices The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities Cosmic rays impact Conclusions

29 Failure mechanisms under extreme electrical stresses In the device linear operating region Short circuit operations (or overload conditions) Instable DC operations (second breakdown) During the device switching At the turn-off Reverse recovery of internal diode In avalanche conditions UIS Unclamped Inductive Switch

30 Type 1 Short circuit of a Power Switch: Definitions Type 1: Short circuit takes place when the device is in the off-state so it is turned on in short circuit Type 2: Short circuit takes place when the device is in the on-state Type 2

31 Type 1 short circuit Vgs Commercial devices can sustain S.C. for 10 ms at the T JMAX and with V GS =16V

32 The failure of a Power MOSFET after a short circuit Fresh Device After a short circuit Failure

33 Type 1 short circuit: First failure mechanism A.Ammous, K.Ammous, H.Morel, B.Allard, D. Bergogne, F. Sellami, J.P.Chante Electrothermal Modeling of IGBT s: Application to Short-Circuit Conditions, IEEE Trans. Power Electronics, Vol. 15, No. 4, JULY 2000

34 Type 1 short circuit: Second failure mechanism Device avalanching due to stray inductance

35 Type 2 short circuit Avalanche limit S.C. Device avalanching due to stray inductance can cause device failure H.G.Eckel, L.Sack, Experimental Investigation on the Behaviour of IGBT at Short-Ciruit during the On-State, Proc. IEEE PESC, 1995

36 Failure mechanisms under extreme electrical stresses In the device linear operating region Short circuit operations (or overload conditions) Instable DC operations (second breakdown) During the device switching At the turn-off Reverse recovery of internal diode In avalanche conditions UIS Unclamped Inductive Switch

37 Failure of Power Devices in the active region DC Safe Operating Area Second Breakdown

38 DC electro-thermal instability of a low voltage Power MOSFET Evolution of the temperature in the hot-spot P.Spirito, G.Breglio, V.d'Alessandro, N.Rinaldi, Analytical Model for Thermal Instability of Low Voltage Power MOS and S.O.A. in Pulse Operation, Proc. ISPSD 2002

39 Basic mechanism in thermal run-away Generated Power vs. Temperature I D Regenerative Thermo-electric Effect I D a T <0 Stable a T >0 Unstable

40 Trans-characteristics of a low voltage Power MOSFET V GS =Const a T I D T 0 Possible thermal run-away P.Spirito, G.Breglio, V.d Alessandro, Modeling the Onset of Thermal Instability in Low Voltage Power MOS: an Experimental Validation, Proc. ISPSD 2005

41 Experimental evidence of hot-spot formation Radiometric temperature detection for 55V Power MOSFET operated under pulsed bias conditions P.Spirito, G.Breglio, V.d Alessandro, Modeling the Onset of Thermal Instability in Low Voltage Power MOS: an Experimental Validation, Proc. ISPSD 2005

42 Failure mechanisms under extreme electrical stresses In the device linear operating region Short circuit operations (or overload conditions) Instable DC operations (second breakdown) During the device switching At the turn-off Reverse recovery of internal diode In avalanche conditions UIS Unclamped Inductive Switch

43 Second Breakdown in a BJT

44 3D structure of a Power BJT Typical top layout of a power BJT Sketch of the 3D structure of a power BJT

45 Crowding of emitter current Reverse Base Bias: central current crowding B.A.Betty, S. Krishna, M.S.Adler, Second Breakdown in Power Transistors Due to Avalanche Injection Trans. Electron Devices, Vol.ED-23, No.8, 1976

46 Second Breakdown in a BJT Avalanche injection Impact ionizzation At increasing Drain current

47 Second Breakdown in IGBT IGBT Modules rated at 3300V-1200A Vcc=1800V, Ic=4000A R ON =R OFF =0.35Ω L load =100µH T=145 C Second breakdown along the voltage rise

48 Internal structure of a power IGBT module I G1 I C1

49 Failure mechanisms under extreme electrical stresses In the device linear operating region Short circuit operations (or overload conditions) Instable DC operations (second breakdown) During the device switching At the turn-off Reverse recovery of internal diode In avalanche conditions UIS Unclamped Inductive Switch

50 Reverse Recovery of Power MOSFET internal diode Test circuito Experimental waveforms Second Breakdown

51 Parassitic BJT Activation Source Emitter Gate Body Base N + R P+ P + P _ Supplemental Charge N _ N + Drain Collector

52 The role of gate capacitance in the activation of parasitic BJT Displacement current

53 Phenomenon insight Displacem ent current 53

54 Failure mechanisms under extreme electrical stresses In the device linear operating region Short circuit operations (or overload conditions) Instable DC operations (second breakdown) During the device switching At the turn-off Reverse recovery of internal diode In avalanche conditions UIS Unclamped Inductive Switch

55 UIS Typical waveforms

56 Safe Unclamped Inductive Switch Test circuit Typical waveforms

57 Failure of Power MOSFET in Unclamped Inductive Switch UIS Failure Waveforms The gate is Off The current Is still flowing The voltage suddenly falls down A. Icaza-Deckelmann, G. Wachutka, J. Krumrey, F. Hirler, Failure Mechanism of Power DMOS Transistors under UIS Stress Conditions, ASDAM EDSSC 03

58 Failure of Power MOSFET in Unclamped Inductive Switch Low Drain Current Electric Field I h I h I e Avalanche multiplication I e

59 Failure of Power MOSFET in Unclamped Inductive Switch I e I h Maximum temperature in the device and currents at the source contact vs. time (I=1mA)

60 Failure of Power MOSFET in Unclamped Inductive Switch High Drain Current Electric Field I e I h Kirk Effect Avalanche multiplication

61 Experimental evidence of instability in UIS

62 Outline Introduction Failure mechanisms under extreme electrical stresses: In the device linear operating region During the device switching In avalanche conditions External causes (eg. cosmic rays impacts) Non destructive techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities Cosmic rays impact Conclusions

63 ND techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities

64 How a Non-Destructive tester can help in robustness validation tests? Collector Voltage RBSOA Collector Voltage

65 How a Non-Destructive tester can help in robustness validation tests? Failure Voltage Gate Resistance

66 ND techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities

67 The first non destructive tester proposed in the literature D.W. Berning: Semiconductor Measurement Technology: A programmable Reverse Bias Safe Operating Area transistor tester National Institute of Standard and Technology Special Publication , August 1990.

68 Basic schematic and principle of operation

69 The first non destructive tester proposed in the literature Tester performances: V Clamp,Max =2000V I C,Max =25,5A t CrowBar,on I CrowBar =40A t CrowBar,on I CrowBar =100A

70 Problems with vacuum tubes Current capabilities of vacuum tubes are quite poor and their use for collector currents larger than 50A is not practical Tubes are very expensive

71 A second version of ND tester G. Carpenter, F.C.Y. Lee, D.Y. Chen: An 1800-V 300-A N Nondestructive Tester for Bipolar Power Transistors IEEE Transaction on Power Electronics, vol.5, n 3, pp , 1990.

72 The MOSFET shunt circuit of the Carpenter non-destructive tester Tester performances: V Clamp,Max =1800V I C,Max =300A t CrowBar,d I CrowBar =300A t CrowBar,on I CrowBar =300A

73 Problems when using dv/dt sense to trigger the crow bar switch A delay time is observed which is sensitive to the output current value The methods to speed up the turn on of the power MOSFET cannot be easily extended to high power IGBTs when used as crow bar switches The instabilities of the power devices often are not accompanied by a sudden variation of the collector voltage Other techniques must be used for the activation of the Crow Bar switch!

74 ND techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities

75 Non Destructive Tester for High Power Modules V A U X 100V Q 1, 1 Series SW H.V. Power Supply V I N V C Q 1, 2 Q 1, 3 L L D 1 D 2 D 3 Q 2, 1 R 1 Q 2, 2 Q 2, 3 DUT Crow-Bar SW No dv/dt sense is used

76 Short circuit High temperature test

77 High voltage Unclamped tests

78 Tester Operations 1 0 Series SW state Crow bar SW state Series SW DUT state V IN C L L D 1 D 2 D 3 DUT Collector Voltage DUT DUT Collector Current Crow-Bar SW Crow bar Current T 0 T 1 T 2 T 3 T 4 Time

79 ND techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities

80 Jitter of the crow bar turn-on

81 Stray capacitance of the crowbar switch

82 The effect of the stray inductance on the crow-bar turn-on time

83 The effect of the crow-bar Reverse Bias Voltage Reverse Bias Voltage

84 Improved NDT

85 Other effects of stray inductances L S =110nH 3300V 1200A IGBT Module 600V 300A IGBT Module

86 Different typologies of non-destructive set-up High voltage IGBTs 1700V Vcc 6500V Ls = 110 nh High current IGBTs Vcc 1700V Ls < 50 nh

87 The stray inductance 600V 300A IGBT Module L S =110nH L S =50nH

88 Stray capacitance of the busbar Ls = 110 nh Ls < 50 nh C SBB = 5nF C SBB = 12nF

89 Stray capacitance of the busbar C SBB = 12nF 1200V 25A IGBT

90 Reduced busbar stray capacitance C SBB = 400pF

91 Reduction of the busbar stray capacitance C SBB = 12nF 1200V 25A IGBT C SBB = 400pF

92 A first conclusion about the tester characteristics High voltage IGBT modules (1700V V) Lower stray inductances Higher dumping capacitors Larger crow bar stray capacitance High current series and CB switch High capacitance dumping capacitor High voltage series and CB switch High voltage dumping capacitor Lower voltage IGBT modules (600V V) Lower current capabilities Higher stray inductances Lower crow bar stray capacitance

93 A first conclusion about the tester characteristics Discrete IGBT devices Lower current much faster CB switch Lower voltage more performing dumping capacitor Lower current capabilities Much lower stray inductances Lower stray busbar capacitance It is not possible to have one experimental set up good for any devices/modules Each phenomenon to be studied requires its specific experimental set-up

94 Example of Tester Operation Second breakdown Single chip MOS-GTO Clamped test on 1500V-10A D AUX and V NEG =50V V IN =1200V, Ic=19A, RG OFF =10Ω 80ns Collector current is zeroed Crow Bar activation DUT Saved

95 UIS Failure Second breakdown 60ns Unclamped test on 600V - 300A IGBT Modules by HC-UNDT V NEG =800V, RG OFF =15Ω Collector current is zeroed Crow Bar activation DUT Fails

96 UIS Failure 20ns 1 Unclamped Test JFET: Id=21A, Vav 1800V, L L =1.5mH tav 2.5µs Eav=51mJ Ts=25 C E SB 0.1mJ (Very low energy after failure)

97 Post Failure Analysis Very small damaged area Melted area between gate and source

98 Is it possible to save DUT in UIS? We cannot rely on dv/dt and di/dt Indicators!!!! Other precursors must be identified

99 Unclamped turn-off test Unclamped Turn-off: 1200V-400A Modules Precursor on the gate voltage Second Breakdown T CASE = 25 C Vav=1300V Ic=400A R OFF =3.3Ω L LOAD =50mH

100 Unclamped turn-off test Unclamped Turn-off: 1200V-400A Modules Precursor on the gate voltage T CASE = 25 C Vav=1300V Ic=400A R OFF =3.3Ω L LOAD =50mH

101 Unclamped turn-off test Unclamped Turn-off: 1200V-400A Modules R OFF =2.0W R OFF =3.3W T CASE = 25 C Second Breakdown Vav=1300V Ic=400A R OFF = 3.3 Ω 2.0 Ω L LOAD =50mH

102 OTHER USES OF PULSED POWER SUPPLY

103 Control of the energy in Avalanche Cycles (application to SiC JFETs) Automatic Tester Operation

104 Effects of Avalanche Cycles on SiC JFETs Failure during avalanche (400 cycles)

105 Effects of Avalanche Cycles on SiC JFETs Gate Leakage Drain Leakage

106 Effects of Avalanche Cycles on SiC JFETs Drain current Effect on drain leakage at fixed URS times (1.2us) and cycles (350).

107 Conclusions The Non Destructive Tester is a useful tool to test power semiconductor devices at the edges of the SOA It is not possible to use the same NDT for testing discrete devices and modules The NDT must be designed according to the characteristics of the device/modules to be tested The pulsed apparatus can be used for other applications In high current and in unclamped inductive turn-off a precursor on the waveform can be recognized that evidence instabilities taking place inside the device and can be used to save the sample under test

108 Outline Introduction Failure mechanisms under extreme electrical stresses: In the device linear operating region During the device switching In avalanche conditions External causes (eg. cosmic rays impacts) Non destructive techniques for electrical testing of power devices The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The precursors of the instabilities Conclusions Cosmic rays impact

109 Cosmic rays impact

110 Particle shower Galactic Cosmic Ray semiconductor failures induced by cosmic radiation are no longer [only] an aerospace problem. Such failure mechanisms must be accounted for in automotive electronics systems design. June 2006 Neutron flux at sea level is 10 5 neutrons/cm 2 -year with E>2 MeV which may cause SEE in electronics

111 Neutron induced Single Event Effects (SEE) A neutron interacts with a nucleus to produce a heavily ionizing secondary that then causes an anomalous macroscopic effect in a working electronic device

112 SEE irradiation experiments IRRADIATION SPECIES Protons Neutrons Heavy ions IRRADIATION FACILITIES INFN LNS Catania Tandem (Heavy ions) Ciclotrone (Protons) INFN LNL Legnaro Tandem (Heavy ions) ENEA Casaccia Roma Tapiro (Neutrons)

113 SEB in a Power Diode

114 Typical test circuit 1MW Ion be am DUT Vbias C i(t) 50W line 50W v(t)

115 Charge Amplification (2D Simulation) kV diode Biasing voltage: 1800V Impacting Ion: 12 C (17MeV) E-field[kV/cm] T=0 25ps 100ps 150ps 230ps 500ps 1ns Electrons-Density [cm ] Depth [ mm] P + N - N + G. Soelkner et al. Charge Carrier Avalanche Multiplication, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 47, NO. 6, DECEMBER 2000, pp

116 Diode Currente during a destructive impact Biasing Voltage: 2200V ns Current [A] Time [ns]

117 2D Simulation a SEB 400 4kV diode Biasing voltage: 2200V Impacting Ion: 12 C (17MeV) E-field[kV/cm] -3 E-Density [cm ] ps 25ps Depth [ mm] 25ps 50ps 75ps 100ps 125ps 75ps 100ps 125ps 300ps 150ps 150ps Depth [ mm]

118 A double injection like phenomenon E-field[kV/cm] High: Current density Carriers concentration Electric field E-Density [cm ] Depth [ mm] Impact ionization

119 SEE in Power MOSFET SEGR SEB

120 Test circuit GPIB Oscilloscope Computer for off-line statistical analysis

121 Single Event Burn-out

122 SEE in power mosfets Numerical simulation activity 3D finite element simulations are performed using the ATLAS TCAD simulation tool by Silvaco International. Q r,t N r t t R tc N e e t tc π erfc t LET 3.6 π R 0 2 pairs cm c R t 0 t C 0.124mm 4ps 2ps The simulated elementary cell with its lumped elements and the parameters used to simulate the ionizing track for a bromine ion at 230MeV.

123 SEE in power mosfets 3D numerical simulation Vds=60V Vds=100V (SEB) The role of the parasitic BJT in the charge generation mechanism.

124 SEE in power mosfets 3D numerical simulation The double injection phenomenon.

125 Double injection in Power MOSFET Electric Field [ V/cm ] 2.5 x Electric Field t=700ps x=9mm VDS=60V VDS=100V Hole Concentration [cm -3 ] 2.5 x Hole Concentration t=700ps x=9mm Vds=100V Vds=60V Distance [ mm ] Distance [ mm ] Impact ionizzation

126 SEE in gate oxide of Power MOSFET SEGR

127 Single Event Gate Rupture

128 A conceptual model for SEGR Ion track J. R. Brews, et. Al. A Conceptual model for SEGR in Power MOSFET s, IEEE TRANS. ON NUCLEAR SCIENCE, VOL. 40, NO. 6, DECEMBER 1993

129 SEB in IGBTs Emettitore Gate N + P _ P + N _ P + Collettore

130 SEB in IGBTs Emettitore Kathode Gate Gate N + P _ P + R P+ N _ P + Collettore Anode

131 2D simulation of SEB in IGBT W. Kaindl, et. Al. Cosmic Radiation-Induced Failure Mechanism of High Voltage IGBT, Proc. of the 17th ISPSD, May 23-26, 2005, Santa Barbara, CA

132 Thank You for Your attention DIEI Università di Cassino e del Lazio Meridionale Via G. di Biasio, 43, Cassino, Italy busatto@unicas.it