EE C247B ME C218 Introduction to MEMS Design Spring 2016

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1 EE C247B ME C218 Introduction to MEMS Design Spring 2016 Prof. Clark T.C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA Module 16: Sensing NonIdealities & Integration EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 1 Lecture Outline Reading: Senturia Chpt. 14, 15 Lecture Topics: Ideal Op Amps Op Amp NonIdealities MEMSTransistor Integration Mixed MEMSFirst MEMSLast Op Amp NonIdealities (cont.) EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 2 1

2 Ideal Operational Amplifiers EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 3 Ideal Op Amp Equivalent Circuit of an Ideal Op Amp: v 1 v 2 R in v i 1 0 v i 2 0 A v v Singleended output R 0 v 0 A v v A v 2 v 1 Differential input VoltageControlled Voltage Source (VCVS) Properties of Ideal Op Amps: R in R 0 0 A 4. i i EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/ v v, assuming v 0 finite Why? 2

3 Properties of Ideal Op Amps: R in R 0 0 A Ideal Op Amp (cont) i i v v 0, assuming v 0 finite Why? Because for v v v finite 0 v v 0 v v v 0 virtual short circuit (virtual ground) Big assumption! v finite 0 How can we assume this? We can assume this only when there is an appropriate negative feedback path! EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 5 Inverting Amplifier v i v R1 1 v i 0 OV Virtual ground i R 2 1. Verify that there is negative FB. v 2. node attached to () terminal is virtual 3. v0 finite v v ground. i 0 i i vi 0 vi i1 R R v 0 i R i 2 i R 2 v 0 EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 6 i 2 v i R2 R 1 1 v 0 Benefit: Any shunt C at this node will be grounded out. NOTE: Gain dependent only on R 1 & R 2 (external components), not on the op amp gain. R2 v0 vi R v i R R 2 1 3

4 Transresistance Amplifier Take R 1 away R 2 i 1 i 2 i i OV Virtual ground i 0 v 0 Again, shunt C at this node will be grounded out. 1. Verify that there is neg. FB yes, since same FB as inverting amplifier 2. Thus, v o = finite v = v () terminal is virtual ground 3. i = 0 i 1 = i 2 v v 0 R2 i 0 i2r2 iir2 i An inverting amplifier is just a transresistance amplifier with an R 1 to convert voltage to current! EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 7 IntegratorBased Diff. Position Sensing V P R 2 i o C F 1 R2 sc2 (for biasing) C 0 p v V P EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 8 4

5 NonIdeal Operational Amplifiers EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 9 Actual Op Amps Are Not Ideal Actual op amps, of course, are not ideal; rather, they Generate noise Have finite gain, A o Have finite bandwidth, b Have finite input resistance, R i Have finite input capacitance, C i Have finite output resistance, R o Have an offset voltage V OS between their () and () terminals Have input bias currents Have an offset I OS between the bias currents into the () and () terminals Have finite slew rate Have finite output swing (governed by the supply voltage used, L to L) And what s worse: All of the above can be temperature (or otherwise environmentally) dependent! EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

6 Finite Op Amp Gain and Bandwidth For an ideal op amp: A In reality, the gain is given by: For >> b : A0 A0 b T A( s) s b s s A j log 20 A 0 A0 As s 1 This pole actually designed in for some op amps. Openloop response of the amplifier. b Finite Gain Finite Bandwidth Integrator w/ time const. 1/ T 20dB/dec 3 db frequency Unity gain frequency: T A0 b b EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 11 T Effect of Finite Op Amp Gain V P Total ADXL50 Sense C ~ 100fF C p C gd Unity Gain Buffer v 0 V P EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

7 Integration of MEMS and Transistors EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 13 Integrate or Not? Benefits: Lower parasitic capacitance and resistance improved sensitivity and resolution, higher operation frequency Better reliability Reduced size lower cost? Reduced packaging complexity integration is a form of packaging lower cost? Higher integration density supports greater functionality Challenges: Temperature ceilings imposed by the transistors or MEMS Protecting one process from the other Surface topography of MEMS Material incompatibilities Multiplication of yield losses (versus nonintegrated) Acceptance by transistor foundries EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

250 nm CMOS CrossSection D D G S Sub 2 nd Level Metal Interconnect (e.g.

, Al) Polysilicon Gate LOCOS Oxidation TiSi 2 Contact Barrier P N P N P N N Well PMOS Substrate Silicon Substrate P P Well NMOS Substrate LPCVD

EEC247B/MEC218: Introduction to MEMS Design LecM 16 C.

8 250 nm CMOS CrossSection D D G S Sub 2 nd Level Metal Interconnect (e.g., Cu) S G D S G D G S Sub 1 st Level Metal Interconnect (e.g., Al) Polysilicon Gate LOCOS Oxidation TiSi 2 Contact Barrier P N P N P N N Well PMOS Substrate Silicon Substrate P P Well NMOS Substrate LPCVD SiO 2 CVD Tungsten TiN Local Interconnect Lightly Doped Drain (LDD) masks and and a lot lot more complicated than MEMS! EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 15 Merged MEMS/Transistor Technologies (Process Philosophy) MEMSLast: MEMSFirst: Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMSfirst or MEMSlast: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

EE 247B/ME 218: Introduction to MEMS Design Analog Devices BiMEMS Process Interleaved MEMS and 4 m BiMOS

MEMS poly stress anneal Used to manufacture the ADXL50 accelerometer and Analog Devices family of

Nguyen 4/21/15 17 Analog Devices BiMEMS Process (cont) Examples: Old New Analog Devices ADXL202 MultiAxis

9 EE 247B/ME 218: Introduction to MEMS Design Analog Devices BiMEMS Process Interleaved MEMS and 4 m BiMOS processes (28 masks) Diffused n runners used to interconnect MEMS & CMOS Relatively deep junctions allow for MEMS poly stress anneal Used to manufacture the ADXL50 accelerometer and Analog Devices family of accelerometers EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 17 Analog Devices BiMEMS Process (cont) Examples: Old New Analog Devices ADXL202 MultiAxis Accelerometer Analog Devices ADXL 78 Can you list the advances in the process from old to new? EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

10 Merged MEMS/Transistor Technologies (Process Philosophy) Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMSfirst or MEMSlast: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 19 MEMSFirst Integration Modular technology minimizes product updating effort Module 1: micromachining process (planar technology) Module 2: transistor process (planar IC technology) Adv.: (ideally) no changes needed to the transistor process Adv.: high temperature ceiling for some MEMS materials Challenges: Reducing topography after MEMS processing so transistors can be processed Maximizing the set of permissible MEMS materials; the materials must be able to withstand transistor processing temperatures Getting transistor foundries to accept preprocessed wafers EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

11 EE 247B/ME 218: Introduction to MEMS Design MEMSFirst Integration Problem: structural topography interferes with lithography difficult to apply photoresist for submicron circuits Soln.: build mechanics in a trench, then planarize before circuit processing [Smith et al, IEDM 95] EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 21 MEMSFirst Ex: Sandia s imems Used to demonstrate functional fully integrated oscillators Issues: lithography and etching may be difficult in trench may limit dimensions (not good for RF MEMS) mechanical material must stand up to IC temperatures (>1000oC) problem for some metal materials might be contamination issues for foundry IC s [Smith et al, IEDM 95] EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

Bosch/Stanford MEMSFirst Process Singlecrystal silicon microstructures sealed under epipoly encapsulation covers Many masking steps needed, but very stable structures EpiPoly Seal Resonator EpiPoly

Nguyen 4/21/15 23 Problems With MEMSFirst Many masking steps needed, plus CMP required cost can grow if you re not careful Processes using trenches sacrifice lithographic resolution in

12 Bosch/Stanford MEMSFirst Process Singlecrystal silicon microstructures sealed under epipoly encapsulation covers Many masking steps needed, but very stable structures EpiPoly Seal Resonator EpiPoly Cap Contact Substrate Episilicon for CMOS Transistor Circuits Vacuum Chamber [Kim, Kenny Trans 05] Mechanical Device EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 23 Problems With MEMSFirst Many masking steps needed, plus CMP required cost can grow if you re not careful Processes using trenches sacrifice lithographic resolution in microstructures MEMS must withstand transistor processing temperatures Precludes the use of structural materials with low temperature req mts: metals, polymers, etc. Exotic MEMS (e.g., ZnO) that can contaminate transistors during their processing are not permissible thus, not truly modular Foundry acceptance not guaranteed and might be rare EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

13 Foundry Acceptance of MEMSFirst? Is a CMP ed silicon surface sufficiently pure for fabrication of aggressively scaled transistors? How about if an oxide is grown over the CMP ed surface and removed via a wet etch to yield a pristine surface? Is epi silicon grown as part of a sealing process sufficiently pure for fabrication of aggressively scaled transistors? CMOS is many times more difficult to run than MEMS Feature sizes on the nm scale for billions of devices Contamination a big issue: many foundries may not accept preprocessed wafers for contamination reasons Many foundries will not accept any preprocessed wafers, MEMS or not just can t guarantee working transistor circuits with unknowns in starting silicon EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 25 Merged MEMS/Transistor Technologies (Process Philosophy) Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMSfirst or MEMSlast: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

14 MEMSLast Integration Modular technology minimizes product updating effort Module 1: transistor process (planar IC technology) Module 2: micromachining process (planar technology) Adv.: foundry friendly Virtually any foundry can be used can use the lowest cost transistor circuits (big advantage) Adv.: topography after circuit fabrication is quite small, especially given the use of CMP to planarize the metallization layers Issue: limited thermal budget limits the set of usable structural materials Metallization goes bad if temperature gets too high Aluminum grows hillocks and spikes junctions if T>500 o C Copper diffusion can be an issue at high temperature Lowk dielectrics used around metals may soon lower the temperature ceiling to only 320 o C EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 27 Berkeley Polysilicon MICS Process Uses surfacemicromachinedpolysilicon microstructures with silicon nitride layer between transistors & MEMS Polysilicon dep. T~600 o C; nitride dep. T~835 o C 1100 o C RTA stress anneal for 1 min. metal and junctions must withstand temperatures ~835 o C tungsten metallization used with TiSi 2 contact barriers in situ doped structural polysi; rapid thermal annealing EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

[Nguyen, Howe [Nguyen, Howe1993] 1993] To

15 EE 247B/ME 218: Introduction to MEMS Design Surface Micromachining Fabrication steps compatible with planar IC processing EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 29 SingleChip Ckt/MEMS Integration Completely monolithic, low phase noise, highq oscillator (effectively, an integrated crystal oscillator) Oscilloscope Output Waveform [Nguyen, Howe [Nguyen, Howe1993] 1993] To allow the use of >600oC processing temperatures, tungsten (instead of aluminum) is used for metallization EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

16 Usable MEMSLast Integration Problem: tungsten is not an accepted primary interconnect metal Challenge: retain conventional metallization minimize postcmos processing temperatures explore alternative structural materials (e.g., plated nickel, SiGe [Franke, Howe et al, MEMS 99]) Limited set of usable structural materials not the best situation, but workable EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 31 PolySiGe MICS Process MICS = Modular Integration of Circuits and Structures MEMSlast process, where SiGe micromechanics are planar processed directly above conventional foundry circuits enabled by lower deposition temperature of SiGe ~450 o C Adv.: alleviates contamination issues of precircuit processes, allowing a wider choice of IC technologies Shielded Interconnect to drive electrode PolySiGe MEMS 5Level Metal Foundry CMOS Shielded vertical signal path to gate of input transistor [Franke, Howe 2001] EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

Polysilicon Germanium Deposition LPCVD thermal decomposition of GeH 4 and SiH 4 or Si 2 H 6 Rate >50 Å/min, T < 475 C, P = 300600 mt At higher [Ge]: rate, T Insitu doping, ion implantation Dry

17 Polysilicon Germanium Deposition LPCVD thermal decomposition of GeH 4 and SiH 4 or Si 2 H 6 Rate >50 Å/min, T < 475 C, P = mt At higher [Ge]: rate, T Insitu doping, ion implantation Dry Etching Similar to polysi, use F, Cl, and Br containing plasmas Rate ~0.4 m/min Wet Etching H 2 O 90 o C: can get 4 orders of magnitude selectivity between >80% and <60% Ge content Good release etchant EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 33 PolySiGe Mechanical Properties Conformal deposition Low asdeposited stress (when its done right) Young s modulus ~ 146 GPa (for polysi 0.35 Ge 0.65 ) Density ~4280 kg/m 3 Acoustic velocity ~5840 m/s (25% lower than polysilicon) Harder to achieve high frequency devices Fracture strain 1.7% (compared to 1.5% for MUMPS polysi) Q=30,000 for ntype polyge in vacuum EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

30s) Transistor Circuits EEC247B/MEC218: Introduction to MEMS Design LecM 16 C.

18 UCB PolySiGe MICS Process 2 m standard CMOS process w/ Al metallization Ptype polysi 0.35 Ge 0.65 structural material; polyge sacrificial material Process: Passivate CMOS w/ 400 o C Open vias to interconnect runners Deposit & pattern ground plane RTA anneal to lower resistivity (550 o C, 30s) Transistor Circuits EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 35 ASIMPS Ckt/MEMS Integration Process MEMS constructed from metal/insulator laminates of foundry CMOS Top metal layer used as etch mask for CHF 3 /O 2 oxide etch Structures released via a final SF 6 isotropic dry etch Independent electrostatic actuation possible due to multiple insulated metal layers Stress issues can be tricky Must design defensively against warping Metal/insulator stack [G. Fedder, CMU] EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

ASIMPS Ckt/MEMS Integration Process Direct integration of Al/oxide MEMS structure with silicon CMOS or SiGe BiCMOS circuits Multiple electrodes within structures Derivatives for

Fedder, CMU] Uncooled IR Detector Element EEC247B/MEC218: Introduction to MEMS Design LecM 16 C.

resistance, R i Have finite input capacitance, C i Have finite output resistance, R o Have an offset voltage V OS between their () and () terminals Have input bias currents Have an

19 ASIMPS Ckt/MEMS Integration Process Direct integration of Al/oxide MEMS structure with silicon CMOS or SiGe BiCMOS circuits Multiple electrodes within structures Derivatives for bulk silicon structures Composite Beam Gyro Resonator CMOS Transistor Etched Pit Silicon Substrate Stator Electrodes [G. Fedder, CMU] Uncooled IR Detector Element EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 37 Actual Op Amps Are Not Ideal Actual op amps, of course, are not ideal; rather, they Generate noise Have finite gain, A o Have finite bandwidth, b Have finite input resistance, R i Have finite input capacitance, C i Have finite output resistance, R o Have an offset voltage V OS between their () and () terminals Have input bias currents Have an offset I OS between the bias currents into the () and () terminals Have finite slew rate Have finite output swing (governed by the supply voltage used, L to L) And what s worse: All of the above can be temperature (or otherwise environmentally) dependent! EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

20 Finite Op Amp Gain and Bandwidth For an ideal op amp: A In reality, the gain is given by: For >> b : A0 A0 b T A( s) s b s s A j log 20 A 0 A0 As s 1 This pole actually designed in for some op amps. Openloop response of the amplifier. b Finite Gain Finite Bandwidth Integrator w/ time const. 1/ T 20dB/dec 3 db frequency Unity gain frequency: T A0 b b EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 39 T Op Amp NonIdealities Op Amp NonIdealities R i & R 0 Input resistance R i and Output Resistance R 0 : With finite R i and R 0, and finite gain and BW, the op amp equivalent circuit becomes: v v () R i A v R 0 C 0 v v v 0 Basically reduces down to a voltageamplifier model Add an output C0 to model a single pole response, where 1 w b R C 0 0 EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

21 Back to Op Amp NonIdealities EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 41 Input Offset Voltage V 0S Input Offset Voltage, V 0S: v 0 A v v Ideal case: Reality: v 0 0 v0 0 (usually, v0 L or L : it rails out!) Why? Internal mismatches within the op amp cause a dc offset. Model this with an equivalent input offset voltage V 0S. v 0 Typically, V 0S = 1mV 5mV V 0S EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

22 Effect of V 0S on Op Amp Circuits Example: NonInverting Amplifier R 2 R 1 V 0 S R 2 V 0 V0S 1 R 1 R2 e.g., 9, V0 S 5mV V0 50mV R 1 (not so bad ) EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/15 43 Effect of V 0S on Op Amp Circuits (cont.) Example: v 0 Integrator R i 1 V 0S V 0S R f v C C To fix this, place a resistor in shunt with the C then: R v V 1 f 0 0S R 1 t v V S i dt C t V0 S V0 S dt C 0 R t V0 S 1 v RC C t0 Will continue to increase until op amp saturates t EEC247B/MEC218: Introduction to MEMS Design LecM 16 C. Nguyen 4/21/

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 7: Noise &