PS21265-P/AP TRANSFER-MOLD TYPE TYPE INSULATED TYPE TYPE
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1 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Power Module> TYPE TYPE PS21265 INTEGRTED POWER FUNCTIONS 600/20 low-loss 5 th generation IGBT inverter bridge for three phase DC-to-C power conversion INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (U) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a U fault (Lower-side supply). Input interface : 3, 5 line compatible. (High ctive) UL pproved : Yellow Card No. E80276 PPLICTION C100~200 three-phase inverter drive for small power motor control. Fig. 1 PCKGE OUTLINES (Short-pin type : PS21265-P) (=75.6) 2.8± Type name, Lot No. 2-φ4.5± ±0.5 31±0.5 Refer Fig. 6 for long-pin type : PS21265-P. 34.9± ± ±0.5 D Heat sink side (11.5) (8.5) 28±0.5 NOTE TERMINL CODE 1. UP 2. P1 3. UFB 4. UFS 5. P 6. P1 7. FB 8. FS 9. WP 10. P1 11. PC 12. WFB 13. WFS Dimensions in mm 14. N1 15. NC CFO 18. FO 19. UN 20. N 21. WN 22. P 23. U W 26. N ±0.3 10±0.3 10±0.3 20± ±0.2 67± ±0.2 79±0.5 B (71) C Heat sink side 8± ±0.5 1±0.2 (2.5) Irregular solder remains 0.5MX C0.2 1± ± ±0.2 C0.2 OTHERS TERMINL 22, 26 DETIL B (5 pins t = 0.7) 0.6± ±0.2 Irregular solder remains 0.5MX 0.45± ± ± ±0.2 OTHERS TERMINL 1-2, DETIL C (21 pins t = 0.7) 0.6± ±0.2 DETIL (0 ~ 5 ) DETIL D Note: ll outer lead terminals are with Pb-free solder plating.
2 Fig. 2 INTERNL FUNCTIONS BLOCK DIGRM (TYPICL PPLICTION EXMPLE) C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system.) C2 : 0.22~2µF R-category ceramic capacitor for noise filtering Inrush current limiter circuit P High-side input (PWM) (3, 5 line) (Note 1, 2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (U) Protection circuit (U) Protection circuit (U) Drive circuit Drive circuit Drive circuit CBU CBU+ CBW+ CBW CB+ CB C2 (Note 7) C1 (Note 6) C line input Z Z : ZNR (Surge absorber) C : C filter (Ceramic capacitor 2.2~6.5nF) (Note : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment.) C NC Low-side input (PWM) (3, 5 line) (Note 1, 2) (Note 4) N1 Drive circuit Input signal conditioning Fo logic Protection circuit FO N CFO Fault output (5 line) (Note 3, 5) Control supply Under-oltage protection H-side IGBTS U W L-side IGBTS NC D (15 line) Note1: The logic of input signal is high-active. The input signal section integrates a 2.5kΩ(min) pull-down resistor. If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. 2: By virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3: This output is open drain type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. 4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P & N1 DC power input pins. 5: Fo output pulse width should be decided by putting external capacitor between CFO and NC terminals. (Example : CFO=22nF tfo=1.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. 7: To prevent ICS from surge destruction, it is recommended to insert a Zener diode (24, 1W) between each control supply terminals. (Note 7) M C line output Fig. 3 EXTERNL PRT OF THE PROTECTION CIRCUIT P Drive circuit Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC () H-side IGBTS U W SC Protection Trip Level External protection circuit L-side IGBTS N1 Shunt Resistor N (Note 1) NC C R Drive circuit B Protection circuit C (Note 2) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, C should be as short as possible. 0 Collector current waveform 2 tw ()
3 MXIMUM RTINGS (Tj = 25 C, unless otherwise noted) INERTER PRT Symbol Parameter Ratings Unit CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature pplied between P-N pplied between P-N TC = 25 C TC = 25 C, less than 1ms TC = 25 C, per 1 chip (Note 1) ~+125 Note 1 : The maximum junction temperature rating of the power chips integrated within the is 150 C (@ TC 100 C) however, to insure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 C (@ TC 100 C). W C CONTROL (PROTECTION) PRT Symbol Parameter Ratings Unit D DB IN FO IFO SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between P1-PC, N1-NC pplied between UFB-UFS, FB-FS, WFB-WFS pplied between UP, P, WP-PC, UN, N, WN-NC pplied between FO-NC Sink current at FO terminal pplied between -NC ~D ~D ~D+0.5 TOTL SYSTEM Symbol Parameter Ratings Unit Self protection supply voltage limit D = 13.5~16.5, Inverter part CC(PROT) Tj = 125 C, non-repetitive, less than 2 (short circuit protection capability) TC Module case operation temperature (Note 2) C Tstg iso Storage temperature Isolation voltage Note 2 : TC measurement point Control terminals 60Hz, Sinusoidal, C 1 minute, connecting pins to heat-sink plate ~ ~ C rms Heat sink TC TC Heat sink boundary Power terminals
4 THERML RESISTNCE Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f)F Parameter Junction to case thermal resistance (Note 3) Contact thermal resistance Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Case to fin (per 1 module) thermal grease applied Note 3 : Grease with good thermal conductivity should be applied evenly with a thickness of about +100µm~+200µm on the contact surface of and heat-sink. Min. Limits Typ. Max Unit C/W C/W C/W ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PRT CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current D = DB = 15 IC = 20, Tj = 25 C IN = 5 IC = 20, Tj = 125 C Tj = 25 C, IC = 20, IN = 0 CC = 300, D = DB = 15 IC = 20, Tj = 125 C, IN = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 125 C Limits Min. Typ. Max Unit CONTROL (PROTECTION) PRT Symbol ID FOH FOL SC(ref) IIN UDBt UDBr UDt UDr tfo th(on) th(off) Circuit current Parameter Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage D = DB = 15 IN = 5 D = DB = 15 IN = 0 Total of P1-PC, N1-NC UFB-UFS, FB-FS, WFB-WFS Total of P1-PC, N1-NC UFB-UFS, FB-FS, WFB-WFS SC = 0, FO circuit pull-up to 5 with 10kΩ SC = 1, IFO = 1 TC = 20~100 C, D = 15 (Note 4) IN = 5 Trip level Reset level Tj 125 C Trip level Reset level CFO = 22nF (Note 5) pplied between UP, P, WP-PC, UN, N, WN-NC Limits Min. Typ. Max Note 4 : Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the collector current rating (20). 5:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tfo depends on the capacitance value of CFO according to the following approximate equation : CFO = tfo [F]. Unit ms
5 MECHNICL CHRCTERISTICS ND RTINGS Mounting torque Weight Heat-sink flatness Note 6 : Parameter Mounting screw : M4 Recommended : 1.18 N m (Note 6) Min Limits Typ. 54 Max Unit N m g µm + Measurement point 3mm Heat sink Place to contact a heat sink + Heat sink RECOMMENDED OPERTION CONDITIONS CC D DB D, DB tdead fpwm IO Symbol PWIN(on) PWIN(off) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation rm shoot-through blocking time PWM input frequency llowable r.m.s. current Minimum input pulse width pplied between P-N pplied between P1-PC, N1-NC pplied between UFB-UFS, FB-FS, WFB-WFS For each input signal, TC 100 C TC 100 C, Tj 125 C CC = 300, D = DB = 15, fpwm = 5kHz P.F = 0.8, sinusoidal PWM fpwm = 15kHz TC 100 C, Tj 125 C (Note 7) (Note 8) 200 CC 350, 13.5 D 16.5, 13.0 DB 18.5, 20 C TC 100 C, N-line wiring inductance less than 10nH (Note 9) Below rated current Between rated current and 1.7 times of rated current Between 1.7 times and 2.0 times of rated current Recommended value Min. Typ. Max. NC NC variation between NC-N (including surge) Note 7 : The llowable r.m.s. current value depends on the actual application conditions. 8:Input signal with ON pulse width less than PWIN(on) might make no response. 9:IPM might make no response or response delay to next turn-on pulse if off-pulse width is less than PWIN(off). (Please refer to Fig. 4) Please refer to Fig. 9 for recommended wiring method too Unit / khz rms
6 Fig. 4 CURRENT OUTPUT WHEN INPUT SIGNL IS LESS THN LLOWBLE MINIMUM INPUT PULSE WIDTH PWIN(off) (P-side only) P-side control input Internal IGBT gate Output current Ic t2 t1 Real line... off pulse width > PWIN(off) ; turn on time t1 Broken line... off pulse width < PWIN(off) ; turn on time t2 Fig. 5 THE INTERNL CIRCUIT UFB UFS P1 HIC1 CC B IGBT1 Di1 P UP IN HO COM S U FB FS P1 HIC2 CC B IGBT2 Di2 P IN HO COM S WFB WFS P1 HIC3 CC B IGBT3 Di3 WP IN HO PC COM S W LIC IGBT4 Di4 UOUT N1 CC IGBT5 Di5 OUT UN N UN N WOUT IGBT6 Di6 WN WN Fo Fo NO NC GND CFO N CFO
7 Fig. 6 PCKGE OUTLINES (Long-pin type : PS21265-P) Irregular solder remains 0.5MX Irregular solder remains 0.5MX 1 ±0.2 (0.7) 1 ± ± ± ±0.2 (0.6) 0.8 ± ± ± ± ± ± ±0.5 (1) (1) C0.2 C0.2 Type name, Lot No B C (2.5) 1 (0 ~ 5 ) 8±0.5 Heat sink side Heat sink side OTHERS TERMINL 22, 26 OTHERS DETIL B (5 pins t = 0.7) TERMINL 1-2, DETIL C (21 pins t = 0.7) 11.5±0.5 16±0.5 31±0.5 (8.5) (11.5) 28±0.5 2-φ4.5± (=75.6) 2.8± ±0.3 79±0.5 (71) DETIL 0.5±0.2 DETIL D D TERMINL CODE 1. UP 2. P1 3. UFB 4. UFS 5. P 6. P1 7. FB 8. FS 9. WP 10. P1 11. PC 12. WFB 13. WFS 14. N1 15. NC CFO 18. FO 19. UN 20. N 21. WN 22. P 23. U W 26. N 13.4± ±0.5 10±0.3 10±0.3 10±0.3 20±0.3 NOTE 35± ±0.2 Note: ll outer lead terminals are with Pb-free solder plating.
8 Fig. 7 TIMING CHRTS OF THE PROTECTIE FUNCTIONS [] Short-Circuit Protection (Lower-arms only) (with external shunt resistor and CR connection) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input L : IGBT OFF state. a7. Input H : IGBT ON state, but during the FO signal active period the IGBT doesn t turn ON. a8. IGBT OFF in spite of H input. Lower-arms control input a6 a7 Protection circuit state SET RESET Internal IGBT gate a2 a3 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistance Error output Fo a5 SC reference voltage CR circuit time constant DELY [B] Under-oltage Protection (Lower-arm, UD) b1. Control supply voltage rises : fter the voltage reaches UDr level, the circuits start to operate when the next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. The minimum pulse width of FO is set by the external capacitor CFO, and FO outputs continuously during U period. b6. Under voltage reset (UDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET Control supply voltage D UDr b1 UDt b3 b6 b2 b4 b7 Output current Ic Error output Fo b5
9 [C] Under-oltage Protection (Upper-arm, UDB) c1. Control supply voltage rises : Operation starts soon after UDBr. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UDBt). c4. IGBT OFF in spite of control input condition, but there is no FO signal output. c5. Under voltage reset (UDBr). c6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET Control supply voltage DB UDBr c1 UDBt c4 c6 Output current Ic c2 c3 c5 c7 Error output Fo High-level (no fault output) Fig. 8 RECOMMENDED MCU I/O INTERFCE CIRCUIT 5 line 10kΩ UP,P,WP,UN,N,WN MCU Fo NC(Logic) Note : RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application s printed circuit board. The input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, if using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. Fig. 9 RECOMMENDED WIRING OF SHUNT RESISTOR Wiring inductance should be less than 10nH. width=3mm, thickness=100µm, length=17mm in copper pattern (rough standard) NC N Shunt resistor Please make the connection point as close as possible to the terminal of shunt resistor.
10 Fig. 10 EXMPLE OF TYPICL PPLICTION CIRCUIT C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering. (Note: The capacitance value depends on the PWM control used in the applied system.) C3 C2 C1 UFB UFS P1 UP HIC1 CC B IN HO P C2 C1 FB FS COM S U C3 P1 P HIC2 CC B IN HO CONTROLLER C3 C3 C2 C1 WFB WFS P1 WP PC N1 COM S HIC3 CC B IN HO COM S LIC UOUT CC W M 5 line OUT 15 line UN N WN Fo NC UN N WN Fo GND WOUT NO CFO The long wiring of GND might generate noise on input and cause IGBT to be malfunction. CFO C4(CFO) C5 B R1 N C Shunt Resistor If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. If this wiring is too long, short circuit might be caused. N1 Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2-3cm) 2:By virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open drain type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. 4:FO output pulse width is determined by the external capacitor between CFO and NC terminals (CFO). (Example : CFO = 22nF tfo = 1.8ms (typ.)) 5:The logic of input signal is high-active. The input signal section integrates a 2.5kΩ (min) pull-down resistor. If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement. 6:To prevent malfunction of protection, the wiring of, B, C should be as short as possible. 7:Please set the R1C5 time constant in the range 1.5~2. 8:Each capacitor should be located as nearby the pins of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. pproximately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended. 10 : To prevent ICS from surge destruction, it is recommended to insert a Zener diode (24, 1W) between each control supply terminals.
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Powerex, Inc., 173 Pavilion Lane, Youngwood, Pennsylvania 15697 (724) 925-7272 Dual-In-Line Intelligent Power Module J K Q V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 29 41 42 B M (2 PLACES) L (5
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Single-In-Line Intelligent Power Module A D G H J K L M N P C W X E 35 34 33 32 31 30 Y V (2 PLACES) F PS21661-RZ AA AK AJ Z B 1 3 2 5 4 7 6 9 8 11 3 12 15 14 17 16 19 18 21 25 26 27 28 20 22 23 24 29
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Dual-In-Line Intelligent Power Module A D DUMMY PINS K H L Q R C B 28 27 29 30 26 25 24 23 22 21 20 19 18 17 16 15 14 13 LABEL E E E F 12 11 10 9 8 F 7 6 5 4 3 2 1 M C L P 35 HEATSINK SIDE 35 34 33 32
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MITSUBISHI TELLIGET POWER MODULES SULATED PACKAGE D R - DIA. (4 TYP.) E H U V J 12 A B 34 7 5 6 8 9 11 13 15 17 19 T (15 TYP.) Q (4 TYP.) 10 12 14 16 18 U V P B W L M M M M M G 6.0 ± 0.1 X 0.8 ± 0.1 MM
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