PS21869-P/AP PS21869-P/AP. APPLICATION AC100V~200V inverter drive for small power motor control. PS21869

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1 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Power Module> TYPE TYPE PS21869 INTEGRTED POWER FUNCTIONS 600/50 CSTBT inverter bridge for three phase DC-to-C power conversion INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (U) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a U fault (Lower-side supply). Input interface : 3, 5 line CMOS/TTL compatible. (High ctive) UL pproved : Yellow Card No. E80276 PPLICTION C100~200 inverter drive for small power motor control. Fig. 1 PCKGE OUTLINES (Short-pin type : PS21869-P) Refer Fig. 6 for long-pin type : PS21869-P. Dimensions in mm TERMINL CODE (4.5) (3.1) 2-φ4.5±0.2 (4.65) (3.5) (0.6) (2) ± ± Type name, Lot No ±0.3 10± (=75.6) (8.5)(2.4) (14.4) (2.5) (17.6) (2.4) 10±0.3 67±0.3 79±0.5 20± (1) (4.65) (3.5) (2.9) (10) (0.6) (2) 11.5±0.5 31± ± ± ±0.5 (11) (10) C (2.2) 1 MIN D ±0.2 D HET SINK SIDE 1. UP 2. P1 3. UFB 4. UFS 5. P 6. P1 7. FB 8. FS 9. WP 10. P1 11. PC 12. WFB 13. WFS 14. N1 15. NC CFO 18. FO 19. UN 20. N 21. WN 22. P 23. U W 26. N DUMMY TERMINL CODE 27. PC 28. UPG 29. P 30. PC 31. PG 32. U 33. WPG UNG 36. NC 37. NO 38. WNG 39. NG 40. W 41. P D (0 ~ 5 ) B HET SINK SIDE 7±0.5 D 12.8±0.5 1±0.2 Irregular solder remains 0.5MX C0.2 1± ± ± ±0.2 C ±0.5 Irregular solder remains 0.5MX 0.8± ± ± ± ±0.2 (3.8) 1MIN (2.5) TERMINL 22, 26 OTHER TERMINL TERMINL 1-2, OTHER TERMINL DETIL (5 pins t = 0.7) DETIL B (21 pins t = 0.7) DETIL D (5 parts) 1.6± MIN DETIL C (2 parts) ll outer lead terminals are with Pb-free solder (Sn-Cu) plating.

2 Fig. 2 INTERNL FUNCTIONS BLOCK DIGRM (TYPICL PPLICTION EXMPLE) C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit P High-side input (PWM) (3, 5 line) (Note 1, 2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (U) Protection circuit (U) Protection circuit (U) Drive circuit Drive circuit Drive circuit CBU CBU+ CBW+ CBW CB+ CB C2 (Note 7) C1 (Note 6) C line input Z Z : ZNR (Surge absorber) C : C filter (Ceramic capacitor 2.2~6.5nF) (Note : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). C NC Low-side input (PWM) (3, 5 line) (Note 1, 2) (Note 4) Fig. 3 N1 Drive circuit Input signal conditioning Fo logic Protection circuit FO N CFO Fault output (5 line) (Note 3, 5) Control supply Under-oltage protection H-side IGBTS U W L-side IGBTS NC D (15 line) Note1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. 2: By virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 10) 3: This output is open drain type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistance. (see also Fig. 10) 4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P-N1 DC power input pins. 5: Fo output pulse width should be decided by putting external capacitor between CFO and NC terminals. (Example : CFO=22nF tfo=1.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. 7: It is recommended to insert a Zener diode (24/1W) nearby each pair of supply terminals to prevent surge destruction. (Note 7) M C line output Fig. 3 EXTERNL PRT OF THE PROTECTION CIRCUIT P Drive circuit Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC () H-side IGBTS U W SC Protection Trip Level External protection circuit L-side IGBTS N1 Shunt Resistor N (Note 1) NC C R Drive circuit B Protection circuit C (Note 2) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, C should be as short as possible. 0 Collector current waveform 2 tw ()

3 MXIMUM RTINGS (Tj = 25 C, unless otherwise noted) INERTER PRT Symbol Parameter Ratings Unit CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature pplied between P-N pplied between P-N Tf = 25 C Tf = 25 C, less than 1ms Tf = 25 C, per 1 chip (Note 1) ~+125 Note 1 : The maximum junction temperature rating of the power chips integrated within the is 150 C (@ Tf 100 C) however, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 C (@ Tf 100 C). W C CONTROL (PROTECTION) PRT Symbol Parameter Ratings Unit D DB IN FO IFO SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between P1-PC, N1-NC pplied between UFB-UFS, FB-FS, WFB-WFS pplied between UP, P, WP-PC, UN, N, WN-NC pplied between FO-NC Sink current at FO terminal pplied between -NC ~D ~D ~D+0.5 TOTL SYSTEM Symbol Parameter Ratings Unit Self protection supply voltage limit D = 13.5~16.5, Inverter part CC(PROT) Tj = 125 C, non-repetitive, less than 2 (short circuit protection capability) Tf Module case operation temperature (Note 2) C Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, C 1 minute, connection pins to heat-sink plate ~ ~ C rms Note 2 : Tf measurement point l Board Specification : Dimensions : mm, Finishing : 12s, Warp : 50~100µm Control Terminals Groove 18mm I board 13.5mm P U W N Power Terminals FWDi Chip IGBT Chip Temp. measurement point (inside the I board) Temp. measurement point (inside the I board) Silicon-grease should be applied evenly with a thickness of 100~200µm

4 THERML RESISTNCE Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction to case thermal resistance (Note 3) Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of and heat-sink. Min. Limits Typ. Max Unit C/W C/W ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PRT CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current D = DB = 15 IC = 50, Tj = 25 C IN = 5 IC = 50, Tj = 125 C Tj = 25 C, IC = 50, IN = 0 CC = 300, D = DB = 15 IC = 50, Tj = 125 C, IN = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 125 C Limits Min. Typ. Max Unit CONTROL (PROTECTION) PRT Symbol ID FOH FOL SC(ref) IIN UDBt UDBr UDt UDr tfo th(on) th(off) Circuit current Parameter Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage D = DB = 15 IN = 5 D = DB = 15 IN = 0 Total of P1-PC, N1-NC UFB-UFS, FB-FS, WFB-WFS Total of P1-PC, N1-NC UFB-UFS, FB-FS, WFB-WFS SC = 0, FO circuit pull-up to 5 with 10kΩ SC = 1, IFO = 1 Tf = 20~100 C, D = 15 (Note 4) IN = 5 Trip level Tj 125 C Reset level Trip level Reset level CFO = 22nF (Note 5) pplied between UP, P, WP-PC, UN, N, WN-NC Limits Min. Typ. Max Note 4 : Short circuit protection is functioning only for the low-arms. Please select the external shunt resistor such that the SC trip-level is less than 2.0 times of the current ratings. 5:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse width tfo depends on the capacitance value of CFO according to the following approximate equation : CFO = tfo [F]. Unit ms

5 MECHNICL CHRCTERISTICS ND RTINGS Mounting torque Weight Heat-sink flatness Parameter Mounting screw : M4 Recommended : 1.18 N m (Note 6) Min Limits Typ. 65 Max Unit N m g µm Note 6 : Measurement point of heat-sink flatness + Measurement location 3mm Heat-sink side + Heat-sink side RECOMMENDED OPERTION CONDITIONS CC D DB D, DB tdead fpwm IO Symbol PWIN(on) PWIN(off) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation rm shoot-through blocking time PWM input frequency llowable r.m.s. current llowable minimum input pulse width pplied between P-N pplied between P1-PC, N1-NC pplied between UFB-UFS, FB-FS, WFB-WFS For each input signal, Tf 100 C Tf 100 C, Tj 125 C CC = 300, D = DB = 15, P.F = 0.8, sinusoidal output Tf 100 C, Tj 125 C (Note 7) 200 CC 350, 13.5 D 16.5, 13.0 DB 18.5, 20 C Tf 100 C, N-line wiring inductance less than 10nH (Note 9) fpwm = 5kHz fpwm = 15kHz (Note 8) Below rated current Between rated current and 1.7 times of rated current Between 1.7 times and 2.0 times of rated current Recommended value Min. Typ. Max. NC NC variation between NC-N (including surge) Note 7 : The allowable r.m.s. current value depends on the actual application conditions. 8:The input pulse width less than PWIN(on) might make no response. 9:IPM might make delayed response (less than 2ec) or no response for the input signal with off pulse width less than PWIN(off). Please refer Fig. 4 for details Unit / khz rms

6 Fig. 4 CURRENT OUTPUT WHEN INPUT SIGNL IS LESS THN LLOWBLE MINIMUM INPUT PULSE WITH PWIN(off) (P-side only) P-side control input Internal IGBT gate Output current Ic t2 t1 Real line... off pulse width > PWIN(off) : turn on time t1 Broken line... off pulse width < PWIN(off) : turn on time t2 Fig. 5 THE INTERNL CIRCUIT UFB UFS P1 HIC1 CC B IGBT1 Di1 P UP IN HO COM S U FB FS P1 HIC2 CC B IGBT2 Di2 P IN HO COM S WFB WFS P1 HIC3 CC B IGBT3 Di3 WP IN HO PC COM S W LIC IGBT4 Di4 UOUT N1 CC IGBT5 Di5 OUT UN N UN N WOUT IGBT6 Di6 WN WN Fo Fo NO NC GND CFO N CFO

7 Fig. 6 PCKGE OUTLINES (Long-pin type : PS21869-P) 0.7MIN 1 2-φ4.5 ± Type name, Lot No (0.6) (2) 8.5±0.3 10± ±0.3 10± ± ±0.3 TERMINL CODE 1. UP 2. P1 3. UFB 4. UFS 5. P 6. P1 7. FB 8. FS 9. WP 10. P1 11. PC 12. WFB 13. WFS 14. N1 15. NC CFO 18. FO 19. UN 20. N 21. WN 22. P 23. U W 26. N DUMMY TERMINL CODE 27. PC 28. UPG 29. P 30. PC 31. PG 32. U 33. WPG UNG 36. NC 37. NO 38. WNG 39. NG 40. W 41. P 1 ±0.2 (0.7) 0.8 ±0.2 (0.6) (3.8) (1) 1MIN Irregular solder remains 0.5MX 1.6 ±0.5 Irregular solder remains 0.5MX 1 ± ± ± ± ± ± ± ±0.2 C0.2 C0.2 (2.5) TERMINL 22, 26 OTHER TERMINL TERMINL 1-2, OTHER TERMINL DETIL (5 pins t = 0.7) DETIL B (21 pins t = 0.7) DETIL D (5 parts) (0 ~ 5 ) 1.6 ±0.5 (1) B HET SINK SIDE D D C (2.2) D HET SINK SIDE 1 MIN D ±0.2 7 ±0.5 (4.65) (3.5) (2.9) (10) (1) 11.5 ± ± ± ±0.6 (11) (10) 21.4 ±0.5 (0.6) (2) (=75.6) 2.8 ±0.3 (8.5)(2.4) (14.4) (2.5) (17.6) (2.4) 79 ±0.5 (3.5) (4.65) (4.5) (3.1) 16 ±0.5 DETIL C (2 parts)

8 Fig. 7 TIMING CHRTS OF THE PROTECTIE FUNCTIONS [] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input L : IGBT OFF. a7. Input H : IGBT ON. a8. IGBT OFF in spite of input H. Lower-arms control input a6 a7 Protection circuit state SET RESET Internal IGBT gate a2 a3 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistor Error output Fo a5 SC reference voltage CR circuit time constant DELY [B] Under-oltage Protection (Lower-arm, UD) b1. Control supply voltage rises : fter the voltage level reaches UDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET Control supply voltage D UDr b1 UDt b3 b6 b2 b4 b7 Output current Ic Error output Fo b5

9 [C] Under-oltage Protection (Upper-arm, UDB) c1. Control supply voltage rises : Operation starts soon after UDBr. c2. Protection circuit state reset : IGBT ON : Currents output. c3. Normal operation : IGBT ON and carrying current. c4. Under voltage trip (UDBt). c5. IGBT OFF in spite of control input condition, but there is no FO signal output. c6. Under voltage reset (UDBr). c7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET Control supply voltage DB UDBr c1 UDBt c4 c6 Output current Ic c2 c3 c5 c7 Error output Fo High-level (no fault output) Fig. 8 RECOMMENDED CPU I/O INTERFCE CIRCUIT 5 line 10kΩ UP,P,WP,UN,N,WN MCU Fo NC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application s printed circuit board. The input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. Fig. 9 WIRING CONNECTION OF SHUNT RESISTOR Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern with length=17mm, width=3mm, and thickness=100µm NC N Shunt resistor Please make the GND wiring connection of shunt resistor to the NC terminal as close as possible.

10 Fig. 10 TYPICL PPLICTION CIRCUIT EXMPLE C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering. C3 C2 C1 UFB UFS P1 UP HIC1 CC B IN HO P C2 C1 FB FS COM S U C3 P1 P HIC2 CC B IN HO CONTROLLER C3 C3 C2 C1 WFB WFS P1 WP PC N1 COM S HIC3 CC B IN HO COM S LIC UOUT CC W M 5 line OUT 15 line UN N WN Fo NC UN N WN Fo GND WOUT NO CFO Long GND wiring here might generate noise to input and cause IGBT malfunction. CFO C4(CFO) C5 B R1 N Too long wiring here might cause short-circuit. C Shunt Resistor If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. N1 Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm) 2:By virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open drain type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. 4:FO output pulse width is determined by the external capacitor between CFO and NC terminals (CFO). (Example : CFO = 22nF tfo = 1.8ms (typ.)) 5:The logic of input signal is high-active. The input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. 6:To prevent malfunction of protection, the wiring of, B, C should be as short as possible. 7:Please set the R1C5 time constant in the range 1.5~2. 8:Each capacitor should be located as nearby the pins of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. pproximately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended. 10 : It is recommended to insert a Zener diode (24/1W) nearby each pair of supply terminals to prevent surge destruction.