APPLICATION AC100V~200V three-phase inverter drive for small power motor control. (2.2) 21.4 ±0.5 (10) (11) (10) (4.65) (2.9) 34.9 ± ±0.5 (1.

Transcription

1 MITSUBISHI SEMICODUCTOR <Dual-In-Line Package Intelligent Power Power Module> TYPE TYPE PS21869 ITEGRTED POWER FUCTIOS 600/50 low-loss CSTBT inverter bridge for 3 phase DC-to-C power conversion ITEGRTED DRIE, PROTECTIO D SYSTEM COTROL FUCTIOS r upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (U) protection. r lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). (Fig.3) Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a U fault (Lower-side supply). Input interface : 5 line CMOS/TTL compatible. (High ctive) UL pproved : Yellow Card o. E80276 PPLICTIO C100~200 three-phase inverter drive for small power motor control. Fig. 1 PCKGE OUTLIES Dimensions in mm (4.5) (3.1) 2-f4.5 ±0.2 (4.65) (3.5) (0.6) (2) ±0.3 (8.5)(2.4) (=75.6) ±0.3 (14.4) (2.5) (17.6) (2.4) 33 Type name, Lot o ± ±0.3 10± ± ± ±0.5 B (1) (10) (4.65) (3.5) Heat sink side 11.5 ± ±0.5 (16.0) ± ± ±0.5 C Heat sink side (2.2) (1.5) (0.6) 3.8 ±0.2 (2) 7 ±0.5 (2.9) 12.8 ± ±0.5 (11) (10) (1.5) Irregular solder remains 0.5MX 1.9± ± ±0.5 Detail : (t=0.7) 3.25MX Irregular solder remains 0.5MX 1.7 ± ± ±0.5 Detail : B (t=0.7) 1.85MX TERMIL CODE 1. UP 2. P1 3. UFB 4. UFS 5. P 6. P1 7. FB 8. FS 9. WP 10. P1 11. PC 12. WFB 13. WFS (0~5 ) C FO 19. U W 22. P 23. U W 26. DUMMY TERMIL CODE 27. PC 28. UPG 29. P 30. PC 31. PG 32. U 33. WPG UG 36. C 37. O 38. WG 39. G 40. W 41. P Detail : C - : Long terminal type (16.0mm)

2 Fig. 2 ITERL FUCTIOS BLOCK DIGRM (TYPICL PPLICTIO EXMPLE) C1 : Tight tolerance, temp-compensated electrolytic type (ote : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit P High-side input (PWM) (5 line) (ote 1,2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (U) Protection circuit (U) Protection circuit (U) Drive circuit Drive circuit Drive circuit CBU CBU+ CBW+ CBW CB+ CB C2 C1 (ote 6) C line input Z Z : ZR (Surge absorber) C : C filter (Ceramic capacitor 2.2~6.5nF) (ote : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). C C Low-side input (PWM) (5 line) (ote 1, 2) (ote 4) Fig. 3 1 Drive circuit Input signal conditioning logic Protection circuit FO Fault output (5 line) (ote 3, 5) Control supply Under-oltage protection H-side IGBTS U W L-side IGBTS (15 line) ote1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. 2: By virtue of integrating an application specific type HIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 8) 3: This output is open collector type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistance. (see also Fig. 8) 4: The wiring between the power DC link capacitor and the P1 terminals should be as short as possible to protect the against catastrophic high surge voltages. r extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P1 DC power input pins. 5: output pulse width should be decided by putting external capacitor between and C terminals. (Example : =22nF tfo=1.8ms (Typ.)) 6: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. C D M C line output Fig. 3 EXTERL PRT OF THE PROTECTIO CIRCUIT P Drive circuit Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal () is output. Since the SC fault may be repetitive, it is recommended to stop the system when the signal is received and check the fault. IC () H-side IGBTS U W SC Protection Trip Level External protection circuit L-side IGBTS 1 Shunt Resistor (ote 1) C C R Drive circuit B Protection circuit C (ote 2) ote1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of, B, C should be as short as possible. 0 Collector current waveform 2 tw ()

3 MXIMUM RTIGS (Tj = 25 C, unless otherwise noted) IERTER PRT Symbol Ratings CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature pplied between P- pplied between P- Tf = 25 C Tf = 25 C, less than 1ms Tf = 25 C, per 1 chip (ote 1) ~+125 ote 1 : The maximum junction temperature rating of the power chips integrated within the is 150 C (@ Tf 100 C) however, to ensure safe operation of the, the average junction temperature should be limited to Tj(ave) 125 C (@ Tf 100 C). W C COTROL (PROTECTIO) PRT Symbol Ratings D DB I FO IFO SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between P1-PC, 1-C pplied between UFB-UFS, FB-FS, WFB-WFS pplied between UP, P, WP-PC, U,, W-C pplied between FO-C Sink current at FO terminal pplied between -C ~D ~D ~D+0.5 TOTL SYSTEM Symbol Ratings Self protection supply voltage limit D = 13.5~16.5, Inverter part CC(PROT) Tj = 125 C, non-repetitive, less than 2 (short circuit protection capability) Tf Module case operation temperature (ote 2) C Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, C 1 minute, connection pins to heat-sink plate ~ ~ C rms ote 2 : Tf MESUREMET POIT l Board Specification : Dimensions : mm, Finishing : 12s, Warp : 50~100µm Control Terminals Groove 18mm I board 13.5mm P U W Power Terminals FWDi Chip IGBT Chip Temp. measurement point (inside the I board) Temp. measurement point (inside the I board) Silicon-grease should be applied evenly with a thickness of 100~200µm

4 THERML RESISTCE Symbol Rth(j-f)Q Rth(j-f)F Junction to case thermal resistance (ote 3) Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) ote 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of and heat-sink. Min. Typ. Max C/W C/W ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) IERTER PRT CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current D = DB = 15 IC = 50, Tj = 25 C I = 5 IC = 50, Tj = 125 C Tj = 25 C, IC = 50, I = 0 CC = 300, D = DB = 15 IC = 50, Tj = 125 C, I = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 125 C Min. Typ. Max COTROL (PROTECTIO) PRT Symbol ID FOH FOL SC(ref) II UDBt UDBr UDt UDr tfo th(on) th(off) Circuit current Fault output voltage Short circuit trip level Input current Supply circuit under-voltage protection Fault output pulse width O threshold voltage OFF threshold voltage D = DB = 15 I = 5 D = DB = 15 I = 0 Total of P1-PC, 1-C UFB-UFS, FB-FS, WFB-WFS Total of P1-PC, 1-C UFB-UFS, FB-FS, WFB-WFS SC = 0, FO circuit pull-up to 5 with 10kΩ SC = 1, IFO = 1 Tj = 25 C, D = 15 (ote 4) I = 5 Trip level Tj 125 C Reset level Trip level Reset level = 22nF (ote 5) pplied between UP, P, WP-PC, U,, W-C Min. Typ. Max ote 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 85. 5:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tfo depends on the capacitance value of according to the following approximate equation : = tfo [F]. ms

5 MECHICL CHRCTERISTICS D RTIGS Mounting torque Weight Heat-sink flatness Mounting screw : M4 Recommended 1.18 m (ote 6) Min Typ. 65 Max m g µm ote 6: Measurement point of heat-sink flatness + Measurement location 3mm Heat-sink side + Heat-sink side RECOMMEDED OPERTIO CODITIOS CC D DB D, DB tdead fpwm IO Symbol PWI C Supply voltage Control supply voltage Control supply voltage Control supply variation rm shoot-through blocking time PWM input frequency llowable r.m.s. current Minimum input pulse width C variation pplied between P- pplied between P1-PC, 1-C pplied between UFB-UFS, FB-FS, WFB-WFS r each input signal, Tf 100 C Tf 100 C, Tj 125 C CC = 300, D = 15, fc = 5kHz P.F = 0.8, sinusoidal Tj 125 C, Tf 100 C (ote 7) O (ote 8) between C- (including surge) ote 7 : The allowable r.m.s. current value depends on the actual application conditions. 8:The input pulse width less than PWI might make no response. Min. Typ. Max / khz rms ns

6 Fig. 4 THE ITERL CIRCUIT UFB UFS P1 HIC1 CC B IGBT1 Di1 P UP I HO COM S U FB FS P1 HIC2 CC B IGBT2 Di2 P I HO COM S WFB WFS P1 HIC3 CC B IGBT3 Di3 WP I HO PC COM S W LIC IGBT4 Di4 UOUT 1 CC IGBT5 Di5 OUT U U WOUT IGBT6 Di6 W W O C GD

7 Fig. 5 TIMIG CHRTS OF THE PROTECTIE FUCTIOS [] Short-Circuit Protection (Lower-arms only) (With the external shunt resistance and CR connection) a1. ormal operation : IGBT O and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor. a6. Input L : IGBT OFF state. a7. Input H : IGBT O state, but during the FO active signal period the IGBT doesn t turn O. a8. IGBT OFF state. Lower-arms control input a6 a7 Protection circuit state SET Internal IGBT gate a2 a3 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistance SC reference voltage Error output a5 CR circuit time constant DELY [B] Under-oltage Protection (Lower-arm, UD) b1. Control supply voltage rises : fter the voltage level reaches UDr, the circuits start to operate when next input is applied. b2. ormal operation : IGBT O and carrying current. b3. Under voltage trip (UDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UDr). b7. ormal operation : IGBT O and carrying current. Control input Protection circuit state SET Control supply voltage D UDr b1 UDt b3 b6 b2 b4 b7 Output current Ic Error output b5

8 [C] Under-oltage Protection (Upper-arm, UDB) c1. Control supply voltage rises : fter the voltage reaches UDBr, the circuits start to operate when next input is applied. c2. ormal operation : IGBT O and carrying current. c3. Under voltage trip (UDBt). c4. IGBT OFF in spite of control input condition, but there is no FO signal output. c5. Under voltage reset (UDBr). c6. ormal operation : IGBT O and carrying current. Control input Protection circuit state SET UDBr Control supply voltage DB c1 UDBt c3 c5 c2 c4 c6 Output current Ic Error output High-level (no fault output) Fig. 6 RECOMMEDED CPU I/O ITERFCE CIRCUIT 5 line 10kΩ UP,P,WP,U,,W CPU C(Logic) 2.5kΩ (min) ote : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application s printed circuit board. The input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. Fig. 7 RECOMMEDED WIRIG OF SHUT RESISTCE Wiring inductance should be less than 10nH. width=3mm, thickness=100µm, length=17mm in copper pattern (rough standard) Shunt resistor C Please make the connection point as close as possible to the terminal of shunt resistor.

9 Fig. 8 TYPICL PPLICTIO CIRCUIT EXMPLE C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering. (ote: The capacitance value depends on the PWM control used in the applied system.) C2 C1 C3 UFB UFS P1 UP HIC1 CC B I HO P C2 C1 FB FS COM S U C3 P1 P HIC2 CC B I HO CPU UIT C2 C1 C3 WFB WFS P1 WP PC COM S HIC3 CC B I HO COM S LIC UOUT W M 1 C3 CC 5 line OUT 15 line U W C U W GD WOUT O Long GD wiring here might generate noise to input and cause IGBT malfunction. C4() C5 B R1 C Shunt Resistance If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. Too long wiring here might cause short-circuit. 1 ote 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (2cm~3cm or less) 2:By virtue of integrating an application specific type HIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3:FO output is open collector type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. 4:FO output pulse width is determined by the external capacitor between and C terminals (). (Example : = 22 nf tfo = 1.8 ms (typ.)) 5:The logic of input signal is high-active. The input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. 6:To prevent malfunction of protection, The wiring of, B, C should be as short as possible. 7:Please set the R1C5 time constant in the range 1.5~2. 8:Each capacitor should be located as nearby the pins of the as possible. 9:To prevent surge destruction, the wiring between the smoothing capacitor and the P&1 pins should be as short as possible. pproximately a 0.1~0.22µF snubber capacitor between the P&1 pins is recommended.