PS21963-ET/-AET/-CET/-ETW TRANSFER-MOLD TYPE INSULATED TYPE

Transcription

1 PS21963-ET INTEGRTED POWER FUNCTIONS 600/8 low-loss CSTT TM inverter bridge for three phase DC-to-C power conversion INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS For upper-leg IGTS :, High voltage high-speed level shifting, Control supply under-voltage (U) protection. For lower-leg IGTS :, Control supply under-voltage protection (U), Short circuit protection (SC), Over temperature protection (OT). Fault signaling : Corresponding to an SC fault (Lower-leg IGT), a U fault (Lower-side supply) or an OT fault (LIC temperature). Input interface : 3, 5 line (High ctive). UL pproved : Yellow Card No. E80276 PPLICTION C100~200 three-phase inverter drive for small power motor control. Fig. 1 PCKGE OUTLINES (PS21963-ET) Dimensions in mm ± (=35.56) 35 ± ±0.2 2-R QR Code 3 MIN ±0.2 Type name Lot No (=35.56) ± (1) 24 ± 4-C ± 29.2 ± 14.4 ± 14.4 ± 2.5 MIN (2.656) (2.756) (3.5) 0.8 DETIL ±0.05 (3.3) (0~5 ) TERMINL CODE 1. NC 2. UF 3. F 4. WF 5. UP 6. P 7. WP 8. P1 9. NC * 10. UN 11. N 12. WN 13. N1 14. FO 15. CIN 16. NC * 17. NC 18. NC 19. NC 20. N 21. W U 24. P 25. NC DETIL *) Two NC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15 power supply GND outside and leave another one open. 1.5 MIN

2 MITSUISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> Fig. 2 LONG TERMINL TYPE PCKGE OUTLINES (PS21963-ET) ± (=35.56) 35 ± ±0.2 2-R QR Code 3 MIN Type name Lot No ± (=35.56) ± (1) 24 ± 4-C ± 29.4 ± 14.4 ± 14.4 ± 2.5 MIN (2.656) (2.756) (3.5) ±0.05 (3.3) (0~5 ) Dimensions in mm TERMINL CODE 1. NC 2. UF 3. F 4. WF 5. UP 6. P 7. WP 8. P1 9. NC * 10. UN 11. N 12. WN 13. N1 14. FO 15. CIN 16. NC * 17. NC 18. NC 19. NC 20. N 21. W U 24. P 25. NC DETIL DETIL *) Two NC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15 power supply GND outside and leave another one open. 1.5 MIN Fig. 3 ZIGZG TERMINL TYPE PCKGE OUTLINES (PS21963-CET) ± (=35.56) 35 ± ±0.2 2-R QR Code 3 MIN ± (=35.56) Type name Lot No ± (1) 24 ± 4-C ± 33.7 ± 29.2 ± 18.9 ± 14.4 ± 14.4 ± (2.656) (2.756) (3.5) 0.8 DETIL ±0.05 (0~5 ) (0~5 ) TERMINL CODE 1. NC 2. UF 3. F 4. WF 5. UP 6. P 7. WP 8. P1 9. NC * 10. UN 11. N 12. WN 13. N1 14. FO 15. CIN 16. NC * 17. NC 18. NC 19. NC 20. N 21. W U 24. P 25. NC DETIL Dimensions in mm *) Two NC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15 power supply GND outside and leave another one open. 1.5 MIN 2

3 MITSUISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> Fig. 4 OTH SIDES ZIGZG TERMINL TYPE PCKGE OUTLINES (PS21963-ETW) 12 (1.8) 38 ± (=35.56) 35 ± ± R QR Code 3 MIN ±0.25 Type name Lot No (=35.56) ± (1) 24 ± 4-C ± 35.2 ± ± ± 17.4 ± 14.4 ± ± 2.5 MIN (2.656) (2.756) (3.5) 0.8 DETIL ±0.05 (0~5 ) (0~5 ) TERMINL CODE 1. NC 2. UF 3. F 4. WF 5. UP 6. P 7. WP 8. P1 9. NC * 10. UN 11. N 12. WN 13. N1 14. FO 15. CIN 16. NC * 17. NC 18. NC 19. NC 20. N 21. W U 24. P 25. NC DETIL 1.5 MIN Dimensions in mm *) Two NC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15 power supply GND outside and leave another one open. QR Code is registered trademark of DENSO WE INCORPORTED in Japan and other countries. Fig. 5 INTERNL FUNCTIONS LOCK DIGRM (TYPICL PPLICTION EXMPLE) C1 : Electrolytic type with good temperature and frequency characteristics (Note : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. Inrush current limiter circuit P High-side input (PWM) (3, 5 line)(note 1, 2) Input signal conditioning Level shifter Protection circuit (U) Input signal conditioning Level shifter Input signal conditioning Level shifter CW+ CW C+ C CU+ CU H-side IGTS C2 C1 (Note 6) (Note 5) DIPIPM C line input (Note 4) U W (Note 7) M C line output Z C Z : Surge absorber C : C filter (Ceramic capacitor 2.2~6.5nF) (Note : dditionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). N1 N NC CIN Input signal conditioning Fo logic Protection circuit Control supply Under-oltage protection L-side IGTS Low-side input (PWM) (3, 5 line)(note 1, 2) FO Fault output (5 line) (Note 3) NC D (15 line) Note1: Input logic is high-active. There is a 3.3kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. 2: y virtue of integrating an application specific type HIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 11) 3: This output is open drain type. The signal line should be pulled up to the positive side of the 5 power supply with approximately 10kΩ resistor. (see also Fig. 11) 4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIPIPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P & N1 DC power input pins. 5: High voltage (600 or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. 6: It is recommended to insert a Zener diode (24/1W) between each pair of control supply terminals to prevent surge destruction. 7: ootstrap negative electrodes should be connected to U,, W terminals directly and separated from the main output wires. (Note 6) 3

4 Fig. 6 EXTERNL PRT OF THE DIPIPM PROTECTION CIRCUIT P DIPIPM Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-us current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC () H-side IGTS U W SC Protection Trip Level External protection circuit L-side IGTS N1 Shunt Resistor N (Note 1) NC C R CIN Protection circuit C (Note 2) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0. 2: To prevent erroneous protection operation, the wiring of,, C should be as short as possible. 0 Collector current waveform 2 tw () MXIMUM RTINGS (Tj = 25 C, unless otherwise noted) INERTER PRT Symbol Parameter Ratings Unit CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGT collector current Each IGT collector current (peak) Collector dissipation Junction temperature pplied between P-N pplied between P-N TC = 25 C TC = 25 C, less than 1ms TC = 25 C, per 1 chip (Note 1) ~+125 Note 1 : The maximum junction temperature rating of the power chips integrated within the DIPIPM is 150 C (@ TC 100 C). However, to ensure safe operation of the DIPIPM, the average junction temperature should be limited to Tj(ave) 125 C (@ TC 100 C). W C CONTROL (PROTECTION) PRT Symbol Parameter Ratings Unit D D IN FO IFO SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage pplied between P1-NC, N1-NC pplied between UF-U, F-, WF-W pplied between UP, P, WP, UN, N, WN-NC pplied between FO-NC Sink current at FO terminal pplied between CIN-NC ~D+ ~D+ 1 ~D+ m 4

5 TOTL SYSTEM Symbol Parameter Ratings Unit Self protection supply voltage limit D = 13.5~16.5, Inverter part CC(PROT) Tj = 125 C, non-repetitive, less than 2 (short circuit protection capability) TC Module case operation temperature (Note 2) C Tstg iso Storage temperature Isolation voltage 60Hz, Sinusoidal, 1 minute, etween pins and heat-sink plate ~ ~ C rms Note 2: TC measurement point Control terminals 11.6mm 3mm IGT chip position FWD chip position Power terminals TC point Heat sink side THERML RESISTNCE Symbol Parameter Rth(j-c)Q Junction to case thermal Inverter IGT part (per 1/6 module) 4.1 C/W Rth(j-c)F resistance (Note 3) Inverter FWD part (per 1/6 module) 5.4 C/W Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIPIPM and heat-sink. The contacting thermal resistance between DIPIPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3 C/W when the grease thickness is 20µm and the thermal conductivity is 1.0W/m k. Min. Limits Typ. Max. Unit ELECTRICL CHRCTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PRT CE(sat) EC ton trr Symbol tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Switching times Collector-emitter cut-off current D = D = 15 IC = 8, Tj = 25 C IN = 5 IC = 8, Tj = 125 C Tj = 25 C, IC = 8, IN = 0 CC = 300, D = D = 15 IC = 8, Tj = 125 C, IN = 0 5 Inductive load (upper-lower arm) CE = CES Tj = 25 C Tj = 125 C Limits Min. Typ. Max Unit m 5

6 CONTROL (PROTECTION) PRT Symbol ID FOH FOL SC(ref) IIN OTt OTrh UDt UDr UDt UDr tfo th(on) th(off) th(hys) Circuit current Parameter Fault output voltage Short circuit trip level Input current Over temperature protection (Note 5) Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage ON/OFF threshold hysteresis voltage D = D = 15 IN = 5 D = D = 15 IN = 0 Total of P1-NC, N1-NC UF-U, F-, WF-W Total of P1-NC, N1-NC UF-U, F-, WF-W SC = 0, FO terminal pull-up to 5 by 10kΩ SC = 1, IFO = 1m Tj = 25 C, D = 15 (Note 4) IN = 5 D = 15, t temperature of LIC Tj 125 C Trip level Trip/reset hysteresis Trip level Reset level Trip level Reset level (Note 6) pplied between UP, P, WP, UN, N, WN-NC Limits Min. Typ. Max Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 5:Over temperature protection (OT) outputs fault signal, when the LIC temperature exceeds OT trip temperature level (OTt). In that case if the heat sink comes off DIPIPM or fixed loosely, don t reuse that DIPIPM. (There is a possibility that junction temperature of power chips exceeded maximum Tj (150 C)). 6:Fault signal is asserted only corresponding to a SC, a U or an OT failure at lower side, and the FO pulse width is different for each failure modes. For SC failure, FO output is with a fixed width of 20ec(min), but for U or OT failure, FO output continuously during the whole U or OT period, however, the minimum FO pulse width is 20ec(min) for very short U or OT period less than 20ec Unit m m m m m C MECHNICL CHRCTERISTICS ND RTINGS Parameter Mounting screw : M3 Mounting torque (Note 7) Weight Heat-sink flatness Note 7 : Plain washers (ISO 7089~7094) are recommended. Recommended : 0.69 N m (Note 8) Min Limits Typ. 10 Max Unit N m g µm Note 8: Flatness measurement position + Measurement position 4.6mm Heat sink side + Heat sink side 6

7 RECOMMENDED OPERTION CONDITIONS CC D D D, D tdead fpwm IO Symbol Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation rm shoot-through blocking time PWM input frequency llowable r.m.s. current pplied between P-N pplied between P1-NC, N1-NC pplied between UF-U, F-, WF-W For each input signal, TC 100 C TC 100 C, Tj 125 C CC = 300, D = D = 15, fpwm = 5kHz P.F = 0.8, sinusoidal PWM, Tj 125 C, TC 100 C (Note 9) fpwm = 15kHz PWIN(on) llowable minimum input PWIN(off) pulse width (Note 10) NC NC variation etween NC-N (including surge) 5.0 Note 9 : The allowable r.m.s. current value depends on the actual application conditions. 10 : IPM might not make response if the input signal pulse width is less than the recommended minimum value. Limits Min. Typ. Max Unit / khz rms Fig. 7 THE DIPIPM INTERNL CIRCUIT UF P1 CC HIC U IGT1 Di1 P UP UP UOUT NC COM US U F IGT2 Di2 P P OUT S WF W IGT3 Di3 WP WP WOUT WS W LIC IGT4 Di4 UOUT N1 CC IGT5 Di5 OUT UN UN N N IGT6 Di6 WN Fo WN Fo WOUT CIN NO NC GND N CIN 7

8 Fig. 8 TIMING CHRT OF THE DIPIPM PROTECTIE FUNCTIONS [] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter) a1. Normal operation : IGT ON and carrying current. a2. Short circuit detection (SC trigger). a3. IGT gate hard interruption. a4. IGT turns OFF. a5. FO outputs (tfo(min) = 20). a6. Input L : IGT OFF. a7. Input H : IGT ON. a8. IGT OFF in spite of input H. Lower-side control input a6 a7 Protection circuit state SET Internal IGT gate a2 a3 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistor SC reference voltage Error output Fo a5 CR circuit time constant DELY [] Under-oltage Protection (Lower-side, UD) b1. Control supply voltage rising : fter the voltage level reaches UDr, the circuits start to operate when next input is applied. b2. Normal operation : IGT ON and carrying current. b3. Under voltage trip (UDt). b4. IGT OFF in spite of control input condition. b5. FO outputs (tfo 20 and FO outputs continuously during U period). b6. Under voltage reset (UDr). b7. Normal operation : IGT ON and carrying current. Control input Protection circuit state SET Control supply voltage D UDr b1 UDt b3 b6 b2 b4 b7 Output current Ic Error output Fo b5 8

9 [C] Under-oltage Protection (Upper-side, UD) c1. Control supply voltage rising : fter the voltage level reaches UDr, the circuits start to operate when next input is applied. c2. Normal operation : IGT ON and carrying current. c3. Under voltage trip (UDt). c4. IGT OFF in spite of control input signal level, but there is no FO signal outputs. c5. Under voltage reset (UDr). c6. Normal operation : IGT ON and carrying current. Control input Protection circuit state SET UDr Control supply voltage D c1 UDt c3 c5 c2 c4 c6 Output current Ic Error output Fo High-level (no fault output) [D] Over Temperature Protection (Lower-side, OT) d1. Normal operation : IGT ON and carrying current. d2. LIC temperature exceeds over temperature trip level (OTt). d3. IGT OFF in spite of control input condition. d4. FO outputs during over temperature period, however, the minimum pulse width is 20. d5. LIC temperature becomes under over temperature reset level. d6. Circuits start to operate normally when next input is applied. Control input Protection circuit state SET LIC temperature OTt d2 d5 Output current Ic d1 d3 OTrh d6 Fault output Fo d4 Fig. 9 RECOMMENDED MCU I/O INTERFCE CIRCUIT 5 line 10kΩ DIPIPM UP,P,WP,UN,N,WN MCU Fo NC(Logic) 3.3kΩ (min) Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The DIPIPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage. Fig. 10 WIRING CONNECTION OF SHUNT RESISTOR NC DIPIPM Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100µm, length=17mm N Shunt resistor Please make the GND wiring connection of shunt resistor to the NC terminal as close as possible. 9

10 Fig. 11 N EXMPLE OF TYPICL DIPIPM PPLICTION CIRCUIT C1: Electrolytic capacitor with good temperature characteristics C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering C2 C1 C2 C1 C2 C1 C3 P1 UP UF F WF HIC CC U UP UOUT P ootstrap negative electrodes should be connected to U,, W terminals directly and separated from the main output wires. US U P P OUT S M W MCU WP NC WP WOUT COM WS W LIC UOUT 5 line C3 N1 CC OUT UN UN N N WN Fo NC WN Fo GND WOUT CIN Long wiring here might cause short-circuit. N C 15 line Long GND wiring here might generate noise to input and cause IGT malfunction. C4 R1 Long wiring here might cause SC level fluctuation and malfunction. Shunt resistor N1 Note 1 : Input drive is High-ctive type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 2 :Thanks to HIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 3 :FO output is open drain type. It should be pulled up to the positive side of a 5 power supply by a resistor of about 10kΩ. 4 :To prevent erroneous protection, the wiring of,, C should be as short as possible. 5 :The time constant R1C4 of the protection circuit should be selected in the range of SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4. 6 :ll capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.) 7 :To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a µF snubber between the P-N1 terminals is recommended. 8 :Two NC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15 power supply GND outside and leave another one open. 9 :It is recommended to insert a Zener diode (24/1W) between each pair of control supply terminals to prevent surge destruction. 10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point. 10