High-speed Serial Interface

Transcription

1 High-speed Serial Interface Lect. 9 Noises 1

2 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2

3 Sampling in Rx Interface applications usually employ binarylevel signaling Rx samples input signal with single threshold. Tx Rx DATA Channel Sampler 3 Threshold Input Signal Sampling Point

4 Noise in time domain Noises in high-speed interface can be easily observed in time-domain Noise waveform is added on the signal waveform Sampling Point 4

5 How noise affects sampling? Noise at sampling point can cause wrong sampling Sampling Point 5

6 How noise affects sampling? Noise can disturb the disturb sampling point Noise can distorts clock generation both in Tx and Rx. If sampling point goes outside of data period, sampling results in wrong data. Timing noise reduces sampling margin. Tx CLK Sampling Point 6

7 How noise affects sampling? AM-to-PM noise conversion Amplitude noise at signal transition reduces timing margin. Shorter the transition time, less the noise conversion Threshold Timing margin Bit period 7

8 Jitter Definition Jitter is the undesired deviation from true periodicity of an assumed periodic signal in electronics and telecommunications, often in relation to a reference clock source. by wikipedia Jitter is noise observation in time domain. Amplitude noise can be also observed as jitter Jitter reduces timing margin of sampling 8

9 Bit-error rate (BER) Most important performance metric. BER shows end-to-end system performance. Timing margin is evaluated from BER performance. BER is calculated as follows; = 9

10 Bit-error rate (BER) BER: Probability that the noise will exceed a given value 10

11 Bit-error rate (BER) For Gaussian noises, Probability that the noise will exceed a given value: 11

12 Bath-tub Eye-diagram BER contour Bath-tub for Timing Bath-tub for Amplitude Timing margin for BER<10-6 and

13 Where are noises from? Device noise Channel noise Power supply Coupling 13

14 Device noise Noise sources in MOSFETs Thermal noise in the channel 1/f noise Noise in the resistive poly gate Noise due to the distributed substrate resistance Shot noise associated with the leakage current of the drain source reverse diodes Noise sources in other devices resistor / capacitor / diode * Reference: 14

15 Device noise Device noise in amplifiers Device noise of Tx output and Rx input buffer stage generate random noise. This kind of noise is not significant in electrical-channel-based interface since the signal amplitude is usually large enough. Device noise in clock generators Device noise of Tx clock generator and Rx clock recovery circuit generate random noise. This noise is significant and will be covered in next lectures. 15

16 Device noise Duty-cycle distortion Originally metric of clock generation. This kind of noise is deterministic and static. Duty-cycle distortion gives asymmetric timing margin for high and low signal. Defined as follows; Bit period = " " Threshold Clock Signal Period of High 16

17 Device noise Duty-cycle distortion Single-ended signaling: threshold variation Single-ended signaling requires threshold which is usually generated in Rx side. If threshold is not exactly mid-level, duty cycle is distorted. Bit period Threshold > 0.5 Input Signal Duty cycle = 50% Period of High Duty cycle < 50% 17

18 Device noise Duty-cycle distortion Differential signaling: differential offset Differential amplifier has differential offset which is caused by mismatch of input transistor pair. Cross-point of differential signals is changed, thus, duty-cycle is distorted. Z load Z load OUT- OUT+ IN+ gm gm IN- I bias Input Signal - Bit period Input Signal + Period of High Duty cycle < 50% 18

19 Channel noise Random noise Electrical channel Thermal noise in electrical channel generate random noise. This kind of noise is not significant compared to channel ISI since the signal amplitude is usually large enough. 19

20 Channel noise Inter-symbol interference ISI is covered in previous lectures. Reduces both amplitude and timing margin. Dominant noise source in BW-limited channel. 20

21 Power supply noise Performance degrades by power supply noise Lowered power supply voltage results in BW limitation. Transition time is enlarged. AM-to-PM noise conversion Decision threshold Threshold voltage of CMOS logic is defined by P/N ratio and supply voltage. Bias condition Bias condition (gm or rout) is changed as supply voltage changes 21

22 Power supply noise IR drop in power-supply rail Power supply rail is resistive channel Large current drawing results in significant voltage drop. Resistance is reduced by large-width of supply rail. Power supply branching topology is also important. The width and topology of power-supply rail should not be the main limiting factor in PCB or IC design. VDD I 1 I 2 I 3 VDD1 VDD 2 VDD 3 Device #1 Device #2 Device #3 22

23 Power supply noise Self-generated supply noise Power supply rail is also inductive channel BW of current flowing is limited. Capacitances are located near devices. Instantaneous current drawing results in peak on the supply. VDD Supply Source IN IN OUT OUT VDD VSS Supply Source VSS 23

24 Power supply noise Induced supply noise Supply noise from the external noise source Power management IC cannot reject noise perfectly. Supply noise from adjacent device Supply noise is generated from device sharing power supply rail DC-DC Converter 220V AC Interface Chip Digital Signal Processing Chip 24

25 Power supply noise How to minimize the effect of power supply noise? 1. supply filtering Supply noise can be filtered by external components. Trade-off in supply filtering and the number of external components LC-type Supply filter DC-DC Converter 220V AC CAP Bead Bead CAP Interface Chip Digital Signal Processing Chip (Ferrite bead, Ferrite choke) 25

26 Power supply noise How to avoid the effect of power supply noise? 2. on-chip supply regulator Supply regulator can be integrated on the IC. Internal VDD is reduced. Very large capacitors should be integrated. VDD Vref Internal VDD Devices VSS 26

27 Power supply noise How to avoid the effect of power supply noise? 3. circuit topology using differential signaling Single-ended signaling suffers from threshold variation by supply noise. Threshold of differential signaling is defined as crossing point. Differential signaling requires much larger power consumption and chip area. trade-off Threshold Input Signal Single-ended signaling Input Signal - Input Signal + Differential signaling 27

28 Coupling noise Crosstalk between lanes Neighboring channels have both capacitive and inductive coupling Mutual Capacitance, Cm Mutual Inductance, Lm V Lm L m di dt Cm far far Lm Zs near Zs near I Cm C m dv dt 28

29 Coupling noise Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT) far far I Cm Lm I Lm Zs near Zs near I near I Cm I Lm I far I Cm I Lm 29

30 Coupling noise Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT) Driven Line Far End Un-driven Line victim Driver Zs Near End 30

31 Coupling noise Time = 0 V Near end crosstalk pulse at T=0 (I near ) TD ~Tr Near end crosstalk Time= 1/2 TD V Far end crosstalk pulse at T=0 (I far ) ~Tr 2TD far end crosstalk Time= TD V Far end terminated at T=TD Time = 2TD 31 V Near end Terminated at T=2TD

32 Coupling noise How to minimize inter-lane crosstalk? Enlarge space between channel Most effective but trade-off with PCB artwork. Adjust transition timing of each lane Split transition timing of adjacent lanes. ex) ½ UI delayed timing for even-numbered lanes.» Fluctuation appears at center of data period Compensate coupling at Tx side Tx knows output data patterns of all lanes. 32

33 Coupling noise Inter-chip crosstalk Similar coupling problem appears on the IC level. N coupled lines: (a) capacitive coupling only, (b) inductive coupling only, and (c) capacitive and inductive coupling. Victoria Vishnyakov, Multi-aggressor capacitive and inductive coupling noise modeling and mitigation Microelectronics journal,

34 Coupling noise How to minimize inter-chip crosstalk? Separate sensitive signals Shield signal lines Employing grounded-shielding line Layout effort / area issues Use different metal layers for adjacent lanes Usually minimum spacing within the same metal layer is much smaller than the separation between metal layers Perpendicular routing for vertical metal layers (Manhattan routing) Limit maximum parallel routing distance 34

35 Coupling noise How to minimize inter-chip crosstalk? Maximize signal transition time For differential signals, periodically twist routing Separate sensitive signals 35