A Low Power Ultra Wideband Transceiver and Sensor Interface Architecture for Wireless Sensor Networks

Transcription

1 A Low Power Ultra Wideband Transceiver and Sensor Interface Architecture for Wireless Sensor Networks By Karim Allidina, M.A.Sc. Department of Electrical and Computer Engineering McGill University, Montreal, Quebec, Canada Aug. 08, 2014 A thesis submitted to McGill University In partial fulfillment of the requirements of the degree of Doctor of Philosophy Copyright 2014 All rights reserved.

2 ACKNOWLEDGMENTS The first person I would like to thank is my supervisor, Dr. Mourad El-Gamal. His advice and insight went far beyond the technical aspects and helped me analyze my research from various perspectives, including the ever important big picture. I am grateful for his continued support and for his confidence in my abilities. I would also like to thank Dr. Tamer Khattab for our discussions concerning the statistical analysis of communications systems. His technical advice was much appreciated. There are many others who made this research successful, and helped me maintain my sanity through many days (and nights) spent in the lab. The list includes Frederik Nabki, Adrian Ngoly, Chris Rodenchuck, Paul-Vahe Cicek, Mahdi Parvizi, Ali Gorgi, Qing Zhang, Sareh Mahdavi, Mohannad Elsayed, and Ahmad Alfaifi. I would like thank my wife Kim for her continued support throughout this endeavor, and my daughter Adara who may yet understand all of this when she grows up. I would also like to thank my parents and my brother for their encouragement and support. Finally, I would like to thank McGill University and the National Sciences and Engineering Research Council of Canada (NSERC) for their financial support of this research. ii

3 TABLE OF CONTENTS TABLE OF CONTENTS... iii LIST OF TABLES... vi LIST OF FIGURES... vii LIST OF ABBREVIATIONS... xi ABSTRACT... xiii ABRÉGÉ... xiv Chapter 1 - Introduction Motivation Background of Ultra Wideband Technology Advantages and Challenges of IR-UWB Technology Research Goal Contributions The Design of a Low Power LNA for UWB Systems Analysis of Non-Coherent UWB Systems in the Presence of Noise and Interference The Design of a Low Power UWB Transceiver with a Fast and Low Complexity Synchronization Scheme A Temperature Compensated Architecture for Integrated, Low Power, Frequency Domain Sensors Related Contributions Thesis Outline Chapter 2 Overview of UWB Systems Introduction IR-UWB Modulation Techniques Ultra Wideband Transmitters Direct Generation of an UWB Pulse UWB Pulse Generation by Filtering a Broadband Pulse UWB Pulse Generation by Upconverting a Baseband Pulse Digital Pulse Generation with a Digital-to-Analog Converter Comparison of Implemented UWB Transmitters Ultra Wideband Receivers Synchronization of UWB Receivers UWB Receiver Implementations Ph.D. Thesis iii 2014 K. Allidina

4 2.5.1 IR-UWB Receivers Based on Correlation in the Analog Domain Mostly Digital IR-UWB Receivers IR-UWB Receivers Based on Energy Detection IR-UWB Receivers Based on Peak Detection Comparison of Implemented UWB Receivers The Proposed System Chapter 3 - Analysis of Non-Coherent UWB Receivers Introduction System Description Performance in the Presence of Noise Energy Detector Performance Peak Detector Performance Performance Comparison Performance in the Presence of Interference Energy Detector Performance Peak Detector Performance Performance Comparison Simulation Results AWGN Channel Results Multipath Channel Results Summary Chapter 4 - A Compact and Low Power UWB Transceiver with a Fast and low Complexity Synchronization Scheme Introduction System Level Description of the Receiver Ultra-Wideband Receiver Design RF Front-End The LNA The Amplifier Chain The Comparator RF-Front End Summary Clock and Data Recovery System The Phase / Frequency Detector The Charge Pump Ph.D. Thesis iv 2014 K. Allidina

5 The Loop Filter The Voltage Controlled Oscillator CDR Loop Dynamics Cycled Biasing of the RF Front-End Clock and Data Recovery System Summary Ultra-Wideband Transmitter Design Measurement Results Transmitter Measurements Receiver Measurements Summary Chapter 5 - A Low Power Sensor Interface with Temperature Compensation for Frequency Domain Sensors Introduction Background of Capacitive Sensor Interfaces The MEMS Capacitive Humidity Sensor Description of the Architecture System Level Simulations Summary Chapter 6 - Conclusion Research Summary Future Work LIST OF REFERENCES Ph.D. Thesis v 2014 K. Allidina

6 LIST OF TABLES Table 1-1: Summary of Recent Low Power, Low Data Rate Narrowband Receivers Table 2-2: Comparison of Recent Transmitters that Operate in the GHz UWB Band Table 2-3: Comparison of Recent Transmitters that operate in the MHz UWB Band Table 2-4: Comparison of Recent Receivers that Operate in the GHz UWB Band Table 2-5: Comparison of Recent Receivers that Operate in the GHz UWB Band Table 4-1: Link Budget Calculation Table 4-2: Equations for the input impedance and noise figure of the LNAs in Fig Table 4-3: Performance Comparison of Wideband LNAs in the Band of Interest Table 4-4: Parameters and Component Values of the CDR Loop Table 4-5: Comparison of IR-UWB transmitter with recent works Table 4-6: Description of the waveforms in Fig Table 4-7: Comparison of this IR-UWB receiver with recent works Ph.D. Thesis vi 2014 K. Allidina

7 LIST OF FIGURES Fig. 1-1: FCC emissions mask for ultra wideband communications Fig. 1-2: Link capacity vs. distance for an ultra wideband and narrowband system, both in the range of 2.4 GHz Fig. 1-3: Common existing wireless services in the MHz UWB band Fig. 1-4: Power consumption vs. data rate for recent narrowband receivers Fig. 2-1: Waveforms showing how data is modulated using a) on-off keying, b) pulse-position modulation, c) binary phase shift keying, and d) transmitted reference Fig. 2-2: Plots of the (a) time and (b) frequency domain characteristics of common IR-UWB pulses Fig. 2-3: Common topologies for IR-UWB transmitters Fig. 2-4: Waveforms of a 5 th order Gaussian pulse in the time and frequency domain Fig. 2-5: Waveforms of an upconverted triangular and square baseband pulse in the time and frequency domain Fig. 2-6: Pulse trains with the same power and different repetition rates Fig. 2-7: Pulse trains with the different powers and repetition rates Fig. 2-8: Power consumption vs. the pulse repetition rate for UWB transmitters Fig. 2-9: Energy efficiency vs. the pulse repetition rate for UWB transmitters Fig. 2-10: Correlation receiver structure and associated waveforms in a BPSK system Fig. 2-11: Simplified receiver structures for energy and peak detectors Fig. 2-12: Correlation coefficient vs. pulse misalignment for 1 ns long Guassian monocycles Fig. 2-13: Pulse train with a 1 MHz repetition rate, illustrating the low duty cycle nature Fig. 2-14: Example of a general synchronization system for correlation and energy detection receivers Fig. 2-15: UWB pulse trains with equal energy pulses at different repetition rates Fig. 2-16: Normalized sensitivity at 1 Mbps vs. front-end power consumption for UWB receivers Fig. 2-17: Energy / bit vs. the repetition rate for UWB receivers Fig. 3-1: (a) Probability density functions of the test statistics of a dual peak detector at selected time samples of a (b) received pulse Fig. 3-2: BER vs. the normalized threshold voltage for the dual peak detector Fig. 3-3: Comparison of the theoretical BER vs. E b /N 0 for a single peak detector, dual peak detector, and energy detector for various detection windows Fig. 3-4: Required E b /N 0 for a BER of 10-3 vs. the detection window duration Fig. 3-5: Energy vs. the phase of the interferer for the energy detector test statistic in the presence of a single narrowband interferer Ph.D. Thesis vii 2014 K. Allidina

8 Fig. 3-6: Amplitude vs. time plot of i(t) and s(t) + i(t) within the detection window for a peak detector Fig. 3-7: Amplitude vs. the phase of the interferer for the peak detector test statistics in the presence of one narrowband interferer Fig. 3-8: Theoretical BER results for an energy detector, a single peak detector, and a dual peak detector in the presence of a single narrow-band interferer located at various percentages of the pulse bandwidth Fig. 3-9: RMS delay for the 100 multipath channels Fig. 3-10: Histogram of the number of significant paths in each channel Fig. 3-11: Examples of two channel outputs (b, c) when the input pulse (a) is passed through these channels Fig. 3-12: Comparison between the theoretical results (solid lines) and simulated results (circles) for the peak detectors and the energy detector Fig. 3-13: Simulation results comparing the peak and energy detector performance in an AWGN channel with narrowband interferers Fig. 3-14: Simulation results comparing the performance of the peak detectors and energy detector in a multipath channel with noise Fig. 3-15: Plot of the E b /N 0 required to obtain a 10-3 BER vs. detection window duration for the peak detectors and energy detector in a multipath channel Fig. 3-16: Simulation results comparing the performance of the peak detectors and energy detector in a multipath channel with narrowband interference Fig. 3-17: Plot of the E b /I 0 required to obtain a 10-3 BER vs. detection window duration for the peak detectors and energy detector in a multipath channel Fig. 4-1: Block diagram of the UWB receiver Fig. 4-2: Expanded view of the RF front-end Fig. 4-3: Wideband amplifier topologies: a) resistively terminated common-source amplifier, b) shunt-feedback amplifier, and c) common-gate amplifier Fig. 4-4: LNA topology based on a common-gate amplifier with active feedback Fig. 4-5: Small-signal model of the LNA Fig. 4-6: The S11 response of the LNA Fig. 4-7: The S21 response of the LNA Fig. 4-8: The noise figure of the LNA Fig. 4-9: The IIP3 of the LNA at a frequency of 500MHz Fig. 4-10: The IIP3 of the LNA vs. frequency Fig. 4-11: Schematic of the amplifier chain Fig. 4-12: Schematic of the amplifier chain including the switches required for duty-cycled operation Fig. 4-13: Simulated response of the amplifier chain Fig. 4-14: Simulated tuning range of the gain with V ctrl Ph.D. Thesis viii 2014 K. Allidina

9 Fig. 4-15: Schematic of the comparator Fig. 4-16: Monte-Carlo simulation results to determine the switching threshold of the comparator in the presence of process and mismatch Fig. 4-17: Block diagram of the clock and data recovery system Fig. 4-18: Schematic of the phase detector Fig. 4-19: Phase detector waveforms for the cases where the (a) data leads the clock and (b) clock leads the data Fig. 4-20: The average voltage output from the PD vs. the data delay relative to the clock Fig. 4-21: Schematic of the frequency detector Fig. 4-22: Frequency detector waveforms for the cases where the (a) data is faster than the clock and (b) clock is faster than the data Fig. 4-23: Average phase and frequency voltage outputs from the PD and FD, respectively, as the clock period is varied for a data period fixed at 1 μs Fig. 4-24: Schematic of the charge pump Fig. 4-25: Schematic of the loop filter Fig. 4-26: Voltage controlled oscillator topology Fig. 4-27: Block level schematic of each stage in the VCO Fig. 4-28: Circuit-level schematic of each stage in the VCO Fig. 4-29: VCO frequency and power consumption vs. the control voltage Fig. 4-30: The open loop response of the CDR with and without C 2 in the loop filter Fig. 4-31: Schematic of the cycled-bias signal generation circuitry Fig. 4-32: Waveforms showing the operation of the cycled bias generation circuitry Fig. 4-33: Schematic of the UWB transmitter Fig. 4-34: Waveforms for the a) output pulse in the time domain and b) corresponding power spectral density for a 1 MHz pulse repetition rate Fig. 4-35: a) Chip micrograph (covered by metal fill) and b) the layout showing chip features Fig. 4-36: Measured pulses from the transmitter in the time domain (a, c) and their corresponding power spectral densities for a 1 MHz pulse repetition rate (b, d) Fig. 4-37: Measured spectrum of a pulse train with a 1 MHz repetition rate from the UWB transmitter Fig. 4-38: Measurement results of the transmitter connected to the receiver through a 33 db attenuator Fig. 4-39: Measured control voltage synchronization results for various initial control voltages Fig. 4-40: Measured pk-pk clock jitter vs. the number of consecutive 0 s Fig. 4-41: Picture of the BER measurement setup Fig. 4-42: Plot of the BER vs. the received signal power Ph.D. Thesis ix 2014 K. Allidina

10 Fig. 4-43: Measured S11 of the 300 MHz narrowband antenna Fig. 4-44: Measurement setup showing successful wireless communications with narrowband antennas Fig. 4-45: Measurement setup showing unsuccessful wireless communications with narrowband antennas Fig. 4-46: Passband of the digital filter superimposed on the S11 of the antenna Fig. 4-47: Plots of the amplitude vs. time for a) the output of the transmitter and b) the pulse shape at the receiver Fig. 5-1: Examples of temperature compensated sensor architectures based on a) a temperature sensor and a look-up table, b) a heater integrated with the sensor, and c) compensation using a reference sensor Fig. 5-2: Proposed temperature compensated sensor architecture Fig. 5-3: Capacitive humidity sensor alongside the reference capacitor used in the temperature compensation scheme Fig. 5-4: Plots of a) the minimum division ratio vs. T CF, and b) the worst case ΔTemp vs. T CF Fig. 5-5: The counter output vs. temperature at the extremes of the relative humidity range Fig. 5-6: The counter output vs. temperature for the case where a temperature insensitive clock is used as the reference oscillator Fig. 5-7: Measurements of a) the humidity sensor capacitance vs. relative humidity and b) the resulting sensitivity to humidity at a temperature of 25 C Fig. 5-8: Measurements of a) the humidity sensor capacitance vs. temperature and b) the resulting sensitivity to temperature at a relative humidity of 50% RH Fig. 5-9: Simulation results showing the accumulated counter output over 5 consecutive measurements vs. temperature Fig. 6-1: Possible implementation of the sensor interface architecture Ph.D. Thesis x 2014 K. Allidina

11 LIST OF ABBREVIATIONS ΔΣ ADC AWGN BER bps BPSK CDR CMOS DAC DFF DS-UWB E b / I 0 E b / N 0 FCC FD FD-SOI FPGA GPS IEC IEEE iid IIP3 IoT IR-UWB ISI ISM ISO J CC LNA LUT MB-OFDM MEMS NBI NRZ Delta-Sigma Analog to Digital Converter Additive White Gaussian Noise Bit Error Rate bits per second Binary Phase Shift Keying Clock and Data Recovery Complementary Metal-Oxide-Semiconductor Digital to Analog Converter D Flip-Flop Direct Sequence Ultra Wideband bit energy / interference power spectral density bit energy / noise power spectral density Federal Communications Commission Frequency Detector Fully Depleted Silicon on Insulator Field-Programmable Gate Array Global Positioning System International Electrotechnical Commision Institute of Electrical and Electronics Engineers independent and identically distributed Input-Referred Third Order Intercept Point Internet of Things Impulse Radio Ultra Wideband Intersymbol Interference Industrial, Scientific and Medical International Organization for Standardization Cycle-to-Cycle Jitter Low Noise Amplifier Look-Up Table Multiband Orthogonal Frequency Division Multiplexing Micro-Electromechanical Systems Narrow-Band Interference Non-Return-to-Zero Ph.D. Thesis xi 2014 K. Allidina

12 OFDM OOK PD PFD PG PPM QAC RF RH RMS RZ SIR SNR S-OOK TOA TR UWB VCO WPAN WSN Orthogonal Frequency Division Multiplexing On-Off Keying Phase Detector Phase / Frequency Detector Processing Gain Pulse Position Modulation Quadrature Analog Correlation Radio Frequency Relative Humidity Root Mean Square Return-to-Zero Signal to Interference Ratio Signal to Noise Ratio Synchronized On-Off Keying Time of Arrival Transmitted Reference Ultra Wideband Voltage Controlled Oscillator Wireless Personal Area Network Wireless Sensor Network Ph.D. Thesis xii 2014 K. Allidina

13 ABSTRACT This thesis focuses on the design of a low power ultra wideband (UWB) transceiver and a low power sensor interface architecture, both for use in wireless sensor networks. Pulse-based UWB radios communicate using short broadband pulses, which allow the transceiver to be duty cycled such that power is only consumed when a pulse is being transmitted or received. This enables increased power savings when compared to traditional narrowband transceivers. The receiver designed here is based on peak detection, and it is shown that this type of non-coherent receiver can perform better than a more complex energy detection receiver in interference dominated environments (such as urban areas) in both an additive white Gaussian noise channel, and a multipath environment. The fabricated UWB receiver uses a clock and data recovery system to synchronize the local receiver clock to the transmitted data to reduce synchronization time and enable more efficient communications for sensor networks, which typically have a small data payload. By moving the synchronization to the analog domain, the size and power consumption of the digital backend is reduced significantly when compared to other receiver architectures. The clock and data recovery synchronization scheme also provides real-time tracking of any variations in the transmitted data rate and the receiver clock, which minimizes the need for a high precision crystal reference in either system. The fabricated UWB transmitter is implemented by exciting a pulse shaping filter with a broadband pulse, and the resulting signal conforms to the FCC spectral mask including the GPS stopband. The demonstrated transceiver system achieves a sensitivity of dbm with a power consumption of ~400 μw at a 1 Mbps data rate, making it suitable for wireless sensor networks and other low power, low data rate systems. An architecture for an energy efficient sensor interface for frequency domain sensors is also presented. The proposed system produces a digital output with inherent temperature compensation without the need for a high accuracy temperature sensor, a heater, or a temperature insensitive clock. This architecture is targeted towards systems where the emphasis is placed on battery longevity as opposed to high resolution sensing, such as in wireless sensor nodes. Ph.D. Thesis xiii 2014 K. Allidina

14 ABRÉGÉ Cette thèse porte sur la conception d'un émetteur-récepteur faible puissance à bande ultra large (UWB) et d une architecture d'interface de capteur faible puissance, pour une utilisation dans les réseaux de capteurs sans fil. Les émetteurs-récepteurs UWB à impulsion communiquent à l'aide de courtes impulsions à large bande, qui permettent à l'émetteur-récepteur d être activé et désactivé de façon à ce que l'énergie soit consommée seulement lorsqu une impulsion est transmise ou reçue. Cela permet une augmentation des économies d'énergie par rapport aux émetteursrécepteurs classiques à bande étroite, qui comportent une porteuse. Le récepteur conçu ici est basé sur la détection de crêtes et il est démontré que ce type de récepteur non-cohérent peut faire mieux qu un récepteur de détection d'énergie plus complexe dans des environnements dominés par les interférences (comme dans les zones urbaines) à la fois au niveau d un canal à bruit blanc gaussien additif et d un environnement de propagation par trajets multiples. Le récepteur UWB fabriqué utilise un système de récupération d'horloge et de données pour synchroniser l'horloge locale du récepteur avec les données transmises pour réduire le temps de synchronisation et permettre des communications plus efficaces pour les réseaux de capteurs, qui ont généralement une faible charge utile de données. En déplaçant la synchronisation dans le domaine analogique, la taille et la consommation d'énergie des circuits numériques sont considérablement réduites par rapport à d'autres architectures de récepteur. Le régime de récupération d'horloge et de données fournit également un suivi en temps réel de toutes les variations dans le débit des données transmises par l émetteur et dans la fréquence d'horloge du récepteur, ce qui réduit la nécessité d'une référence fréquentielle de haute précision dans les deux systèmes. L'émetteur UWB fabriqué est mis en œuvre en excitant un filtre de mise en forme d'impulsions avec une impulsion à large bande et le signal résultant est conforme au masque spectral de la FCC, incluant la bande GPS à éviter. Le système d'émetteurrécepteur réalise une sensibilité de dbm avec une consommation d'énergie d'environ 400 µw à un débit de données de 1 Mbps, ce qui convient aux réseaux de capteurs sans fil et à d'autres systèmes à faible puissance et à faible débit de données. Ph.D. Thesis xiv 2014 K. Allidina

15 Une architecture d interface pour capteurs énergiquement efficace pour les capteurs dans le domaine fréquentiel est également présentée. Le système proposé produit une sortie numérique avec compensation de température inhérente sans l usage d un capteur de température à haute précision, d un dispositif de chauffage, ou d une horloge insensible à la température. Cette architecture est orientée vers les systèmes où l'accent est mis sur la longévité de la batterie plutôt que de la détection à haute résolution, comme dans les nœuds de capteurs sans fil. Ph.D. Thesis xv 2014 K. Allidina

16 Chapter 1 - Introduction Introduction 1.1 Motivation In the last few decades we have seen a proliferation of portable wireless communication devices from standard radios to mobile phones that allow you to talk to someone overseas and send an while ordering a coffee. This is due to the convenience offered by portable wireless devices, which allow us efficient access to (and control of) information on demand. There are a variety of standards in the wireless world, each with unique goals and specifications. For example, high throughput local area networking standards such as a/b/g/n allow seamless access to the internet, while standards such as Bluetooth and ZigBee offer lower data rate communications over a shorter range, and with lower power consumption. These short range technologies play a key role in achieving the vision of everything is connected, which is associated with the concept of the Internet of Things (IoT). One aspect of this idea that has experienced widespread interest in recent years is wireless sensor networks (WSNs). A wireless sensor network consists of multiple sensing devices, or nodes, that are capable of collecting and storing information about their surroundings. Typically, sensor nodes gather information over an interval of time and then periodically transmit the data to a base station for analysis. This functionality can provide us with unprecedented levels of information about our environment, which can be used to realize flexible and highly efficient systems. Example applications of WSNs include health care, environmental monitoring, agriculture, structural health monitoring, and optimized control over manufacturing processes [1-4]. The overall data rate requirement of WSNs is typically quite low (on the order of 100 kbps to 1 Mbps) due to the long time constant associated with many of the processes being sensed, however, the required lifetime of a sensor node can be quite long. In some cases these sensor nodes are deployed for years, necessitating cost effective designs with a focus on battery longevity. To achieve this goal, energy efficient transceivers are a necessity. Ph.D. Thesis K. Allidina

17 Impulse radio ultra wideband (IR-UWB) technology is a promising technology for this application, and it possesses desirable characteristics when compared to traditional narrowband systems. This form of communications sends information using a stream of narrow pulses with durations of nanoseconds or less. The transceiver circuitry only needs to be active when a pulse is being transmitted or received, and can otherwise be in a low power state to conserve energy. The use of IR-UWB technology in designing energy efficient wireless transceivers for short range, low data rate communications is the main subject of this thesis. 1.2 Background of Ultra Wideband Technology In principle, using ultra wideband (UWB) technology for communication actually dates back to the late 1800s when Marconi used the spark gap transmitter (developed by Hertz) for wireless transmission. This type of transmitter emits radio waves over a very wide bandwidth, albeit in an uncontrolled fashion. The lack of control in these broadband signals caused them to interfere with each other, leading to experimentation in generating continuous-wave sinusoids for radio transmission. By the time Fessenden made his famous broadcast on Christmas Eve in 1906, the advantages of narrowband radios for wireless communications were clear [5]. While wideband pulses of RF energy have been used in radar systems for several decades, the technology was not used for communications until the early 1990s [6-8]. In 2002 the Federal Communications Committee (FCC) authorized the use of UWB systems in the frequency ranges of MHz and GHz [9]. Since this spectrum was already occupied by pre-existing narrowband radio systems, the allowed UWB power levels are limited to the same order as unintentional radiators. The Equivalent Isotropically Radiated Power (EIRP) limit for the lower frequency band is dbm/mhz, and dbm/mhz in the upper frequency band. The emission mask is shown in Fig. 1-1, and it includes a stopband to avoid interference with sensitive global positioning system (GPS) radios. Ph.D. Thesis K. Allidina

18 -40 EIRP Emissions Level (dbm/mhz) GPS Band Frequency (GHz) Fig. 1-1: FCC emissions mask for ultra wideband communications. To be classified as an UWB system, the signal must either have a 10 db bandwidth that is greater than 500 MHz, or that is greater than 20% of the center frequency. The main advantage of UWB technology can be seen from Shannon s channel capacity formula, which is given by [10]: C = W log 2 (1 + SNR), (1.1) where C is the channel capacity in bits per second (bps), W is the bandwidth in Hz, and SNR is the signal to noise ratio. Essentially, this says that the capacity of a channel increases linearity with bandwidth, but only logarithmically with SNR. This means a wideband signal needs to transmit less power to achieve the same data rate as a traditional narrowband signal. Since the allowed transmit power is regulated by the FCC, ultra wideband systems are suitable for either high data rate communications over short distances, or low data rate communications over longer distances. To illustrate this, a plot of the channel capacity for an UWB signal with a 2 GHz bandwidth (in the 3.1 GHz 5.1 GHz band) vs. a narrowband signal with an 20 MHz bandwidth in the 2.4 GHz Industrial, Scientific, and Medical (ISM) band is shown in Fig The power of the UWB signal is -20 dbm (10 µw), the power of the Ph.D. Thesis K. Allidina

19 narrowband signal is 0 dbm (1 mw), and channel models for a typical indoor environment were used [11]. It is clear that over short distances, the UWB signal has a much higher channel capacity, even though the transmitted power is orders of magnitude lower. As the distance increases, the higher noise floor of the UWB signal causes the channel capacity to drop quicker than for the narrowband signal Channel Capacity (Mbps) Ultra Wideband Narrowband Distance (m) Fig. 1-2: Link capacity vs. distance for an ultra wideband and narrowband system, both in the range of 2.4 GHz. The IEEE established two task groups to develop Wireless Personal Area Network (WPAN) standards for the physical layer in UWB systems one responsible for high data rate applications (IEEE a), and one responsible for low data rate applications (IEEE a). The IEEE a task group debated over two different proposals to establish high data rate communications over short distances: Direct-Sequence UWB (DS-UWB) and Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM). The DS-UWB proposal advocated the use of short, broadband pulses transmitted with a fast repetition rate to achieve high data rate communications. In contrast, the MB-OFDM proposal was based on splitting the allotted spectrum into multiple sub-bands and using OFDM (as used in the WLAN a/g/n standards, for example) to modulate the signal. By Ph.D. Thesis K. Allidina

20 rapidly hopping between the sub-bands, compliance with the FCC emission requirements could be met while providing high data rate communications. Unfortunately, the task group failed to decide on a proposal, and was disbanded in However, the MB-OFDM standards Ecma 368 and 369 were later accepted as ISO / IEC standards [12]. The IEEE a task group was more successful, and established a physical layer for the use of UWB in low-cost and low-power wireless connectivity over distances of up to 20 m. This standard employs IR-UWB techniques, and the short pulses allow ranging capabilities (i.e., measuring the distance between nodes) in addition to communications. For example, using pulses with a duration of less than 3 ns can enable accurate ranging estimations with less than 1 m of spatial uncertainty using time of arrival (TOA) techniques [13]. A compliant system is required to support a data rate of 851 kbps, and optional data rates range between 110 kbps and Mbps [14]. This physical layer was amended to the standard (which includes ZigBee) in 2007 [15]. 1.3 Advantages and Challenges of IR-UWB Technology As has been discussed, using short broadband pulses for communication offers unique advantages as compared with narrowband systems. The large bandwidth of these pulses allows for a higher throughput with lower signal power over short distances, and since the emitted energy is limited to that of an unintentional radiator, interference with existing narrowband systems is unlikely. (This second point also makes UWB communications hard to detect, which is of interest to military applications.) The short duration of the pulses enables power savings since the transceiver only has to be on when a pulse is being sent or received, and also enables ranging and localization between UWB systems. The short pulse duration also provides immunity to multipath cancelation caused by destructive interference between direct and reflected signal paths in continuous wave communications. Of course, these advantages come with implementation issues that must be addressed to realize a fully functional system. One such issue is synchronization. In order to properly receive the transmitted data, the receiver must be synchronized to the transmitted pulse. The short duration and low power of the pulses make the initial detection and synchronization a challenging task. Ph.D. Thesis K. Allidina

21 This problem is exacerbated at low data rates where the duty cycle of the pulses is very small. For example, if a 1 ns pulse is sent with a 1 μs repetition rate, the pulse energy only exists for 0.1% of the period! Synchronization becomes even more complicated when clock jitter and frequency offsets between the transmitter and receiver are taken into account. The ability to quickly synchronize the receiver to the incoming data is especially relevant for wireless sensor networks since the data payload is typically small. In this type of application acquisition / synchronization phase can take a significant portion of each communication sequence [16, 17]. Consider a wireless sensor network node monitoring temperature and humidity, which can typically each be represented by less than 16 bits of data. This, combined with identification and location information, will typically need a packet with a length of ~50 bits. Thus, a synchronization preamble of even 50 bits will halve the efficiency of the communication scheme. Another issue is interference from existing wireless services. While it is true that UWB emission levels are low enough to prevent them from interfering with existing narrowband systems, the reverse cannot be said. The wide bandwidth of UWB systems basically ensures that narrowband signals will corrupt the UWB signal to some extent. In fact, measurements have shown that in urban environments, the average narrow-band interference (NBI) power from existing services is orders of magnitude higher than the nose floor [18, 19]. An example of common existing wireless services in the MHz UWB band is shown in Fig. 1-3 to give an idea of the interference that must be tolerated by an UWB receiver [20]. It can be seen that the spectrum is already quite crowded! Ph.D. Thesis K. Allidina

22 -40 Cordless / Cell Phones ISM Band PSD (dbm/mhz) MHz ISM Band Navigation Signals Mobile Comm. FM Radio Satellite Comm. VHF TV UHF TV Frequency (GHz) Fig. 1-3: Common existing wireless services in the MHz UWB band. Lastly, there are general implementation issues that cause non-optimal performance. Designing circuits to make full use of the desirable properties in UWB communications is a challenging task. On the transmitter side, occupying the full bandwidth allowed by the FCC spectral mask while still meeting the out-of-band attenuation levels would require ideal brick-wall filters. Since this is not possible, effort has gone into mathematically synthesizing a pulse shape that meets the spectral mask while maximizing the bandwidth. Solutions include using n th order derivatives of a Gaussian monocycle [21], using a Sholtz monocycle [22], or using digital filters with carefully optimized coefficients [23]. However, the large bandwidth of an UWB pulse makes designing the necessary transmitter circuitry to take these pulses from the mathematical domain to the physical domain very complicated. A digital to analog converter (DAC) with the necessary bandwidth (>1 GHz) and high-speed sampling clock would require high power consumption, and would negate some of the benefits of using short pulses for energy efficient communications. In practice, circuitry to realize approximations of optimal pulse shapes are implemented, as will be discussed in Chapter 2. Despite these issues in implementing an UWB transmitter, the receiver is viewed as the more challenging part of the communications link [24, 25]. The optimal UWB architecture would use a coherent receiver that correlates the received pulse with the expected pulse shape. This type of receiver requires very accurate timing and precise Ph.D. Thesis K. Allidina

23 synchronization, and additionally, the group delays associated with the antennas and circuits make the expected pulse shape uncertain [26]. As well, multiple signal paths between a transmitter and receiver exist due to the transmitted signal being reflected from various surfaces (e.g., the ground, walls, etc.), and interference between echoes and the main signal can also cause distortion of the pulse shape [11, 27, 28]. Channel estimation techniques are required to compensate for these effects, at the expense of increased system complexity [27, 28]. A RAKE receiver can be used to improve performance by capturing these echoes with properly timed multiple reception paths, but again, accurate channel estimation is required [29]. Since the number of multipath components in UWB systems can be large and the power contained in each component is very low, channel estimation a non-trivial task [28]. The implementation complexity required to create an optimal coherent UWB transceiver results in systems with high power consumption, and one that is not well suited to wireless sensor networks. Non-coherent receivers based on either energy or peak detection are preferred for these low power applications [30-34], as will be discussed in Chapter Research Goal The goal of this work is to design and implement a low power, low data rate IR-UWB transceiver suitable for wireless sensor networks. This design will be focused on applications in interference dominated environments such as urban centers, and an emphasis will be placed on reducing the time needed to synchronize the receiver to the incoming data to minimize the overhead associated with a lengthy preamble. The target average power consumption for the transceiver is under 500 μw with a data rate of 1 Mbps, and the desired communications distance is ~5 m. These specifications are to be achieved with a full transceiver e.g., no external field-programmable gate array (FPGA) or other off-chip digital processing should be needed in the receiver to convert the RF input signal into a digital output. Before proceeding, it is instructive to take a look at what has been achieved with low power narrowband receivers designed for low data rate applications. A plot of the power consumption vs. data rate for recent narrowband receivers encompassing various Ph.D. Thesis K. Allidina

24 standards is shown in Fig. 1-4, with numerical details given in Table 1-1. This comparison includes existing products from commercial companies, as well as receivers from the literature. Note that receivers from the literature have a few advantages when it comes to power consumption since they generally do not include regulators, and can function from a very low voltage supply. For instance, the receiver in [35] functions from a 300 mv supply. Commercial receivers are generally designed to accept minimum supply voltages of 1.8 V to be compatible with end-user systems, which impacts the power consumption Power Consumption (mw) Bluetooth Bluetooth Low Energy / ZigBee Commercial ISM Research Desired Performance Data Rate (kbps) Fig. 1-4: Power consumption vs. data rate for recent narrowband receivers. The receivers in [36] and [37] operate near the desired performance area, however, the stated power consumption is just for the receiver. Out of these works, the transmitter in [36] achieves a lower power consumption, but it still requires 700 μw to generate a -8.5 dbm signal. While reduced output power would be acceptable for short-range links (e.g., less than 5 m), the requirement of an always-on voltage controlled oscillator (VCO) to generate the narrowband signal puts a limit on how low the power consumption can go. For example, the VCO in [36] consumes 160 μw, which places the power consumption Ph.D. Thesis K. Allidina

25 of the transceiver at 490 μw without even considering the transmitter s power amplifier. In contrast, the pulsed nature of an UWB signal allows duty cycling of the transmitter, which results in power savings. As will be seen later, UWB transmitters operating below 50 μw have been implemented and for use in short range wireless links [38-40]. Table 1-1: Summary of Recent Low Power, Low Data Rate Narrowband Receivers Type of Receiver Data Rate Power Consumption Reference 1 Mbps 35.6 mw ISSCC 2008 [41] Bluetooth 1 Mbps 32.5 mw ISSCC 2008 [42] 1 Mbps 59.0 mw ISSCC 2005 [43] 1 Mbps 22.0 mw ISSCC 2001 [44] 1 Mbps 23.4 mw Commercial (Nordic Semiconductor) [45] Commercial Bluetooth Low 1 Mbps 12.8 mw (Dialog Semiconductor) [46] Energy Commercial 1 Mbps 14.6 mw (ST Microelectronics) [47] 1 Mbps 1.1 mw MTT 2013 [48] 250 kbps 26.5 mw ISSCC 2006 [49] 250 kbps 32.4 mw ASSCC 2007 [50] / ZigBee 250 kbps 39.5 mw Commercial (Texas Instruments) [51] 250 kbps 9.45 mw Commercial (Linear Technology) [52] 76.8 kbps 20.2 mw Commercial Commercial ISM (Custom Standard) Research (Custom Standard) (Texas Instruments) [53] 115 kbps 8.4 mw Commercial (RF Monolithics) [54] 66 kbps mw Commercial (Maxim Semiconductor) [55] 500 kbps 330 μw JSSC 2006 [36] 500 kbps 2.8 mw JSSC 2007 [56] 50 kbps 2.1 mw JSSC 2008 [57] 1 Mbps 530 μw ISSCC 2011 [37] 200 kbps 1.6 mw ISSCC 2013 [35] In summary, the system designed in this thesis will exploit the advantages of UWB technology while proposing methods of resolving associated challenges to implement a complete transceiver for low power and low data rate wireless links. Ph.D. Thesis K. Allidina

26 While the main goal of the research described in this thesis is to implement a low power transceiver, energy efficient circuits are also needed to interface with the sensors in each wireless node and convert their output into a digital signal for wireless transmission. A secondary goal of this research is to investigate energy efficient architectures to interface with frequency domain sensors. 1.5 Contributions The main contributions of this work are described in the following subsections The Design of a Low Power LNA for UWB Systems The first block of any wireless receiver is generally a low noise amplifier (LNA). This circuit is responsible for amplifying the incoming signal with minimal degradation to the SNR, and a properly designed LNA reduces the impact of noise contributions from all subsequent stages. Significant effort has been spent optimizing the design methodology for LNAs in conventional narrowband systems, however, ultra wideband LNAs require different topologies and design trade-offs. A new topology for an UWB LNA that is capable of providing a wideband impedance match to the antenna, a low noise figure, and operation with sub-mw power consumption was proposed and implemented [58, 59]. The contributions associated with this LNA are: K. Allidina and M. N. El-Gamal, "A 1V CMOS LNA for low power ultra-wideband system," EEE International Conference on Electronics, Circuits, and Systems (ICECS), pp , Sept T. Tsang, K.-Y. Lin, K. Allidina, and M. N. El-Gamal, "Low Power UWB Circuits: Front-End Building Blocks," in Circuits and Systems for Future Generations of Wireless Communicatoins, A. Tasic, W. A. Serdijn, L. E. Larson, and G. Setti, Eds., Netherlands: SpringerLink, 2009, pp Analysis of Non-Coherent UWB Systems in the Presence of Noise and Interference While an optimal UWB receiver is based on a coherent receiver structure, non-coherent receivers are preferred in low power applications such as wireless sensors networks due to their simplicity, increased energy efficiency, and less stringent timing requirements. The most common non-coherent receiver architectures are energy detectors and peak detectors. Energy detectors provide a higher level of performance in the presence of Ph.D. Thesis K. Allidina

27 noise since a peak detector only uses a portion of the signal energy, however, the analysis performed in this work shows that peak detectors can perform better in interference dominated environments, and at the same time, lead to simpler systems [60]. This situation is especially relevant in UWB communications where the signals from existing narrowband transceivers cannot be filtered without also attenuating the desired signal. The contribution associated with this work is: K. Allidina, T. Khattab, and M. N. El-Gamal, "On Dual Peak Detection UWB Receivers in Noise and Interference Dominated Environments," submitted for publication as a journal paper, July The Design of a Low Power UWB Transceiver with a Fast and Low Complexity Synchronization Scheme The results that an UWB receiver based on peak detection can perform better than an energy detection receiver in interference dominated environments is used to design a low power UWB receiver with a fast and low complexity synchronization scheme [61-63]. The synchronization scheme is based on a clock and data recovery (CDR) system, which has numerous advantages. Along with reduced synchronization time, this method enables continuous compensation for any jitter associated with either the transmitted data or receiver clock, which relaxes the timing requirements of both systems. This minimizes the need for a high accuracy crystal reference in the transmitter and receiver, leading to a lower cost solution. Additionally, a signal capable of duty-cycling the RF front-end is readily derived from the synchronized receiver clock, which results in a significant power reduction. As will be seen, many published UWB receivers require an off-chip FPGA to perform the synchronization and duty-cycling operations, whereas the system proposed here implements these functions on-chip. A low power transmitter is also designed as part of this work [61-63], and the generated UWB pulses contain higher energy than other comparable works while still meeting the FCC spectral mask. This is an advantage because the ability to generate pulses with higher energy allows wireless communications over a longer distance. Ph.D. Thesis K. Allidina

28 The contributions associated with this transceiver are: K. Allidina and M. N. El-Gamal, "A compact and low power UWB transceiver with a fast synchronization scheme," Presented at IEEE International Solid State Circuits Conference, Student Research Preview, Feb K. Allidina and M. N. El-Gamal, "A compact and low power UWB transceiver with a fast and low complexity synchronization scheme," submitted for publication as a journal paper, July M. Parvizi, K. Allidina, and M. N. El-Gamal, "Ultra-Low Power RF Systems and Building Blocks," in Wireless Transceiver Circuiots: System Perspectives and Circuit Aspects, W. Rhee and K. Iniewski, Eds.: CRC Press, to be published, A Temperature Compensated Architecture for Integrated, Low Power, Frequency Domain Sensors The main focus of the research described in this thesis is to implement a low power transceiver for wireless sensor networks since this is the largest power consumer in each sensor node. However, energy efficient circuits are also needed to interface with the sensors and convert their output into a digital signal for wireless transmission. A system architecture that interfaces with frequency domain sensors (e.g., resonant sensors or oscillators based on capacitive sensors) is proposed, and it produces a digital output with inherent temperature compensation without the need for a high accuracy temperature sensor or a temperature insensitive clock to perform the time-to-digital conversion [64]. This has the advantage of enabling a sensing system with lower power, and lower complexity. The contribution associated with this work is: K. Allidina, T. Saha, and M. N. El-Gamal, "A temperature compensated architecture for integrated, low power, frequency domain sensors," IEEE International Conference on Microelectronics, pp , Dec Related Contributions The reader may also be interested in following contributions that are related to the subject matter of this thesis: The following works relate to the design of sub-mw LNAs for UWB systems. In both works, the author s contribution was advice on the circuit analysis, design and layout techniques to meet the required power and performance goals. Ph.D. Thesis K. Allidina

29 M. Parvizi, K. Allidina, F. Nabki, and M. El-Gamal, "A 0.4V ultra low-power UWB CMOS LNA employing noise cancellation," IEEE International Symposium on Circuits and Systems, pp , May M. Parvizi, K. Allidina, and M. N. El-Gamal, "A sub-mw, ultra-low-voltage, wideband low-noise amplifier design technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 pages, accepted for publication, In the following work, a low power frequency-to-voltage converter for a resonant vacuum sensor was designed. The author s contribution was the system-level design and simulation, as well as the design of all of the associated analog circuitry. K. Allidina, M. A. Taghvaei, F. Nabki, P. V. Cicek, and M. N. El-Gamal, "A MEMS-based vacuum sensor with a PLL frequency-to-voltage converter," IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp , Dec In the following two publications, a temperature compensated sensor interface for resonant vacuum sensors is described. The author s contribution was to design the analog circuitry required to interface with the MEMS resonators, as well as help with system integration. M. A. Taghvaei, P.-V. Cicek, K. Allidina, F. Nabki, and M. N. El-Gamal, "A MEMS-based temperature compensated vacuum sensor for low-power monolithic integration," IEEE International Symposium on Circuits and Systems, pp , Jun M. A. Taghvaei, P. V. Cicek, K. Allidina, F. Nabki, and M. N. El-Gamal, "A 0.13-μm CMOS interface circuit for a MEMS resonator-based vacuum measurement system," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, pp , Dec Thesis Outline This thesis is organized as follows: Chapter 2 presents an overview of UWB signals and modulation techniques, followed by an overview and literature review of UWB transmitters and receivers. An emphasis is placed on systems and implementations that are targeted towards low power, low data rate applications. Chapter 3 presents an analysis of UWB receivers based on energy and peak detection in the presence of noise and interference. Theoretical expressions are derived, and simulations are performed both in additive white Gaussian noise (AWGN) and multipath channels. Chapter 4 presents the design and implementation of a complete UWB transceiver. The receiver is based on peak detection and implements a fast synchronization scheme that is capable of duty-cycling the RF front-end. The transmitter is capable of generating UWB pulses with Ph.D. Thesis K. Allidina

30 a higher energy that other works, while still meeting the FCC spectral mask. Chapter 5 presents a system architecture for frequency domain sensors that produces a digital output and has inherent temperature compensation without the need for a high accuracy temperature sensor. Chapter 6 concludes the thesis with a summary of the main results and a discussion on how this research can be extended. Ph.D. Thesis K. Allidina

31 Chapter 2 Overview of UWB Systems Overview of UWB Systems 2.1 Introduction This chapter provides an overview of IR-UWB communications. A description of modulation techniques will be covered first, and the focus will be on schemes that are applicable to low power, low data rate, and low complexity communications. Various methods of generating the IR-UWB pulse will then be discussed, followed by a literature review of UWB transmitters that have been implemented. Both coherent and non-coherent receiver architectures will then be described, along with the associated trade-offs. A literature review of implemented UWB receivers will then be presented. The chapter will conclude with a discussion of the proposed architecture based on the presented overview. 2.2 IR-UWB Modulation Techniques A number of modulation techniques that are compatible with pulse-based UWB systems can be found in the literature. The most straightforward modulation formats in terms of implementation are on-off keying (OOK), pulse position modulation (PPM), binary phase shift keying (BPSK), and transmitted reference (TR) [11]. It is also possible to modulate the shape of the pulse itself to represent information bits using orthogonal basis functions [27], but this significantly increases the transmitter and receiver complexity. As this work is focused on low complexity energy efficient implementations, the details of this modulation method will not be covered here. Examples of OOK, PPM, BPSK, and TR modulations are shown in Fig These modulation schemes represent the information as follows: OOK modulation: A 1 is represented by the presence of a pulse, and a 0 is represented by the absence of a pulse (Fig. 2-1a). Ph.D. Thesis K. Allidina

32 PPM modulation: The position of the pulse within a data frame indicates whether a 1 or 0 is transmitted (Fig. 2-1b). BPSK modulation: The phase of the pulse is used to indicate whether a 1 or 0 is transmitted (Fig. 2-1c). TR Modulation: A reference pulse is sent prior to the data pulse and is used as for comparison. If the data pulse is equal to the reference pulse, it is interpreted as a 1. If the data pulse is antipodal to the reference pulse, it is interpreted as a 0. The sequence is shown in Fig. 2-1d (a) (b) (c) REF DATA (d) Fig. 2-1: Waveforms showing how data is modulated using a) on-off keying, b) pulse-position modulation, c) binary phase shift keying, and d) transmitted reference. Since OOK modulation only sends a signal when there is a 1, for a 50% average data density (50% 1 s and 50% 0 s) the power in each pulse can be twice as high as PPM or BPSK while still meeting FCC regulations. However, since information is not sent in every data period, this type of modulation is not particularly suited for coherent receivers. Additionally, long runs of 0 s can degrade synchronization. PPM and TR modulation both have the advantage of enabling differential-based signaling to cancel out channel noise and interference. In PPM systems, this can be achieved by comparing the energy in the two positions where a pulse is expected. If the energy in the Ph.D. Thesis K. Allidina

33 first position is higher, a 1 is received, and if the energy in the second position is higher, a 0 is received. In TR systems, the reference signal can be compared directly to the data signal though a correlator, however, implementing this has challenges as will be discussed later in this chapter. Both of these modulation formats also suffer a drop in efficiency since the receiver has to be active twice every data period instead of just once. In addition to this TR modulation needs to send two pulses in each data period, which doubles the transmit power. BPSK systems have an inherent 3-dB advantage over OOK and PPM systems due to the increased spacing between constellation points, and, like OOK, the receiver only needs to be active once per data period. However, since the data is transmitted using the phase of the pulse, this type of modulation requires a coherent receiver for optimal detection. This adds significant complexity to the receiver, as will be discussed later in this chapter. 2.3 Ultra Wideband Transmitters As mentioned earlier, UWB transmitters can be very efficient since the transmitter only needs to consume power when a pulse needs to be transmitted. Additionally, if the proper pulse shape is synthesized directly, an UWB transmitter has no need for conventional RF circuits such as mixers or filters, and is primarily a digital circuit. Of course, this becomes challenging when it comes to implementation. Approaches that are easier to implement include upconverting a baseband pulse with the desired spectral shape to the correct frequency band using an RF mixer or exciting a filter that has the appropriate response with a broadband pulse. It is also possible to create a pulse in the digital domain and use a high-speed DAC to generate the actual signal, but this is very difficult to implement in an energy efficient fashion. A suitable IR-UWB pulse can be any function that satisfies the FCC spectral mask. Amongst the most common UWB pulses are the Guassian pulse, Guassian monocycle, and the Scholtz waveforms [11, 22, 27]. These pulses are preferred as opposed to a rectangular or cosine shaped pulses because their spectrums have lower sidelobes, and are therefore better suited to meet the FCC spectral mask. The waveform of a Guassian pulse is given by the equation [27]: Ph.D. Thesis K. Allidina

34 2 1 t µ 2 σ 1 p G ( t) = e, (2.1) 0 2πσ where μ is the center of the pulse, and σ is a scaling factor related to the width of the pulse. The first derivative of the Guassian pulse is referred to as the Gaussian monocycle [65], which can be described by the equation: 2 1 t µ 2 σ t µ p G ( t) = e. (2.2) 1 2πσ The Scholtz monocycle was initially proposed by Scholtz and his group in the early 1990 s [6], and is similar to the second derivative of the Guassian pulse. The waveform is given by the equation [22]: 2 t µ 2π σ 2 t µ p SCHOLTZ ( t) = 1 4π e. (2.3) σ The Guassian pulse, Guassian monocycle, and Scholtz monocycles are shown in the time and frequency domain in Fig Each pulse has a duration of around 3 ns, and it can be seen that with each derivative, the roll-off is steeper and the baseband energy is reduced. With minor modifications, all of these pulses can be suitable for use in the MHz UWB band, and of course, all can be upconverted for use in the GHz band. Higher order derivatives of a Guassian pulse can be used to directly meet the FCC requirements in the GHz band, and this type of pulse will be shown when reviewing examples of implemented UWB transmitters. Ph.D. Thesis K. Allidina

35 1 0.5 Amplitude Time (ns) (a) Guassian Pulse Gaussian Monocycle Scholtz Monocycle Guassian Pulse, BW = 500 MHz Guassian Monocycle, BW = 940 MHz Scholtz Monocycle, BW = 780 MHz Power Spectral Density Fig. 2-2: Plots of the (a) time and (b) frequency domain characteristics of common IR-UWB pulses. The most common topologies of implementing pulse generators in hardware are to: Directly implement a pulse that will meet the FCC spectral mask (shown in Fig. 2-3a). Filter the output of a broadband pulse generator to create the UWB pulse (shown in Fig. 2-3b) Freuqency (GHz) (b) Ph.D. Thesis K. Allidina

36 Generate a baseband pulse with the appropriate bandwidth and upconvert it to the desired frequency band (shown in Fig. 2-3c). Create the pulse in the digital domain and use a high-speed DAC to generate the UWB pulse (shown in Fig. 2-3d). Data in Direct UWB Pulse Generator RF out Data in Broadband Pulse Generator Pulse Shaping Filter RF out (a) (b) Mixer Data in Baseband UWB Pulse Generator RF out (c) VCO Data in Digital Pulse Generator High Speed DAC RF out (d) Fig. 2-3: Common topologies for IR-UWB transmitters. Generally, a driver to interface the pulse generator output to the 50 Ω antenna is needed, but the low emitted power restrictions make a full power amplifier unnecessary [66]. The following sections will review the performance of various types of pulse generators in the literature. The text will focus on describing the architectural techniques used, after which summary tables with detailed performance metrics will be provided and discussed Direct Generation of an UWB Pulse When directly generating the UWB pulse for the GHz UWB band, the most common method is to use a 5 th to 7 th order derivative of a Gaussian pulse [21, 67-69]. As seen when discussing common pulse shapes, each derivate reduces the baseband energy and increases the spectral roll-off. By using higher order derivatives of the Gaussian, a pulse shape that meets the FCC spectral mask can be designed directly. An example of a 5 th order Gaussian pulse and the corresponding spectrum is shown in Fig Ph.D. Thesis K. Allidina

37 1-40 FCC Mask Amplitude PSD (dbm / MHz) Time (ns) Frequency (GHz) Fig. 2-4: Waveforms of a 5 th order Gaussian pulse in the time and frequency domain. In [67], the pulse generation is accomplished by first approximating a Guassian pulse with a triangular wave and then passing it through a cascade of 5 passive RC differentiators. This is a direct implementation of the mathematical functions that produce the 5 th order derivative. In contrast, the approach taken in [68, 69] to generate a 5 th order Guassian pulse is to generate multiple Gaussian pulses with varying phases and combine the waveforms to approximate the 5 th order derivative. To decrease the static power consumption, the individual pulses are generated using digital circuits with controlled rise and fall times. An UWB pulse suitable for the MHz UWB band is generated directly in [70]. To perform this operation, 8 digital drivers with controlled rise and fall times are used to generate a Guassian monocycle (1 st order derivative of a Gaussian waveform) UWB Pulse Generation by Filtering a Broadband Pulse Using a pulse shaping filter after a broadband pulse generator simplifies the timing and precision required to generate the pulse directly since the filter is used to attenuate unwanted signal components. Typically, the broadband pulse is either a short rectangular or triangular pulse. The generator in [39] uses both positive and negative rectangular pulses followed by a filter to generate BPSK pulses for the MHz band. In [40], a transmitter that is capable of operating in the MHz and the GHz band is presented. This circuit generates very short glitches which are combined to approximate a Gaussian monocycle which nominally has most of its energy in the GHz range. An external Ph.D. Thesis K. Allidina

38 band-pass filter is then used to shape this pulse to meet spectral requirements. To generate a pulse that is compatible with the MHz band, the supply voltage of the transmitter is reduced to increase the width of the glitches. In this mode of operation the external bandpass filter is not used. An example of a system that uses a triangular pulse followed by a pulse shaping filter to smooth out the signal is given in [71]. The triangular pulse decreases the sidelobe energy in the frequency domain and relaxes the requirements of the pulse-shaping filter. However, this technique results in a pulse that contains less energy UWB Pulse Generation by Upconverting a Baseband Pulse Upconverting the spectrum of a baseband pulse is a useful technique for transmitters operating in the GHz band. Since the frequency of the upconverting oscillator can be easily tuned, this technique is also well suited to generate pulses at different center frequencies to enable band-hopping. This technique can be used for interference reduction or multi-user access, and examples will be seen when UWB receivers are reviewed. The transmitter in [72] generates a 4 ns wide rectangular pulse and upconverts it using a tunable oscillator. This signal is then multiplied by a triangular wave to reduce the sidelobes of the spectrum, and a pulse-shaping filter is included to limit the bandwidth to 528 MHz. A tunable oscillator allows tuning of the center frequency from GHz to enable band-hopping. This ring oscillator has a fast startup time so its operation can be duty-cycled to reduce power consumption. The same pulse generation scheme is used in [38], although the ring oscillator is replaced with an LC oscillator with signals to kick-start the oscillation for a fast startup time. A similar implementation was used in [73], however, the rectangular pulse was not multiplied by a triangular waveform. This does yield a pulse with higher energy, but the resulting sidelobes in the frequency domain are also higher, and an external filter would be needed for this transmitter to be compliant with the FCC spectral mask. To illustrate the importance of the triangular shaping, an example of both a triangular and rectangular pulse and their corresponding spectrums are shown in Fig Both pulses Ph.D. Thesis K. Allidina

39 are 2 ns wide and have been upconverted by a 4.5 GHz sinusoid. The steeper roll-off of the triangular pulse can clearly be seen in the frequency domain. Amplitude Time (ns) PSD (dbm / MHz) -40 FCC Mask Frequency (GHz) Fig. 2-5: Waveforms of an upconverted triangular and square baseband pulse in the time and frequency domain Digital Pulse Generation with a Digital-to-Analog Converter By using digital techniques, pulse shapes that make very efficient use of the allotted UWB spectrum can be realized. In [74], numerical techniques based on sampling the spectral mask are used to obtain orthogonal pulses that are more efficient than Gaussian derivatives. However, the resulting pulse shapes require a sampling rate of 64 GHz, which is infeasible for energy efficient transmitters. An approach to synthesize an UWB pulse based on FIR filters is proposed in [23]. This technique uses second order cone programming to find an optimal pulse shape that achieves an impressive 92.16% spectrum utilization while still having sidelobes that meet the out-of-band attenuation constraints. However, the sampling rate required in a DAC to produce this pulse is 24 GHz, which is still too high for energy efficient transmitters. An example of a transmitter that stores a baseband pulse shape in digital memory and then upconverts the output of the DAC is given in [66]. This reduces the required sampling frequency to 2 GHz, but the transmitter still consumes over 100 mw. While the use of digital template pulses do have advantages in terms of spectral efficiency and pulse shape configurability, implementation issues currently prevent them from being an option in low power transceivers. Ph.D. Thesis K. Allidina

40 2.3.5 Comparison of Implemented UWB Transmitters Before comparing the implemented UWB transmitters that have just been described, it is important to discuss how the performance of these circuits is evaluated. A pulse-based UWB transmitter is essentially a time-domain circuit that must conform to regulations in the frequency domain, which can make finding a comparison metric tricky. The most common comparison metric found in the literature is the energy / pulse, which is the total transmitter power divided by the pulse repetition rate. However, this metric does not consider the energy contained in each pulse. As an example, consider the pulse trains shown in Fig. 2-6 which have the same power spectral densities, but different repetition rates. Since the 100 MHz pulse train has twice as many pulses as the 50 MHz train, its amplitude must be 2 times smaller to meet the FCC spectral mask. Amplitude MHz Pulse Train 100 MHz Pulse Train Time (ns) PSD (dbm / MHz) -40 FCC Mask MHz Pulse Train 100 MHz Pulse Train Frequency (GHz) Fig. 2-6: Pulse trains with the same power and different repetition rates. If we neglect DC power consumption, we can see that both transmitters will have the same power consumption. However, since the higher repetition rate transmitter emits more pulses, the energy / pulse metric will make it appear more efficient. The energy / pulse metric can become an even more unfair comparison if the pulse trains have different energies. For example, consider the pulse trains in Fig In this case the higher data rate transmitter will have a lower energy / pulse metric even though the pulses themselves contain much lower energy. Ph.D. Thesis K. Allidina

41 Amplitude MHz Pulse Train 100 MHz Pulse Train Time (ns) PSD (dbm / MHz) -40 FCC Mask MHz Pulse Train 100 MHz Pulse Train Frequency (GHz) Fig. 2-7: Pulse trains with the different powers and repetition rates. Adding in the DC power consumption creates additional issues when comparing transmitters with different data rates. The DC energy of a transmitter operating at 100 MHz will have much less effect on the energy / pulse than that of a transmitter operating at 10 kbps since the DC energy is amortized over a larger number of pulses. For these reasons, the following efficiency metric should be used [71, 75]: E η P E =, (2.4) EC where E P is the energy in a transmitted pulse, and E C is the energy consumed by the transmitter to generate the pulse. Since many papers do not report the energy contained in each pulse, this can be approximated by assuming a pulse is equal to a sinusoidal monocycle. This gives the relation [71]: E P V T 2R MAX 0 =, (2.5) L where V MAX is the peak voltage, T 0 is the pulse duration, and R L is the load resistance. This approximates a sine wave that is gated with a rectangular waveform, and will typically result in slightly more energy than is actually present in a pulse that meets FCC regulations, so the approximation will be used even if the actual pulse energy is reported such that a fair comparison can be made. A comparison of transmitters that operate in the GHz band is shown in Table 2-2, and a comparison of transmitters in the MHz band is shown in Table 2-3. Plots of the power consumption and energy efficiency vs. the pulse repetition Ph.D. Thesis K. Allidina

42 rate are shown in Fig. 2-8 and Fig. 2-9, respectively. It can be seen that the average power for UWB transmitters can be quite low. Fig. 2-8 shows that at low pulse repetition rates (< 1 MHz), it is possible to operate below 50 µw in the GHz band and below 10 μw in the MHz band. Fig. 2-9 shows that the energy efficiency for transmitters in the GHz band is under 5%, and typically under 1%. The efficiency in the MHz band is typically higher, and is seen to approach 10% in one case. This metric shows the general trend of increasing as the repetition rate is decreased. Note that the most energy efficient transmitter may not always be the best for a particular application. In the GHz band the transmitter in [40] has the highest efficiency, but the transmitters in both [38, 73] produce pulses that contain higher energy. This same case can be seen in the MHz band where [40] is more efficient, but [39] produces a pulse with more energy. Since a higher pulse energy will allow for a longer communications distance, this may be more important than the transmitter efficiency in some applications. In terms of the method of pulse generation, these works indicate that transmitters based on filtered broadband pulses or upconverted baseband pulses have a higher efficiency and higher pulse energy than directly generating the UWB pulse. Ph.D. Thesis K. Allidina

43 Table 2-2: Comparison of Recent Transmitters that Operate in the GHz UWB Band. [68] (2008) [69] (2005) [67] (2013) [71] (2010) [40] (2012) [72] (2008) [38] (2010) [73] (2011) Technology (CMOS Node) 0.18μm 0.5μm 90nm 90nm 0.13μm 0.18μm 90nm 90nm Type of Transmitter Direct Pulse Gen. Direct Pulse Gen. Direct Pulse Gen. Filtered Broadband Pulse Filtered Broadband Pulse Upconverted Baseband Pulse Upconverted Baseband Pulse Upconverted Baseband Pulse Center Frequency (GHz) 7 * to to to dB Bandwidth (MHz) 7000** * Pulse Amplitude (mv pk-pk) Pulse Width (ns) Repetition Rate 100MHz 20MHz 200MHz 1MHz 1MHz 30MHz 100kHz 1MHz Power Consumption (@ Repetition Rate) 3.6mW 1.16mW 19.2mW 19.1mW 31μW 260μW 8μW 258μW Energy / Pulse (@ Repetition Rate) 36pJ 58pJ 96pJ 19nJ 31pJ 8.67pJ 80pJ 258pJ Pulse Energy (pj) Energy Efficiency % 0.22% 0.33% 2.6% 4.1% 0.91% 1.95% 0.72% FCC Compliant? Yes * Yes Yes No Yes Yes No *No frequency plots were included in the paper. **Simulated value. PSD from measurements was below the noise floor of the spectrum analyzer. Ph.D. Thesis K. Allidina

44 Table 2-3: Comparison of Recent Transmitters that operate in the MHz UWB Band. [70] (2008) [40] (2012) Technology (CMOS Node) 90nm 0.13μm Type of Transmitter Direct Pulse Gen. Filtered Broadband Pulse [39] (2006) 0.15μm FD-SOI Filtered Broadband Pulse Center Frequency (MHz) dB Bandwidth (MHz) Pulse Amplitude (mv pk-pk) Pulse Width 4ns 2ns 5ns Repetition Rate 100MHz 300kbps 25kbps Power Consumption Repetition Rate) 220μW 1.93μW 1μW Energy / Pulse (@ Repetition Rate) 2.2pJ 6.43pJ 40pJ Pulse Energy (pj) 0.022* * Energy Efficiency 1% 9.2% 4.2% FCC Compliant? No Yes No *Assumed that the PSD limit in the MHz band is dbm/mhz, as in the GHz band. The pulse energy has been adjusted to reflect the maximum PSD of dbm/mhz for a fair comparison Power Consumption (mw) [39] [38] [40] [71] [40] Repetition Rate (MHz) Fig. 2-8: Power consumption vs. the pulse repetition rate for UWB transmitters. [69] [68] [73] [72] [70] [67] GHz Transmitters MHz Transmitters Ph.D. Thesis K. Allidina

45 10 1 [40] Energy Efficiency (%) [39] [38] [40] [71] [73] [72] [69] [70] [68] [67] GHz Transmitters MHz Transmitters Repetition Rate (MHz) Fig. 2-9: Energy efficiency vs. the pulse repetition rate for UWB transmitters. 2.4 Ultra Wideband Receivers Ultra wideband receivers can be broadly categorized into coherent and non-coherent types. Coherent receivers are based on a correlation approach, and these receivers have a higher immunity to noise and interference than non-coherent receivers. The basic operating principle of a correlation receiver is to compare the received signal to the expected signal. This is done by generating a template pulse and comparing it to the received pulse. If the two pulses have a correlation above a pre-determined threshold value, then a pulse has been received. A simple example of the receiver structure and waveforms for the detection of a 1 and a 0 using BPSK modulation is shown in Fig Ph.D. Thesis K. Allidina

46 DETECTION OF A 1 DETECTION OF A 0 Received Signal Product Output Signal Received Signal Product Output Signal Template Signal Template Signal Fig. 2-10: Correlation receiver structure and associated waveforms in a BPSK system. This type of receiver is very sensitive to the shape and timing of the template pulse, and therefore requires precise synchronization and an accurate template for high performance operation. Additionally, the shape of the received signal will be distorted based on the parameters of the antenna and wireless channel, so channel estimation is needed to properly generate the template pulse [26, 29]. Since the template pulse needs to be configurable, a digital approach to implement the receiver is preferred. However, directly converting the wideband signal to the digital domain requires an analog to digital converter (ADC) with a fast sampling rate, which typically means high power consumption [16, 76]. One suggestion to reduce power consumption in this type of receiver is to use a 1 bit ADC for the conversion [77, 78], however, the low resolution decreases the benefits associated with a correlation-based receiver. It is also possible to provide an estimated template pulse for correlation in the analog domain prior to digitization. One approach is to use an LC oscillator operating at the center frequency of the transmitted pulse [76, 79], and another is to use a 1 bit digital representation of the template pulse [80], however both of these approaches still require precise synchronization and timing to correctly match the phases of the template and received signal. The non-optimal template pulse shape also somewhat reduces the performance benefits of a correlator-based receiver. More details about the performance of these reduced complexity correlation receivers will be presented when the receiver implementations are discussed. Another type of correlation receiver that has been proposed is based on the transmittedreference modulation scheme discussed earlier. This scheme sends an unmodulated reference pulse first, followed by a data modulated pulse. The unmodulated pulse can be Ph.D. Thesis K. Allidina

47 used as the template, and the benefit is that it goes through the exact same channel as the data pulse, which means it will have the same distortion [81, 82]. This eliminates the need for channel estimation and the generation of a local template pulse, and since the received signal is being correlated with a delayed version of itself, this type of receiver is also known as an autocorrelation receiver. Although this receiver uses correlation as the detection mechanism, it is referred to as a non-coherent receiver since exact phase information about the received signal cannot be obtained [24]. One significant implementation challenge with this receiver is that an on-chip analog delay line is required to delay the reference pulse for comparison with the data pulse Transmission lines are the most accurate way of creating the delay, but would consume unreasonable chip areas at frequencies below 10 GHz [83]. Artificial transmission lines can be synthesized using lumped inductors and capacitors, but even then, delays in the nanosecond range become infeasible [24, 83, 84]. Approximate delay lines using digital techniques have also been proposed, but this comes with high power consumption. The approach in [85] can generate delays of 0.5 ns, but requires a power consumption of 58 mw. As with the standard correlation receiver, it is also possible to convert the received signal to the digital domain to perform the delay and autocorrelation, but this has the same issue of high power consumption. The other main disadvantage of using a transmitted-reference scheme is that the template pulse for correlation is noisy. This can lead to a significant degradation in performance, even if an ideal analog delay could be generated [76]. Due to the implementation challenges and high power that comes with correlator or transmitted-reference receivers, non-coherent receivers are generally preferred for low data rate, energy efficient systems [30-34]. These receivers are based on either energy detection or peak detection, and simplified receiver structures for both approaches are shown in Fig Ph.D. Thesis K. Allidina

48 ENERGY DETECTOR PEAK DETECTOR Received Signal Product Integral Output Signal Received Signal Output Signal + - Threshold Comparator Threshold + - Comparator Fig. 2-11: Simplified receiver structures for energy and peak detectors. In energy detection, the incoming signal is squared and integrated over the interval where the pulse is expected. A pulse is detected by comparing this energy to a threshold value. This type of receiver also integrates the noise and interferer energy, therefore, the chance of making a false detection also depends on the duration of the integration window [30, 86, 87]. In contrast, a receiver based on peak detection compares the incoming signal to a threshold to determine whether or not a pulse occurred. While noise and interference can still trigger a false decision, the detection scheme is based on instantaneous operation and is not affected by accumulated noise and interference. The advantage of non-coherent receivers is that they don t require the same level of timing precision as receivers based on correlation. However, to enable optimal detection and duty-cycling of the receiver, synchronization is still vital and will be discussed next Synchronization of UWB Receivers In an IR-UWB receiver, the most basic level of synchronization is pulse-level synchronization. This is essential for any IR-UWB receiver, however, as mentioned above, the level of precision required does vary based on receiver type. For example, in a correlator based receiver, the received pulse and template pulse must be aligned precisely to avoid performance degradation. A plot of the correlation coefficient between two 1 ns long Guassian monocycles vs. the misalignment of the pulses is shown in Fig It can be seen that a misalignment of ±90 ps results in a 25% decrease in the correlation coefficient. Ph.D. Thesis K. Allidina

49 Correlation Coefficient Pulse Misalignment (ns) Fig. 2-12: Correlation coefficient vs. pulse misalignment for 1 ns long Guassian monocycles. A typical guideline for the level of misalignment that can be tolerated is 1/10 th of the pulse width [24], which means for UWB pulses on the order of a nanosecond, the misalignment must be below 100 ps. This includes any jitter from the associated clock or delay generation circuitry in both the transmitter and receiver, which means a crystal oscillator is typically required on both ends of the communication link. In contrast, the level of synchronization required in an energy or peak detection receiver depends on the detection window. For example, if the UWB pulse duration is 1 ns and the detection window has a length of 10 ns, synchronization mismatches of up to ±4.5 ns can be tolerated. Attaining this level of jitter is possible with low cost, low power, and fully integrated circuits. As mentioned earlier, pulse level synchronization is more challenging at low data rates because the search space is so large. An example pulse train with a 1 MHz repetition rate that illustrates the sparseness of the pulses is shown in Fig The low repetition rate means that there are a large number of empty detection windows to search through in order to find the pulse. In this example, the duty cycle is only 0.2% of the pulse period. Ph.D. Thesis K. Allidina

50 µs Repeitition Time ~2ns Wide Pulse > 0.4 Amplitude (V) Empty Detection Windows Empty Detection Windows Time (µs) Fig. 2-13: Pulse train with a 1 MHz repetition rate, illustrating the low duty cycle nature. An example of a general synchronization system for a correlation or energy detection receiver is shown in Fig. 2-14, where parallel detectors combined with signal processing are used to synchronize the receiver to the incoming pulse. Each parallel block is active for a different part of the cycle (as determined by the delay line), and if one of the blocks continuously detects a signal, the receiver is synchronized. In a correlation receiver a template pulse generator is required to activate each parallel block, whereas in an energy detection receiver only an enable pulse is required. Ph.D. Thesis K. Allidina

51 Correlator or Energy Detector Correlator or Energy Detector Correlator or Energy Detector Signal Processing Correlator or Energy Detector Delay Delay Delay Delay Pulse Generator / Enable Signal Fig. 2-14: Example of a general synchronization system for correlation and energy detection receivers. This type of system imposes a trade-off between power consumption and the time needed for synchronization. For instance, if less parallel blocks are used to reduce power consumption, a smaller number of detection windows can be searched during each cycle which increases synchronization time. This trade-off can be alleviated in energy detectors by increasing the duration of the integration window. For example, in a system with a 1 MHz pulse repetition rate, using 100 ns energy detection windows would mean only 10 windows would need to be searched. However, the wide windows would cause a large amount of noise and interference to be integrated along with the signal, which would increase the probability of a false decision. A receiver based on peak detection triggers when a signal of sufficient amplitude is received. While noise and interference can still cause a false decision, their effects will not be accumulated over time. In contrast with an energy detector, this means widening the detection window in the synchronization scheme above could be used to decrease synchronization time without significant performance degradation. However, the wide detection windows would limit the level of duty-cycling that could be applied to the RF front-end for power savings once the receiver is synchronized. This work uses a clock and data recovery system for synchronization to avoid this issue, and the details of the Ph.D. Thesis K. Allidina

52 synchronization scheme will be described in detail when the implemented IR-UWB system is presented. 2.5 UWB Receiver Implementations This section will describe recent implementations of low power and low to medium data rate IR-UWB receivers found in the literature according to the architectures described above. The text will focus on the higher level techniques used for detection and synchronization, after which summary tables with detailed performance metrics will be provided and discussed IR-UWB Receivers Based on Correlation in the Analog Domain Most low power receivers based on correlation in the analog domain have been designed by using approximations of a template pulse. The receiver in [76] operates in the GHz range and uses what is known as quadrature analog correlaion (QAC), which is essentially a correlation receiver that uses an in-phase and quadrature sine wave at the center frequency of the UWB pulse to approximate the pulse template. The correlation operation is followed by a 4 bit ADC on both the in-phase and quadrature paths, and signal processing and synchronization is performed on an FPGA. The use of quadrature correlation reduces the level of precision needed in the template alignment as compared to the 1/10 th of the pulse width guideline stated previously since signal processing on the quadrature paths can be used to interpolate the timing of the received signal. The temporal resolution used here is 1 ns (for a ~4 ns pulse width), and with the 20 MHz repetition rate used in this system, there are 50 bins to search through for pulse-level synchronization. The number of bins increases as the data rate decreases - in a lower data rate system with a repetition rate of 1 MHz, there would be 1000 bins to search through! The modulation type used in this work is PPM, and two delay lines are used to provide timing for the analog front-end one delay line to provide the delay between the PPM pulses, and one to reset the window of integration in the corrleators. The input to these delay lines is the synchronized system clock from the FPGA. Duty cycling of the frontend for power reduction was not implemented here, but is stated as future work. Ph.D. Thesis K. Allidina

53 The approach of quadrature analog correlation is also taken in the receiver in [79], which operates in the MHz band and also implements a programmable spreading code (1 to 64 pulses / symbol) to realize a processing gain. Two synchronization algorithms are implemented in this work to investigate the trade-off between acquisition time and performance. The first is an exhaustive search that uses a parallel correlator for every possible code alignment, and cycles through each detection bin. For long code lengths or low pulse repetition rates, this process is very costly in terms of power. The second synchronization algorithm first achieves pulse level synchronization, followed by synchronization of the spreading code. While this algorithm is significantly more power efficient, it does not benefit from the processing gain of the code sequence, and will not perform as well in noisy conditions. This receiver is capable of pulse repetition rates of ~19.5MHz or ~39MHz, and is a very complete receiver the synchronization and baseband processing is implemented on-chip, but an off-chip crystal reference is still required to generate the accurate timing needed in a correlation receiver. Due to the high pulse repetition rate, duty cycling of the RF front-end was not implemented. The receiver in [80] operates with OOK modulation in the MHz band and uses a 1 bit digital approximation of the UWB template pulse for correlation. This template is used to create a clocked correlator, so current is only consumed when the template pulse is active. Synchronization is achieved by using a delay line to vary the timing of the template pulse. This system uses a pulse repetition rate of 1 MHz and a delay resolution of 160 ps. Since only a single correlator is used, there are 6250 bins to search through! Once the receiver is synchronized, duty-cycling of the RF front-end is enabled to reduce power consumption Mostly Digital IR-UWB Receivers Low power receivers that use a mostly digital architecture have been designed by using a 1 bit ADC in the MHz band. (They are described as mostly digital since an RF front-end is still required to amplify the signal.) The receiver in [77] samples the amplified input signal using a time-interleaved bank of 32 ADCs driven by a delay line. The input clock to the delay line operates at 60 MHz, which gives an effective ADC sampling rate of 1.92 GHz. An off-chip crystal reference is used to generate the Ph.D. Thesis K. Allidina

54 necessary stable reference, and an off-chip LC tank is needed to form the 60 MHz oscillator. The digital back-end is implemented off-chip and not described in this work, but the previous work from the same authors ([18]) gives insight into its behaviour. Even though the received signal has a resolution of 1 bit, the template for pulse detection used in the digital correlator must have a resolution of at least 4 bits to avoid further degrading the performance achievable with the low resolution digital signal. To recover from the low resolution ADC, an 11 x 11 concatenated Barker code is used, which means 121 pulses are used to represent each bit. To trade off speed vs. area for the synchronization procedure, 11 code phases are tried at a time. The pulse duration used is 2 ns, which means a worse case of 5500 pulses are needed for synchronization at a pulse repetition rate of 1 MHz. The receiver in [78] uses the same approach for their 1 bit ADC (including the bank of 32 time-interleaved ADCs), but has a more complete digital back-end integrated on-chip. A longer spreading code of 1024 bits is used to offset the performance degradation of the 1 bit ADC, which makes synchronization a daunting task. The process is streamlined using parallel blocks, however, 8192 pulses are still needed for synchronization. The work in [88] applies the concept of a 1 bit ADC to design an UWB receiver operating in the GHz band that is a cross between a mostly-digital architecture and an energy detector. The incoming signal is first converted to digital levels by two parallel chains of saturating amplifiers, and the outputs of each chain are XNORed together to perform the squaring (or autocorrelation) operation before digitization. The theory behind this detection scheme is that if no signal is detected, random noise will cause the outputs of the amplifier chains to fluctuate randomly between 0 and 1, and the integrated XNOR output will be at a level of 0.5 bits. If a signal larger than the noise is received, the output of both amplifiers will match each other, and the XNOR gate will output a 1. A single channel ADC with a 998 MHz sampling clock follows the XNOR gate, and the integrating filter of the energy detector is implemented in the digital back end. The length of the integration window is 8 ns, and when using overlapping windows to account for the case where a pulse straddles two frames, the time needed for pulse level synchronization at a pulse repetition rate of 1 MHz is 250 pulse periods. All of the Ph.D. Thesis K. Allidina

55 required digital circuitry is included on-chip, however, duty cycling to reduce power consumption is not implemented IR-UWB Receivers Based on Energy Detection The receiver in [89] is based on energy detection and uses PPM modulation. It operates in the GHz range, but splits this into three 500 MHz sub-bands to trade communications distance with the ability to change bands in the presence of strong narrowband interferers. Each frame is 60 ns long, which means the energy detection window is 30 ns per PPM pulse location. The results of the energy integration for the two PPM phases are stored on capacitors to enable the relative comparison between the two possible pulse locations at the end of each frame. The timing and synchronization are performed off-chip using an FPGA, and the 60 ns long frames mean that pulse-level synchronization with a minimum of 34 pulses is possible for a repetition rate of 1 MHz. (This accounts for the use of overlapping bins to prevent the case where the pulses straddle two frames.) This is significantly faster than the analog correlation receivers described earlier; however, the relatively long 30 ns integration window does reduce the performance of this receiver in the presence of narrowband interference. Duty-cycling is implemented in this work to save power, but it should be noted that the 60 ns frame time places a limit on the level of duty-cycling that can be obtained. This research group also implemented the same concept of a multi-band energy detection receiver with a ~30 ns integration window in [90], but in this work the digital backend described in [91] was integrated on the same chip to realize a full receiver with synchronization and duty-cycling capabilities. This receiver also has additional flexibility in that it can operate with OOK as well as PPM modulation, and the application for this fully integrated design was the control of an insect s flight path! The receiver, control electrodes, and a miniature battery as well as supporting components (all weighing 1 g) were mounted on a hawkmoth, whose flight path was demonstrably altered by sending wireless control signals. The receiver in [92] presents a similar energy detection receiver as the previous two that operates in the GHz band to reduce the probability of interference caused by existing narrowband systems. This energy detector uses a 15 ns integration window Ph.D. Thesis K. Allidina

56 which can achieve pulse-based synchronization in ~133 pulse periods at a repetition rate of 1 MHz, and the shorter detection window reduces the amount of signal corruption from integrated noise and interference. This work only provides the RF front-end, and all necessary digital electronics were implemented off-chip. The ability to duty-cycle the RF front-end to reduce power was also not implemented. The receiver in [16] implements an energy detector with a tunable window of integration to allow for a configurable trade-off in terms of performance and synchronization time. This receiver operates in the 3 5 GHz range, and uses the full 2 GHz spectrum for pulses as opposed to using 500 MHz channels with band-hopping as in some of the other works. The larger bandwidth allows each pulse to have more power, which enables a longer communications distance. A major portion of the backend in this receiver is implemented on an FPGA to allow for flexible testing, including options such as controlling the tunable integration window, different synchronization schemes, coding options, etc., however, a comparison of the performance trade-offs when using these options is not provided IR-UWB Receivers Based on Peak Detection The receiver in [39] operates in the MHz band, and is based on dual peak detection such that it can detect BPSK modulated signals. This is done by noting whether the received signal first crossed the positive or the negative threshold in the comparator. If the positive peak comes first, the signal is interpreted as a 1, and if the negative peak comes first, it is a 0. This receiver uses a counter as the synchronization scheme the number of cycles of a higher frequency clock between adjacent received pulses is counted and stored to determine when the receiver should turn on. In theory, this receiver can attain pulse-level synchronization within 2 pulse periods; however, to obtain sufficient resolution for duty-cycling, the clock frequency must be orders of magnitude higher than the data rate. The ability to continuously track the received signal and compensate for clock drift is also not implemented here. The receiver in [38] is a dual-band receiver based on peak detection that operates in the 3 5 GHz band. A comparator with positive feedback is used as the peak detection mechanism, and the dual-band approach is not for interference mitigation as in other Ph.D. Thesis K. Allidina

57 works, but for synchronization. Data is sent on one channel, and the second channel is used to for the sole purpose of a simultaneous multiuser synchronization scheme [93]. No details on the performance of this scheme are given in this paper. The receiver back-end and pulse-level synchronization scheme is implemented off-chip, and no details are discussed here or in a related work from the same authors [94]. The detection window in this receiver has a duration of 10 ns, so if they are using the same type of detection scheme as an energy detection receiver, the synchronization routine would require 200 pulses at a pulse repetition frequency of 1 MHz. The receiver in [73] is based on peak detection in the GHz band, and uses a modulation scheme that could be called an OOK version of transmitted-reference modulation. This work dubs the modulation scheme as synchronized on-off keying (S-OOK), and operates by sending a pilot pulse in every frame. If a 1 is to be sent, the pilot pulse is followed by a second pulse. For the transmission of a 0, the pilot pulse is sent alone. This has the advantage of providing additional timing information since a pulse is sent in the same position in each cycle, but since the receiver has to listen for two pulses, the achievable level of duty-cycling is reduced. As well, the transmission of more pulses means each pulse must contain less energy in order to meet the FCC restrictions. The portion of the back-end that converts the received RF input into a digital signal is implemented on-chip, however, the duty-cycling control signals and associated synchronization hardware is implemented on an FPGA. The receiver in [95] uses a peak detection with OOK modulation in the 3 5 GHz band. Little information about the front-end performance is given, but the synchronization scheme uses the same clock and data recovery synchronization scheme as the one proposed in this thesis (although the receiver in this thesis was initially presented three years earlier [62]). The receiver in [95] uses an all-digital CDR to perform the synchronization, which has the advantage of greater programmability due to the use of a digital loop filter, and the disadvantages of increased jitter and the need of a higher clock frequency to operate the digital blocks. No information on the speed of synchronization (e.g., the bandwidth of the CDR loop) is given in this work. Ph.D. Thesis K. Allidina

58 2.5.5 Comparison of Implemented UWB Receivers As with UWB transmitters, some background is needed to perform an informed quantitative comparison of the UWB receivers that have just been described. One factor that must be taken into account is that the sensitivity of an UWB receiver improves as the data rate is decreased. This is because the sensitivity numbers reported in the literature are for the average power in the received waveform, and this will decrease with data rate since the signal is less dense. For example, consider the pulse trains shown in Fig The pulses in both signals have the same energy, and we will assume a receiver has been designed such that this is the minimum detectable energy level. If the receiver operates at 50 Mbps, it will have a sensitivity of -43dBm, however, if it operates at 100 Mbps, it will have a sensitivity of -40dBm. This can be extrapolated to lower data rates as well if the receiver operates at 100 kbps, it will have a sensitivity of -70dBm. Thus, the sensitivity of a receiver must be reported at a specific data rate to portray relevant comparison information. (Note that in all cases, the instantaneous minimum detectable signal of the receiver remains unchanged.) Amplitude (mv) Amplitude (mv) Pulse Energy = 1.03fJ Pulse Train Power = -42.9dBm 50 MHz Pulse Train Time (ns) Pulse Energy = 1.03fJ Pulse Train Power = -39.9dBm 100 MHz Pulse Train Time (ns) Fig. 2-15: UWB pulse trains with equal energy pulses at different repetition rates. Another issue with UWB receiver comparisons is the metric of energy / bit. While this is theoretically a good measure of a receiver s energy efficiency, it favors receivers that Ph.D. Thesis K. Allidina

59 operate at high data rates. This is because the fixed power of the RF front-end is amortized over more data bits. For example, a receiver that has an always-on 10 mw RF front-end will have an energy efficiency of 1 nj/bit at 10 Mbps, but this will increase to 10 nj/bit at 1 Mbps. This metric also favors receivers that are less sensitive since they will typically implement fewer gain stages, and therefore consume less power. As such, energy efficiency is really only a useful metric for comparison if the receivers operate at the same data rate and sensitivity. Note that UWB receivers that implement duty cycling do not have an always-on front-end, which helps to reduce the bias towards high data rate receivers when using the energy / bit metric. Lastly, many receivers in the literature do not implement a full receiver in that the synchronization routine, duty-cycling of the RF front-end, and/or the entire digital backend may be implemented off-chip. This will result in a receiver with reduced area and power consumption than it would have if implemented completely on-chip. These issues will be pointed out whenever possible as the performance numbers associated with each receiver are presented. A comparison of UWB receivers that operate in the GHz band is shown in Table 2-4, and a comparison of UWB receivers that operate in the MHz band is shown in Table 2-5. When comparing receivers in the GHz band, an entry for the receiver sensitivity normalized to a 1 Mbps data rate has been provided to allow for a more complete comparison and reduce the dependency of sensitivity on the data rate. Unfortunately, the same type of normalization cannot be readily applied to the energy / bit metric since most receivers in this band implement the digital band-end, synchronization algorithm, and generation of the signal for front-end duty cycling off-chip (usually on an FPGA). A normalized sensitivity metric for the receivers in the MHz band has not been provided because most of these receivers did not report the sensitivity. The front-end gain can only give an approximation of the receiver sensitivity since different detection methods will yield different results. Ph.D. Thesis K. Allidina

60 Table 2-4: Comparison of Recent Receivers that Operate in the GHz UWB Band. [76] (2007) [88] (2009) [89] (2007) [90] (2010) [16] (2012) [38] (2010) [73] (2011) [95] (2013) Technology (CMOS Node) 0.18μm 0.13μm 90nm 90nm 90nm 90nm 90nm 65nm Type of Receiver Analog Mostly Energy Energy Energy Peak Peak Peak Correlator Digital Detector Detector Detector Detector Detector Detector Die Size 8mm 2 8mm 2 2.2mm mm 2 1.1mm 2 1.9mm 2 1mm mm 2 Data Rate Up to Up to Up to Up to Up to 20Mbps 31Mbps 16.7Mbps 16Mbps 33Mbps 100kbps 1Mbps 2Mbps Modulation PPM OOK, PPM PPM OOK, PPM OOK OOK S-OOK OOK Maximum Front-End Gain * 80dB 40dB 45dB 59dB 39dB 38dB * Receiver Sensitivity * -78 dbm -99 dbm -76 dbm -79 dbm -87 dbm -66 dbm -76 @ 2Mbps Receiver Sensitivity Normalized to 1Mbps * -73 dbm -89 dbm -88 dbm -89 dbm -77 dbm -66 dbm -79 dbm Operating Frequency (GHz) * Front-End Power (mw) Digital / Backend Power Off-Chip 37mW Off-Chip 2.49mW Off-Chip Off-Chip 0.2 mw** 100μW Energy per Bit (nj / bit) at Highest Data Rate * Value not reported ** Duty-cycling and associated hardware if off-chip Ph.D. Thesis K. Allidina

61 Table 2-5: Comparison of Recent Receivers that Operate in the GHz UWB Band. [80] (2006) [79] (2010) [77] (2006) [39] (2006) Technology (CMOS 0.15μm 0.18μm 0.13μm 0.13μm Node) FD-SOI Type of Receiver Analog Analog Mostly Peak Correlator Correlator Digital Detector Die Size 0.38mm mm mm mm 2 Data Rate 1 Mbps 305 kbps to Up to 39 Mbps 10 Mbps 25 kbps Modulation OOK BPSK BPSK, PPM BPSK Maximum Front-End Gain Receiver Sensitivity * 16dB 50dB 42dB 50dB 1.3Mbps** * Value not reported. ** Using the reported PN code of 15 pulses / bit in LPP mode *** Using an 11 x 11 concatenated Barker code * * Operating Frequency (MHz) 0 to to to to 350 Front-End Power (mw) Digital / Backend Power 60μW 2mW Off-Chip 30μW Energy per Bit (nj / bit) 1Mpbs 1.3Mbps** 83 kbps*** 25kbps The only receivers that are fully characterized and have complete on-chip implementations are those in [90], [79], and [88]. The mostly digital receiver implemented in [88] is seen to have a very high power consumption of 45 mw due to the speed (and power consumption) required in the digital baseband. When considering the receivers in [90] and [79], the average power consumption at a data rate of 1 Mbps (with duty-cycling enabled) can be calculated as 1.4 mw and 2.4 mw respectively. In the acquisition phase (before duty-cycling), the power consumption rises to mw and 4.8 mw, respectively. It can be seen that there is a dramatic power reduction for the receiver in [90] once the pulse is acquired and duty-cycled operation can begin. This clearly shows the need for a fast and efficient synchronization scheme, especially for applications with a small data payload since the acquisition phase can take a significant portion of each communication Ph.D. Thesis K. Allidina

62 sequence [16, 17]. Consider a wireless sensor network node monitoring temperature and humidity, which can typically each be represented by less than 16 bits of data. This, combined with identification and location information, will typically need a packet with a length of ~50 bits. Thus, a synchronization preamble of even 50 bits will halve the efficiency of the communication scheme. The receiver in [79] has a much lower always on power consumption since it operates in the MHz band. The power reduction once synchronization is acquired is not as dramatic due to the fact that multiple pulses per bit are used to realize a processing gain. This means a faster pulse repetition rate is required for a given data rate, which limits the level of duty-cycling that can occur. A plot of the normalized sensitivity at 1 Mbps vs. the always on front-end power consumption for all of the receivers that reported the sensitivity is shown in Fig It can be seen that the trend of higher power consumption for increased sensitivity holds, with the lowest front-end power consumption being 2.8 mw for a normalized sensitivity of -65 dbm in the MHz band. Fig shows a plot of the energy / bit vs. the data rate for the UWB receivers. As expected, the complete receivers ([79, 88, 90]) have a higher energy / bit than those that implement the back-end off-chip. Normalized Sensitivity at 1Mbps (dbm) [79] [73] [88] [38] [95] GHz Receivers MHz Receivers -85 [90] [16] [89] Front End Power (mw) Fig. 2-16: Normalized sensitivity at 1 Mbps vs. front-end power consumption for UWB receivers. Ph.D. Thesis K. Allidina

63 10 1 [39] [77] GHz Receivers MHz Receivers Energy / Bit (nj) 10 0 [89] [73] [80] [79] [95] [90] [88] [16] 10-1 [38] Repetition Rate (Hz) Fig. 2-17: Energy / bit vs. the repetition rate for UWB receivers. 2.6 The Proposed System Now that an overview of existing UWB transmitters and receivers has been presented, the proposed system will be discussed. The main motivation for this system is to implement an UWB receiver with a fast and low complexity synchronization scheme that is also capable of duty-cycling to receiver front-end for power reduction. Of the works that implement a digital baseband for energy detection [90] and analog correlation [79] receivers, the digital power consumption is high (2.49 mw and 2 mw, respecitively), and the chip area is large (5.46 mm 2 and 3.18 mm 2, respectively). To address these issues, a peak detector receiver with a CDR synchronization scheme will be chosen. Transferring the synchronization system to the analog domain with a CDR system will significantly reduce the size of the digital backend, which dominates the chip area in both of these works (the digital area is larger than 60% of the chip). This will also reduce the power consumption since the digital backend is a significant contributor. A non-coherent architecture was chosen for the reduced implementation complexity, which is desirable for a low power receiver. A peak detection architecture is chosen over an energy detection architecture to explore the concept of a synchronization scheme based on a CDR loop. While, in theory, an optimal energy detection receiver performs better in the presence of noise than a peak detector, a non-optimal implementation (as is a Ph.D. Thesis K. Allidina

64 common trend in low power systems) will suffer from accumulated noise and interference during the integration window. This will be discussed further in the next chapter, which will present a comparative analysis of energy and peak detectors in the presence of noise. Additionally, the performance of these receivers in the presence of interference will also be analyzed and, as stated earlier, the wide bandwidth of UWB receivers can cause the impact of interference from pre-existing narrowband systems to be orders of magnitude higher than the impact of noise. The results of this analysis show that in interference dominated environments, a receiver based on peak detection can outperform a receiver based on energy detection, and this is another driving factor for the architectural choice made here. To realize a very low power implementation, the receiver will be designed to operate in the MHz band as opposed to the GHz band. Besides allowing for a lower power receiver, operating below 960 MHz also reduces the path loss and the delay spread of the wireless channel [96]. While the antenna size for this frequency band renders this system unattractive for mobile devices, applications such as structural health monitoring of urban infrastructure (e.g., the structural integrity of bridges) do not have this size constraint. It should also be noted the reduced path loss in this frequency band can also allow for options such as the use of smaller antennas with lower efficiencies. Additionally, high contrast dielectrics (ε r > 100) can be used to create physically small wideband antennas that operate at 1/10 th of the wavelength instead of the usual 1/4 th of the wavelength [97]. It should also be noted that the proposed CDR synchronization scheme can readily be applied to peak detection receivers that operate in the GHz band. A low power transmitter will also be designed, and will be based on using a broadband pulse to excite a pulse-shaping filter. The goal of this transmitter will be to occupy as much of the UWB band as possible while still meeting the power spectral density requirements imposed by the FCC spectral mask. Ph.D. Thesis K. Allidina

65 Chapter 3 - Analysis of Non-Coherent UWB Receivers Analysis of Non-Coherent UWB Receivers 3.1 Introduction As we have seen, the broadband pulses in IR-UWB systems can lead to low power and energy efficient hardware implementations. However, the wide bandwidth and carefully regulated power spectral density makes narrow-band interference from existing wireless services an important issue. As mentioned earlier, measurements have shown that the average NBI power from existing systems can be orders of magnitude higher than the noise floor [18, 19]. Various techniques have been proposed to minimize the effect of these interferers on UWB systems such as the use of notch filters in the receiver [98, 99], code-aided spreading techniques [100, 101], and multichannel approaches [102]. While these approaches can improve the performance of the receiver, they come at the expense of complexity and power consumption which is undesirable for low power, low data rate systems. Even with these techniques, NBI cannot be completely eliminated, which necessitates an accurate analysis of receiver architectures in the presence of interference. This chapter will focus on the analysis of non-coherent receivers in the presence of noise and interference since they are preferred in low power applications due to their simplicity, increased energy efficiency, and less stringent timing requirements. The two types of non-coherent receivers discussed here are those based on either energy detection or peak detection. Since peak detectors only use a portion of the signal energy, they typically require higher signal energy to achieve the same level of performance in the presence of noise. However, a peak detector does have advantages in the presence of interference. This stems from the fact that a peak detector is only affected by the instantaneous interference level, whereas an energy detection receiver accumulates the interference energy over the entire integration window. In this chapter the performance of an energy detector, a peak detector, and a dual peak detector (in which a decision is Ph.D. Thesis K. Allidina

66 made if the signal crosses either a positive or negative threshold) will be analyzed in the presence of noise and interference. Theoretical expressions for the bit error rates will be derived and simulations in both an AWGN and multipath channels will be performed. 3.2 System Description The UWB system analyzed here uses an OOK modulation scheme, and the databit waveform at the receiver that is used to describe the k th bit can be written as: s ( t) = d p( t ), (3.1) k k kt R where d k is the data of the k th bit (0 or 1), p(t) is the pulse waveform at the receiver, and T R is the pulse repetition rate. Each data bit is represented by a single pulse instead of spreading the data bit across multiple pulses since the goal is to compare the peak and energy detectors themselves. The increased performance in the presence of NBI obtained by using multiple pulses per data bit will be equivalent in both cases. The pulse used for this analysis is a baseband Gaussian pulse that conforms to the MHz FCC regulations. Since the transmitting antenna acts as a differentiator for the signal, the received pulse shape p(t) can be described by the Guassian monocycle shown in Chapter 2, and is described by the equation: p( t) = A p ( t τ ) u e 2 t τ u, (3.2) where A p is the pulse amplitude, τ is the offset time and u is a scaling parameter used to select the bandwidth. Note that the variables have changed from the Gaussian monocycle in Eq. (2.2) to be more consistent with the notation typically seen in communications analysis. In this work the pulse shaping parameters have been selected to yield a pulse with a 2 ns duration and a 10 db bandwidth of 870 MHz. The entire received signal is given by: r ( t) = s( t) + n( t) + i( t), (3.3) where n(t) represents thermal noise and i(t) represents narrowband interference. Since this analysis is targeted towards low data rate systems, a 1 Mbps data rate will be used. Ph.D. Thesis K. Allidina

67 The repetition time between pulses is long enough to ensure that no intersymbol interference (ISI) will occur. In an energy detector, the received signal is first squared and integrated within a specific time window, which is denoted by T in the following analysis. A 1 is said to be detected if the output at the end of the integration is above the detection threshold. Otherwise, a 0 is said to be detected. In a single peak detector, the squarer and integrator blocks are removed and a 1 is said to be detected if any part of the received signal during the time window T is above the detection threshold. Otherwise, a 0 is said to be detected. A dual peak detector follows this concept, but uses both the positive and negative portions of the received signal. A 1 is said to be detected if any part of the received signal during the time window T is either above the positive threshold or below the negative threshold. Otherwise, a 0 is said to be detected. Simplified structures of energy and peak detection receivers were shown earlier in Fig. 2-11, and operate as described above. 3.3 Performance in the Presence of Noise This section will assume that the narrowband interference can be neglected, and the performance of both an energy detector and peak detector will be derived Energy Detector Performance While the performance of an energy detector in the presence of noise has been previously derived in [103, 104], a brief derivation follows for completeness. The test statistic used to compute the performance of an energy detector can be expressed as: Y = 2 N 0 T 2 [ s( t) n( t) ] dt + 0, (3.4) where the energy is integrated over an interval of time T and N 0 is the one-sided noise power spectral density. Using the sampling theorem, we can express the equivalent low-pass noise signal as: Ph.D. Thesis K. Allidina

68 ni i= n ( t) = sinc(2wt i), (3.5) where i n = i = n t, (3.6) 2W and W is the receiver bandwidth (i.e., the bandwidth of s(t)). Each n i is a Gaussian random variable with distribution N(0, N 0 W). Assuming a 0 is transmitted and only noise is present, the energy in the interval from 0 to T can be approximated as [103]: Y 0 = 2 N 0 T 0 2 n ( t) dt 1 N W 0 2TW 2 n i i= 1. (3.7) Defining n' = i n i N W 0, we can write: 2TW n i i= 1 2 Y0 = '. (3.8) Since n i is a Gaussian random variable, Y 0 has a central chi-square distribution with 2TW degrees of freedom. By following the same approach, we can find the distribution for the case where a 1 is transmitted. The equivalent low-pass signal waveform can be written as: where s( t = i ) s i =. 2W i i= s ( t) = s sinc(2wt i), (3.9) The energy in the interval from 0 to T can be expressed as: where n i is given above and Y T 2TW = [ s( t) + n( t) ] dt ( s' i + n' i ) N 0 0 i= 1, (3.10) Ph.D. Thesis K. Allidina

69 s s' i i =. (3.11) N W Y 1 has a non-central chi-square distribution with 2TW degrees of freedom, and a noncentrality parameter given by 2E/N 0, where E is the energy of s(t) within the window of integration. The probability of error can now be found from the distributions of Y 0 and Y Peak Detector Performance This section will derive the performance of both the peak detector and the dual peak detector, which is expected to be more robust since both the positive and negative peaks are compared with positive and negative thresholds. As in the previous derivation, the noise can be described by a Guassian waveform with n(t) ~ N(0, N 0 W), and the discrete case will be considered by using the sampling theorem. The test statistic of each discrete sample for the transmission of a 0 is given by the following independent and identically distributed (iid) Gaussian probability density function: 0 x 2N W 1 0 Y0 = ni ~ f0 = e 2πN W 0 2. (3.12) The transmission of a 1 is represented by the sampled signal waveform where each sample is the mean value of this iid Guassian probability density function. In other words, an iid Gaussian probability function representing the noise is centered on each sample of the signal waveform, which creates a distribution of values for each sample of the received signal. The test statistic of each sample is given by: ( x s ) i 2N W 1 0 Y1 = [ si + ni ] ~ f1 = e 2πN W 0 2, (3.13) where s i is the amplitude of the received pulse at each time sample i. These distributions are described graphically in Fig. 3-1 for three different times during a pulse. Note that both a positive and negative threshold is shown in this figure. The dual peak detector will use both thresholds, whereas the single peak detector will only use one. The range of the index i is 0 i 2TW, where, as before, T is the length of the detection window and W is the receiver bandwidth. Ph.D. Thesis K. Allidina

70 t = i 1 PDF for a 1 PDF for a 0 s i -V T 0 V T t = i 2 PDF for a 0 PDF for a 1 -V T 0 s i V T t = i 3 PDF for a 1 PDF for i1 i 2 i 3 a 0 (b) -V T 0 V T s i (a) Fig. 3-1: (a) Probability density functions of the test statistics of a dual peak detector at selected time samples of a (b) received pulse. The probability that a 1 is detected when a 0 is transmitted for the single peak detector can be described by the probability that f 0 is above the positive threshold value in a given detection window T. For the dual peak detector, this case can be described by the probability that f 0 is above the positive threshold or below the negative threshold value. To derive this probability, we will first consider the case where a single noise sample is below the positive threshold (i.e., no error has occurred). This can be expressed as: V T P ni < VT ) = f0, i ( dx, (3.14) where V T is the positive threshold (which is the only threshold in the single peak detector). The probability that all of the noise samples in a given detection window T are below the positive threshold can be expressed as: P( V 2TW T ni < VT ) = f 0, idx, (3.15) i since there are a total of 2TW samples in the detection window T. We can apply this line of reasoning to the negative threshold in the dual peak detector as well. The probability Ph.D. Thesis K. Allidina

71 that all of the noise samples in a given detection window T are above the negative threshold can be expressed as: P( 2TW ni > VT ) = f0, idx. (3.16) i VT Thus, for the dual peak detector the probability that all samples are both below the positive threshold and above the negative threshold is given by the product of (3.15) and (3.16), and is expressed by: P( 2TW V T VT < ni < VT ) = f0, idx f0, idx. (3.17) i VT The expressions in (3.15) and (3.17) give the probability where a 0 is transmitted and a 0 is detected for the single and dual peak detectors, respectively. The probability that an error has occurred (i.e., one or more noise samples has exceeded the positive threshold for a single peak detector or either the positive or negative threshold for a dual peak detector) is given by the complement of these expressions. For the single peak detector the probability of an error is given by: P(1 0) SinglePeak VT = 1 f 0, i dx 2TW. (3.18) The probability of an error in a dual peak detector is given by: P(1 0) DualPeak VT = 1 f 0, idx VT f 0, i dx 2TW. (3.19) The probability that a 0 is detected when a 1 is transmitted can be described by the probability that no samples of f 1 are above the positive threshold in a single peak detector. For the dual peak detector, this case can be described by the probability that no samples of f 1 are above the positive threshold or below the negative threshold. We will first consider the probability that a single sample of f 1 is below the positive threshold, which can be expressed as: Ph.D. Thesis K. Allidina

72 V T [ si + ni ] < VT ) = P f1, i ( dx. (3.20) The probability that all of the samples in the detection window T are below the positive threshold can be expressed as: V 2WT T P [ si + ni ] < VT = f1, idx, (3.21) i i= 1 since there are a total of 2TW samples in the detection window T. For the single peak detector, this expression represents the probability that a 0 is detected when a 1 is transmitted, which can be written as: 2WT VT P( 0 1) = SinglePeak f1, idx. (3.22) i= 1 For the dual peak detector we must also consider the probability that all of the samples in the detection window are above the negative threshold, which can be expressed as: 2WT P [ si + ni ] > VT = f idx. (3.23) 1, i i= 1 VT For a dual peak detector, the product of (3.21) and (3.23) yields the probability that a 0 is detected when a 1 is transmitted, and this is expressed by: 2WT V T P( 0 1) DualPeak = f1, idx f1, idx, (3.24) i= 1 VT where the two PDFs are multiplied since both conditions have to be satisfied to cause a 0 to be detected. The expression for the BER of the single peak detector can now be derived from (3.18) and (3.22) as: Ph.D. Thesis K. Allidina

73 = = TW i o i T TW o T SinglePeak W N s V W N V BER erf erf , (3.25) where erf is the error function, and a symmetric source is assumed (i.e., there is an equal probability that a 1 or a 0 is transmitted). The expression for the BER of a dual peak detector can be derived from (3.19) and (3.24) as: = = TW i o i T o i T TW o T DualPeak W N s V W N s V W N V BER erf 1 2 erf erf (3.26) In the single peak detector, the theoretical optimum threshold value occurs at the intersection of the two Gaussian PDFs, i.e., 0.5*max[s(t)]. However, this is not the case in a dual peak detector, since there are essentially two thresholds that can be surpassed by noise to falsely detect a 1 in the presence of a 0. Likewise, there is a greater chance that noise will not affect the detection of a 1 since it would have to cause both the positive and negative peaks of the signal to fall below their respective thresholds. This reasoning leads to the assumption that the optimal threshold will be somewhat greater than 0.5*max[s(t)]. The optimal threshold value for the dual peak detector can be found by minimizing the derivative of (3.26), or by plotting the BER and graphically finding the minimum. The latter is shown in Fig. 3-2, and while the optimal threshold value does vary with the bit energy / noise power spectral density (E b /N 0 ) of the received signal, it is found to be around 0.61 max(s(t)), which agrees with the above reasoning. Ph.D. Thesis K. Allidina

74 Bit Error Rate C A: E b /N 0 = 14dB B: E b /N 0 = 13dB C: E b /N 0 = 12dB Normalized Threshold Voltage Fig. 3-2: BER vs. the normalized threshold voltage for the dual peak detector Performance Comparison Using the derived probability distributions, the theoretical BER has been calculated for energy and peak detectors with various lengths for the detection window. The results are compared in Fig. 3-3, where the value of E b /N 0 is calculated based on data with an equal probability of being either 0 or 1. It can be seen that for the 2 ns detection windows, the performance of the energy detector and dual peak detector are almost equal while the single peak detector requires a 1.5 db increase in E b /N 0 for the same performance. However, as the length of the detection window is increased, the performance of the energy detector decreases faster than that of the peak detectors. This is because it collects all of the noise present during the longer detection window whereas the peak detectors are only affected by the instantaneous noise level. B A Ph.D. Thesis K. Allidina

75 A: Single Peak Detector - 2ns Window B: Dual Peak Detector - 2ns Window C: Energy Detector - 2ns Window D: Single Peak Detector - 6ns Window E: Dual Peak Detector - 6ns Window F: Energy Detector - 6ns Window BER Fig. 3-3: Comparison of the theoretical BER vs. E b /N 0 for a single peak detector, dual peak detector, and energy detector for various detection windows. A plot of the required E b /N 0 to achieve a BER of 10-3 vs. the duration of the detection window is shown in Fig It can be seen that the performance of the energy detector decreases faster than for the peak detectors. The dual peak detector always outperforms the energy detector, and the single peak detector shows better performance for detection window durations longer than ~15 ns. However, as will be seen later, the fact that the energy detector collects all of the energy within the detection window allows the energy detector to outperform the peak detectors in a multipath channel as opposed to an AWGN channel F B C E A D E b /N o (db) Required E b /N o for a BER of 10-3 (db) Energy Detector Single Peak Detector Dual Peak Detector Detection Window Duration (ns) Fig. 3-4: Required E b /N 0 for a BER of 10-3 vs. the detection window duration. Ph.D. Thesis K. Allidina

76 3.4 Performance in the Presence of Interference This section will assume that the noise can be neglected, and will derive the performance of energy and peak detectors using OOK modulation in the presence of narrowband interference Energy Detector Performance The test statistic used to compute the hypothesis of an energy detector can be expressed as: Y T 2 [ s t) i( t) ] dt = ( +, (3.27) 0 where the interferer i(t) can be well-approximated by a single-tone signal [105, 106]. Thus, i(t) is given by: i( t) = N n= 1 A in cos( ω t + φ ), (3.28) where A i is the amplitude, ω is the frequency, and ϕ is the phase of the n th interferer. We will analyze the case where there is only 1 interferer, and simulations will be provided to evaluate the performance in the presence of multiple interferers. The test statistics for the transmission of a 0 and a 1 are given by: Y = E n n Y 0 = E i, (3.29a) T 1 p i ) 0 + E + 2 p( t) i( t dt, (3.29b) where E i and E p are the energy of the interferer and the pulse, respectively, in the interval from 0 to T. It is the third term in Y 1 that gives rise to errors since the cross correlation between the signal and the interference can cause Y 1 to be below the threshold of the detector. Expanding the third term yields the expression: Ph.D. Thesis K. Allidina

77 2 T 0 * C C * [ e erfi( D) + e erfi( D )] 1 2 Ap Ai π u ω 4 p( t) i( t) dt = t 2, (3.30) τ 1 u Ap Aiue cos( ωt + φ) 4 T u ω where erfi is the complex error function, C = + j( ωt + φ), and 4 uω t τ D = + j. 2 u Assuming ϕ is a uniform random variable [105, 106], a plot of of Y 0 and Y 1 vs. ϕ is shown in Fig. 3-5 for the case where the interference frequency is at the centre of the pulse spectrum (~435 MHz). The integration window is set at 2 ns, and the detection threshold is set as the maximum interference energy. It can be seen that the product of the pulse and interferer (term 3 in (3.29b)) causes a relatively large deviation in Y 1 as the phase is swept. The region where Y 1 drops below the threshold value will result in detection errors, and can be used to calculate the BER by finding the percentage of ϕ values that cause Y 1 to fall below the threshold Energy (nj) Y 1 Detection Errors 0.4 Threshold 0.3 Y Phase of Interferer (rads) Fig. 3-5: Energy vs. the phase of the interferer for the energy detector test statistic in the presence of a single narrowband interferer. Ph.D. Thesis K. Allidina

78 3.4.2 Peak Detector Performance To analyze the peak detector performance in the presence of interference we must look at the maximum and minimum (for the dual peak detector) values of the input signal in the detection window. For the case with one interferer, the test statistics can be expressed as: Y = AI cos( wt + ), (3.31a) 0 φ t τ 2 [ ] ( ) t τ u Y = max ( ) + ( ) = max + cos( + ) 1,max s t i t Ap e AI ωt φ, (3.31b) u Y = min [ s( t) + i( t) ] t τ 2 ( ) t τ u = min A e + A cos( ωt + ) p I, (3.31c) u 1,min φ where the time window is given by 0 t T, i(t) is again given by (3.28), and it is assumed that the detection window is larger than the pulse and that the peak of the interferer occurs within the detection window to account for the worst case scenario. The expression in (3.31c) only applies to the dual peak detector since the single peak detector only uses a positive threshold. As with the energy detector, ϕ is assumed to be a uniform random variable. Insight into the advantages that a dual peak detector offers as opposed to a single peak detector can be obtained by examining the signals in the time domain. Fig. 3-6 shows a plot of the signal and an interferer vs. time over the 2 ns detection window. The frequency of the interferer is at the centre of the pulse spectrum (~435 MHz), and the detection threshold is set as the peak amplitude of the interferer. We can see that the combination of the interferer and signal pulse causes the peak of the received signal to drop below the detection threshold, and an error would occur if only the maximum value of the signal was used (e.g., in the single peak detector). However, the minimum value of the signal is less than the negative threshold, which means an error would not occur if a dual peak detector was used. Ph.D. Thesis K. Allidina

79 0.6 Amplitude i(t) Threshold s(t) + i(t) -Threshold Time (ns) Fig. 3-6: Amplitude vs. time plot of i(t) and s(t) + i(t) within the detection window for a peak detector. A plot of the decision variables for the peak detectors vs. ϕ is shown in Fig The threshold values are also shown, and are set at the peak amplitude of the interferer. Detection errors are seen to occur over a set of phases for the case where only the positive or negative threshold is used (e.g., for a single peak detector). However, at least one of the detection thresholds is crossed for all values of ϕ, which means a dual peak detector would make a correct decision. As with the energy detector, the BER is found by calculating the percentage of ϕ values that will cause Y 1,max to be below the positive threshold for a single peak detector. For a dual peak detector, the BER is found by calculating the percentage of ϕ values where both Y 1,max and Y 1,min are below their respective thresholds simultaneously. Ph.D. Thesis K. Allidina

80 1 Y 1,max 0.5 Threshold Amplitude Threshold Y 1,min Fig. 3-7: Amplitude vs. the phase of the interferer for the peak detector test statistics in the presence of one narrowband interferer Performance Comparison Phase of Interferer (rads) Using the results from the previous sections, the probability of error was calculated for both an energy detector and the peak detectors for single-tone interferers located at 30%, 50%, and 70% of the pulse bandwidth (e.g., for a pulse with an 870 MHz bandwidth, the interferers are at frequencies of 260 MHz, 435 MHz, and 610 MHz). As stated earlier, the phase of these interferers is a uniformly distributed random variable. Fig. 3-8 shows plots of the BER vs. the ratio of energy per bit to the interference power spectral density (E b /I 0 ), where I 0 is the interference power averaged over the 870 MHz pulse bandwidth. BER (Interferer at 30% of Pulse Spectrum) B C A A: Energy Detector B: Dual Peak Detector 10-4 C: Single Peak Detector E b /I 0 (db) (a) BER (Interferer at 50% of Pulse Spectrum) A: Energy Detector B: Dual Peak Detector 10-4 C: Single Peak Detector E b /I 0 (db) (b) Fig. 3-8: Theoretical BER results for an energy detector, a single peak detector, and a dual peak detector in the presence of a single narrow-band interferer located at various percentages of the pulse bandwidth. B C A BER (Interferer at 70% of Pulse Spectrum) B A: Energy Detector B: Dual Peak Detector C: Single Peak Detector E b /I 0 (db) (c) A C Ph.D. Thesis K. Allidina

81 We can see that both peak detectors outperform the energy detector for lower frequency interferers, and the energy detector starts to outperform the single peak detector as the frequency of the interferer increases. The dual peak detector actually performs much better as the interferer frequency is increased, and for the interferer at 70% of the pulse spectrum, it can actually function when the total bit energy is less than the interference power spectral density. The period of the interferer in this case is around 1.6 ns, which is less than the pulse width. This ensures that constructive interference occurs at either the negative or positive peak of the pulse, pushing the amplitude above the threshold level. However, in an actual system, this case is unlikely to be a dominant factor due to the presence of multiple interferers spread over the pulse spectrum. This scenario will be considered through the system simulations presented in the next section. 3.5 Simulation Results Full simulations were run using Matlab to test the performance of the detectors in the presence of noise and multiple interferers. The pulse repetition rate for these simulations is 1 MHz, and perfect synchronization is achieved in all simulations prior to measuring the detector performance. The simulations were run using both an AWGN channel and a 100 MHz 1 GHz indoor channel model from the IEEE a UWB working group to account for multipath reflections [96]. In the latter case, 100 channels were used for the simulations. The root mean square (RMS) delay for these channels is shown in Fig. 3-9, and it ranges between 2 ns and 5.5 ns, with the average being ~4.1ns. Ph.D. Thesis K. Allidina

82 RMS Delay (ns) Individual Channel Delay Mean Chnanel Delay Channel Number Fig. 3-9: RMS delay for the 100 multipath channels. The number of significant paths for these channels is defined as the number of paths that have attenuations of less than 10 db when compared to the peak path. Using this definition, the number of significant paths are shown in Fig On average, there are ~5.5 significant paths between the transmitter and the receiver Number of Channels Number of Significant Paths (within 10 db of peak) Fig. 3-10: Histogram of the number of significant paths in each channel. Examples of how the input pulse is distorted when passing through these channels are shown in Fig The input pulse is shown in Fig. 3-11a, and the output pulses for the two example channels is shown in Fig. 3-11b and Fig. 3-11c. Ph.D. Thesis K. Allidina

83 Amplitude Amplitude Amplitude Fig. 3-11: Examples of two channel outputs (b, c) when the input pulse (a) is passed through these channels AWGN Channel Results (a) (b) Time (ns) Simulations in the presence of noise were run for the peak detectors and the energy detector in an AWGN channel, and these results are compared with the theoretical results derived earlier in Fig The close match between the simulated and theoretical results validates the derivations and conclusions presented earlier. (c) ns Window 6ns Window ns Window 6ns Window ns Window 6ns Window BER for Single Peak Detector BER for Dual Peak Detector BER for Energy Detector E /N (db) b o E /N (db) b o E /N b o (db) Fig. 3-12: Comparison between the theoretical results (solid lines) and simulated results (circles) for the peak detectors and the energy detector. Ph.D. Thesis K. Allidina

84 To test the performance of the detectors in the presence of narrowband interference, five in-band interferers were used. The amplitude, frequency and phase of these interferers were assumed to have uniform distributions [106], and were randomly changed every 10 μs. The noise power was set to 20 db below the interference power to provide a conservative realization of the measurements obtained in [18, 19] (which showed the noise power was ~40 db below the interference power). Fig shows a plot of the BER vs. E b /I 0, where I 0 is the total interference power averaged over the 870 MHz bandwidth. Two clusters of curves can be seen the best performance is seen by the dual peak detector with a 2 ns and 6 ns window, and the energy detector with a 2 ns window. The single peak detector with both a 2 ns and 6 ns detection window and the energy detector with a 6 ns detection window show a performance that is ~1.2 db worse. It is important to note that the performance of the peak detectors only decreases slightly for longer detection windows. In contrast, the energy detector performance decreases substantially as the detection window is increased since the integration of the additional interference energy degrades the ability to make a correct decision BER A: Single Peak Detector - 2ns Window B: Dual Peak Detector - 2ns Window C: Energy Detector - 2ns Window D: Single Peak Detector - 6ns Window E: Dual Peak Detector - 6ns Window F: Energy Detector - 6ns Window B E CA F D E b /I o (db) Fig. 3-13: Simulation results comparing the peak and energy detector performance in an AWGN channel with narrowband interferers. Ph.D. Thesis K. Allidina

85 3.5.2 Multipath Channel Results The multipath channel described earlier was used to simulate the peak detectors and energy detector in the presence of noise and interference. Fig shows simulation results for both the peak detectors and energy detector in the presence of noise. For windows of 2 ns, the dual peak detector performs slightly better than the energy detector. However, the energy detector performance improves with window size as more signal energy is collected from the multipath reflections. The performance of the single peak detector is ~1.5 db worse than the dual peak detector for both window sizes BER A: Single Peak Detector - 2ns Window B: Dual Peak Detector - 2ns Window C: Energy Detector - 2ns Window D: Single Peak Detector - 6ns Window E: Dual Peak Detector - 6ns Window F: Energy Detector - 6ns Window E b /N o (db) Fig. 3-14: Simulation results comparing the performance of the peak detectors and energy detector in a multipath channel with noise. Fig shows a plot of the E b /N 0 required to obtain a BER of 10-3 vs. the detection window duration for all detectors. This figure shows that the performance of the peak detectors decreases with an increasing window size. This is because the detectors initially synchronize to the highest amplitude portion of the received signal, and widening the detection window only increases the probability that noise will cause an error. As Fig shows, the energy detector performance does improve as the detection window is increased up to ~12 ns due to the collection of more multipath energy. However, as the Ph.D. Thesis K. Allidina F B C E A D

86 integration window increases past this point, the multipath signals contain less energy than the background noise and the performance starts to deteriorate E b /N o (db) Single Peak Detector Dual Peak Detector Energy Detector Detection Window Duration (ns) Fig. 3-15: Plot of the E b /N 0 required to obtain a 10-3 BER vs. detection window duration for the peak detectors and energy detector in a multipath channel. Fig shows simulation results for both the peak detectors and energy detector in the presence of five narrowband interferers with the same parameters as in the AWGN channel simulation. It can be seen that the performance of the dual peak detector and energy detector is roughly the same for both a 2 ns and 6 ns detection window duration, while the performance of the single peak detector is ~1.8 db worse for both windows. The performance of the peak detectors increase with window size in the presence of interference, which is opposite from the behavior observed in the presence of noise. This is due to the deterministic nature of the interference amplitude, which can be used to set the threshold value of the detector. Ph.D. Thesis K. Allidina

87 BER A: Single Peak Detector - 2ns Window B: Dual Peak Detector - 2ns Window C: Energy Detector - 2ns Window D: Single Peak Detector - 6ns Window E: Dual Peak Detector - 6ns Window F: Energy Detector - 6ns Window E /I (db) b o Fig. 3-16: Simulation results comparing the performance of the peak detectors and energy detector in a multipath channel with narrowband interference. Fig shows a plot of the E b /I 0 needed to achieve a BER of 10-3 vs. the window duration for all detectors. The performance of the energy detector is much the same as in the presence of noise with a minimum value achieved for a detection window duration of around 11 ns. In contrast, the performance of the peak detectors increase with the window duration until optimal performance is reached for a 16 ns window. It can also be seen that the E b /I 0 required to obtain a BER of 10-3 for the dual peak detector is less than that required by the energy detector for window durations longer than ~8 ns. The single peak detector performs better than the energy detector for window durations longer than ~24 ns. The fact that the optimum performance for the peak detectors do not depend on a specific window size can be exploited to ease the constraints of the receiver design at the circuit level for systems operating in interference dominated environments. E F B C D A Ph.D. Thesis K. Allidina

88 Single Peak Detector Dual Peak Detector Energy Detector 13.5 E b /I o (db) Fig. 3-17: Plot of the E b /I 0 required to obtain a 10-3 BER vs. detection window duration for the peak detectors and energy detector in a multipath channel. 3.6 Summary Detection Window Duration (ns) This chapter evaluated the performance of UWB receivers based on energy and peak detectors in the presence of noise and interference, both in AWGN channels and multipath channels. It was observed that a receiver based on peak detection can perform on-par or better than an energy detector in interference dominated environments (such as urban areas) in both AWGN and multipath channels. This allows for the realization of non-coherent UWB receivers with simplified hardware and synchronization schemes without sacrificing performance. The design and implementation of an UWB receiver based on peak detection using a CDR synchronization scheme will be presented in the next chapter. Ph.D. Thesis K. Allidina

89 Chapter 4 - A Compact and Low Power UWB Transceiver with a Fast and low Complexity Synchronization Scheme A Compact and Low Power UWB Transceiver with a Fast and Low Complexity Synchronization Scheme 4.1 Introduction This chapter describes the UWB transceiver designed in this work. As discussed earlier, the inherent duty-cycled operation of pulse-based transceivers allows UWB radios to achieve energy efficient communications for low data rate systems, such as those used in many wireless sensor network applications. This chapter focuses on the design of an UWB transceiver for use in the MHz band to increase energy efficiency, as compared to operation above 3.1 GHz. While the antenna size for this frequency band renders this system unattractive for mobile devices, applications such as structural health monitoring of urban infrastructure (e.g., the structural integrity of bridges) do not have this size constraint. It should also be noted that the path loss when operating below 960 MHz is reduced due to the lower operating frequency, which may allow the use of smaller antennas with lower efficiencies. Additionally, high contrast dielectrics (ε r > 100) can be used to create physically small wideband antennas that operate at 1/10 th of the wavelength instead of the usual 1/4 th of the wavelength [97]. Efficient low data rate receivers based on energy detection and correlation have previously been implemented in [79, 80, 88-90, 107, 108]. Due to their windowed nature of operation, they employ relatively complex pulse synchronization schemes involving delay chains for timing, multiple switching integrators (or correlators), and digital backend processing. This leads to complex and/or lengthy synchronization procedures, and this problem is aggravated at low data rates where pulse widths are small compared to the pulse repetition rate. Ph.D. Thesis K. Allidina

90 This same type of situation exists in burst mode transceivers which have a high instantaneous data rate but implement duty-cycling at the packet level. In this case, efficient and fast packet-level synchronization is required to create an optimal solution. Additionally, since the UWB pulses in burst mode communications are condensed into a smaller time period, each pulse must have less energy in order to meet FCC regulations, in which the power spectral density of the pulse train is measured over a 1 ms time span. For this reason, this work focuses on non-burst-mode UWB communications. Synchronization time and complexity can be decreased by increasing the window of integration in energy detection receivers, but this decreases the performance of the communications link due to the collection of additional noise and interference. The receiver here focuses on peak detection instead of energy detection to create a single path receiver that does not suffer from cumulative noise and interference integrated within the detection window. The synchronization scheme is based on a clock and data recovery system, which effectively transfers the pulse synchronization process to the analog domain. This reduces the amount of digital circuitry and its associated leakage current, allowing for a low complexity and energy efficient implementation. This method also enables continuous compensation for any jitter associated with either the transmitted data or receiver clock, which relaxes the timing requirements of both systems. This minimizes the need for a high accuracy crystal reference in the transmitter and receiver, leading to a lower cost solution. A control signal for duty-cycling the RF front-end is readily derived from the synchronized receiver clock, which results in a significant power reduction. The transceiver implemented here uses on-off keying modulation with a nominal data rate of 1 Mbps. The transceiver achieves a receiver efficiency of 292 pj/pulse and a transmitter efficiency of 115 pj/pulse, making it attractive for sensor nodes that require increased battery longevity, and also provides for the possibility of powering sensor nodes using energy harvesting techniques. This chapter will first discuss system level requirements of the receiver, followed by the circuit level design of the receiver and transmitter. Measurement results of the transceiver will be presented next, along with a comparison with other recent works. Ph.D. Thesis K. Allidina

91 4.2 System Level Description of the Receiver Fig. 4-1 shows a simplified block diagram of the receiver. The RF front-end is responsible for amplifying a received UWB pulse to digital levels, and the CDR circuitry synchronizes the receiver and outputs the baseband data and clock signals. Once synchronization is achieved, the CDR system is also responsible for cycling the analog circuits so that they are only consuming power when a signal is expected. RF Front End Cycle Control Signal Clock and Data Recovery Circuit Cycle Bias Generator Output Data Output Clock Fig. 4-1: Block diagram of the UWB receiver. To determine the necessary sensitivity of the receiver, an estimate of the losses incurred in the wireless communications link must be made. The link budget for continuous wave RF systems is based on the SNR of the transmitted signal, which has a (roughly) constant power in the time domain, and a constant relationship between the symbol rate and the signal bandwidth given a specific modulation scheme. This approach cannot be directly applied to IR-UWB communications, since the instantaneous SNR varies based on the presence or absence of a signal pulse. A processing gain can be used to account for the fact that the average power of an UWB waveform is compressed into a short duration pulse, and this processing gain (PG) is given by [16, 109]: BW PG = 10 log, (4.1) R b where BW is the bandwidth and R b is the data rate. Note that this processing gain comes directly from the relationship between E b /N 0 and the SNR. The path loss for an UWB channel (assuming unity gain infinitesimal antennas are employed) can be derived as [11]: Ph.D. Thesis K. Allidina

92 P L 4πf cr = 20 log, (4.2) c where c is the speed of light in a vacuum, f c is the geometric mean of the pulse spectrum, and r is the distance between the two antennas. The received power at the antenna is given by: P = P + P, (4.3) RX where P TX is the transmitter power. In this equation, all quantities are in the logarithmic domain (e.g., units of db for the path loss and units of dbm for the transmit and receive power). The noise power at the receiver can be calculated using the equation: TX L N P = 10 log( kt ) + 10 log( BW ) + NF, (4.4) where k is Boltzman s constant, T is the temperature in Kelvins, BW is the bandwidth in Hz, and NF is the receiver noise figure. The link budget calculation and parameters are given in Table 4-1, where it is assumed that the desired communications distance is 5 m, and antennas with a 0 db gain are used in both the transmitter and receiver. Band of Operation Bandwidth Data Rate Transmit Power Geometric Mean of Frequency Band Path Loss for r = 5 m Received Power Receiver Noise Figure Noise Power (@ 25 degc) TX Implementation Loss RX Implementation Loss Processing Gain Required E b /N 0 for BER < 10-3 Link Margin Table 4-1: Link Budget Calculation 100 MHz to 960 MHz BW = 860 MHz R b = 1 Mbps P TX,MAX = dbm/ MHz + 10logBW (MHz) P TX,MAX = dbm f c = 310 MHz P L = 36.8 db P RX = P TX P L = 56.7 dbm 10 db P n = 174 dbm / Hz + 10logBW (Hz) P n = 84.5dBm IL TX = 6 db IL RX = 10 db PG = 27 db S =13.5dB LM = P TX P L P n NF IL S +PG LM = 15.3 db Ph.D. Thesis K. Allidina

93 It is assumed that the maximum available power is used in the transmitter, which corresponds to the maximum power spectral density of dbm/mhz multiplied by the bandwidth of 860 MHz. This is generally not the case in practical systems since the signal must be shaped to avoid interfering with the sensitive GPS band. This can result in a power loss of 3 db or higher, and the reduced bandwidth will also affect the processing gain in the receiver since the pulse duration will be longer. The reduced bandwidth will also have a small positive effect by lowering the frequency of transmission, which will reduce the path loss. The negative effects due to the reduced bandwidth are accounted for in the 6 db TX implementation loss. It is assumed that the receiver noise figure is 10 db, and a 10 db implementation loss is included in the receiver to account for effects such as multipath channel effects and a non-optimal threshold in the peak detector. The required SNR for the peak detector is obtained from the theoretical analysis presented earlier. The link budget calculation shows that there is a 15.3 db margin, allowing for options such as smaller antennas with lower efficiencies to be used, as mentioned earlier. Since the receiver used here is based on peak detection, calculating the voltage level of the received pulse will define the minimum detectable voltage level needed. A received power level of dbm translates to a sine wave with a peak voltage of 460 µv across a 50 Ω load. Accounting for the 27 db processing gain due to the compression of this power to within the short-time duration UWB pulse, the peak voltage of the signal will be 10.3 mv. This level of processing gain is applicable if the full UWB spectrum is used. As mentioned earlier, this will typically not possible if the GPS stopband required by the FCC mask is adhered to. Using the 6 db transmitter implementation loss that accounts for the reduced bandwidth results in an UWB signal with a peak voltage of 5.15 mv. To account for additional losses that may occur due to process variations and other nonidealities in the IC design, the target level for the receiver s voltage sensitivity is 1 mv. 4.3 Ultra-Wideband Receiver Design The following sections will describe the circuit level design of the RF front-end and the CDR circuitry. Ph.D. Thesis K. Allidina

94 4.3.1 RF Front-End An expanded view of the RF front-end is shown in Fig Input (Antenna) LNA Amplifier Chain AC DC Comparator Digital Buffer Output (To CDR) Fig. 4-2: Expanded view of the RF front-end. The signal is first amplified by an LNA and gain stages, and is then compared with a lowpass version of itself to remove any slow-varying offsets. A large input signal will trigger the comparator, which indicates that a pulse was received. The following sections will describe the individual circuits that make up the RF front end The LNA The task of the LNA is to amplify the signal while simultaneously minimizing the degradation of the SNR. As discussed earlier, the interference associated with narrowband systems is more detrimental than the noise, which means the system noise figure specification can be relaxed without limiting performance. The wideband nature of the signal also somewhat relaxes the linearity specification of the LNA since intermodulation distortion is not an issue for non-coherent receivers. (This is an issue in narrowband receivers since distortion can cause power from interferers to enter the desired signal spectrum [110] in UWB systems numerous interferers already lie within the signal spectrum!) The specifications for this design are a gain of more than 10 db, a noise figure of less than 6 db, and an input-referred third order intercept point (IIP3) greater than -5 dbm. Matching the LNA to the 50 Ω input impedance of the antenna can be challenging for low-power systems, and the low frequencies in the chosen band of operation ( MHz) also comes with additional restrictions. Low noise multi-band resonant tanks [111, 112] cannot be used since the low operating frequencies would necessitate large component values that are unsuitable for on-chip integration. This suggests the use of topologies such as those shown in Fig. 4-3, which can provide a wideband input match at the cost of a higher noise figure [5, 19, 113, 114]. Ph.D. Thesis K. Allidina

95 R L R L R L V OUT V OUT R F V OUT V BIAS V IN V IN V IN R T Fig. 4-3: Wideband amplifier topologies: a) resistively terminated common-source amplifier, b) shunt-feedback amplifier, and c) common-gate amplifier. Table 4-2 shows the equations for the input impedance and noise figure of the LNAs in Fig The noise due to the gate resistance has been ignored in this analysis since it can be minimized by using proper layout techniques. In the equations, R s is the input source resistance, r o is the output resistance of the transistor, γ is a noise correction factor that is 2/3 for long-channel transistors and 2-3 for short-channel transistors, and α = g m /g d0 [5]. The resistively terminated common-source amplifier is able to provide a 50 Ω match with no power consumption; however, g m must be greater than 25 ma/v to meet the 6 db noise figure requirement. The shunt-feedback and common-gate amplifiers can both meet the noise figure requirements with a g m of 5 ma/v (if the noise contribution from the resistances is ignored), but g m has to be at least 20 ma/v to provide a 50 Ω input match [19]. In the chosen CMOS 90 nm technology, a typical value for the current efficiency g m /I d is 12 V -1, which means a current of ~1.7 ma is the minimum requirement for these topologies. This leads to an unacceptably high power consumption. Table 4-2: Equations for the input impedance and noise figure of the LNAs in Fig Input Impedance Noise Figure (a) (b) (c) Resistively Terminated CS Amplifier (Fig. 4-3a) F R T γ 2 + α 4 g m R s Shunt Feedback Amplifier (Fig. 4-3b) R F 1 + g F + R m L ( R γ 1+ α L r o r 1 o ) g m R s 50Ω Match no constraint on g m g m 20mA / V 6dB Noise Figure g m 25mA / V g m 5mA / V F CG Amplifier (Fig. 4-3c) 1 g m R 1 + ro γ 1+ α L 1 g m R s g m 20mA / V g m 5mA / V Ph.D. Thesis K. Allidina

96 The LNA designed here is shown in Fig It is based on a common gate amplifier (M1) with feedback provided by M2 to reduce the current needed to achieve a 50 Ω input match. Transistor M3 functions as a current source, and is also used as the control mechanism to turn the LNA on and off during duty-cycled operation of the UWB receiver. This topology ensures that the same bias current is reused by all of the transistors to reduce power consumption. V DD V BIAS,P M 3 V BIAS,CG M 1 V OUT V IN M 2 Fig. 4-4: LNA topology based on a common-gate amplifier with active feedback. The small-signal model is shown in Fig. 4-5, where C out includes C gs2, C gd1, and the capacitance of the current source transistor M3. The additional transconductance caused by the body effect in transistor M1 is included in g m1. V out V in g m1 V gs1 r o1 C gd2 Cout r o3 + V gs2 - - g m2 V gs2 r o2 C gs1 V gs1 + Fig. 4-5: Small-signal model of the LNA. Ph.D. Thesis K. Allidina

97 The output impedance of M2 can be ignored as long as it is significantly larger than the 50 Ω source impedance (R S ) since these two resistances will be in parallel. This criterion is easy to achieve, even in deep submicron technologies. The low frequency input impedance of the LNA can be derived as: Z g + g o1 o3 in ( ω = 0), (4.5) g m1g m2 where output conductances have been used instead of resistances to simplify the equation. The output conductance of the current source M3 can be reduced by using a longer channel transistor, so g o1 will be the dominant term in the numerator. As presented in Table 4-2, the input resistance of a regular common-gate amplifier is 1/g m. By equating this to the output resistance derived in (4.5) and assuming equivalent transconductances (e.g., equivalent transistor sizes and bias current), we can see that this circuit reduces the input impedance by a factor of g o1 /g m. Since g o1 will always be smaller than g m, the feedback does indeed reduce the input impedance of the amplifier as compared to a common-gate amplifier using the same bias current. Including the capacitances in the analysis of the input impedance yields: Z in sc + g + g out o1 o3. (4.6) 2 s Cgs 1Cout + sg m1cout + g m1g m2 This equation shows that there is an inductive component to the input impedance that is caused by the feedback loop, which forms a gyrator or active inductor [115]. The inductive portion of the input impedance can be represented as: C g g out L. (4.7) m1 m2 Care must be taken to ensure that the value of this inductance is small such that it does not affect the circuit below 960 MHz, and does not cause any instability. The low-frequency gain of the circuit is given by: Ph.D. Thesis K. Allidina

98 V V out in g m1 + g o1 1 ( ω = 0), (4.8) R g ( g + g ) + g R g s m2 o1 m1 o1 s m2 which shows that the gain can be maximized by increasing the transconductance of M1 and decreasing the transconductance of M2. The dominant poles will be formed by the capacitors C out and C gd2 since the input capacitance sees a low impedance due to R s. The pole frequencies can be expressed as: ω ω p, Cgd 2 p, Cout g g m2 m2 Rs ( g m1 + g o1) + g (1 + R g ) C s s m2 m1 gd 2 Rs ( g m1 + g o1) + g (1 + R g ) C out o1 o1. (4.9) It can be seen that minimizing the gain maximizes the operating frequency, as does minimizing the output impedance of transistor M1. The noise factor can be analyzed by including the drain noise of M1 and M2, and the noise of the current source. As mentioned before, gate noise has been neglected since a careful layout can reduce the value of gate resistance such that it is insignificant. After simplification, the noise factor equation is: F 1 g 1+ γ + g m2rs Rs g α + m1 R o3 2 s g m1. (4.10) This equation shows that the noise factor can be minimized by increasing the transconductance of M1 and decreasing that of M2 (i.e., increasing the gain). Based on these theoretical equations, the circuit should have the following characteristics: A small transconductance from M2 will increase the gain of the amplifier and reduce the noise figure. Since the transconducance of M2 is small, a larger transconductance is required from M1 to present a 50 Ω input match, as well as to reduce to value of the inductive component of the input impedance. A larger transconductance for M1 will also reduce the noise figure of the circuit. Ph.D. Thesis K. Allidina

99 As with most designs, the output resistance of the current source transistor M3 should be as high as possible. The capacitances should be kept small but this criterion is not too restrictive given the maximum operating frequency of ~1 GHz. These guidelines were used to design the LNA, and the circuit was simulated using a unity gain buffer to drive a 50 Ω load so the results could be compared with other works from the literature. In the fabricated receiver, this buffer will not be present and the output of the LNA will drive the next stage directly. The results for S11 and S21 are shown in Fig. 4-6 and Fig. 4-7, respectively. These results show that the LNA is input matched over the desired bandwidth. The inductive portion of the input impedance was simulated to be ~1 nh, which is small enough to have almost no effect at the frequencies of interest. The gain of the amplifier is 10.5 db, and the 3-dB bandwidth is 1.66 GHz. Fig. 4-6: The S11 response of the LNA. Ph.D. Thesis K. Allidina

100 Fig. 4-7: The S21 response of the LNA. The noise figure response is shown in Fig At low frequencies the flicker noise of the transistors increase the noise figure, which drops below 6 db at 100 MHz. The minimum noise figure is 5.55 db, and the average across the entire band is 5.64 db. Fig. 4-8: The noise figure of the LNA. Two-tone tests were applied to determine the IIP3 of the LNA. Fig. 4-9 shows the IIP3 response at a frequency of ~500 MHz, and Fig shows how it varies over the entire band. It stays fairly constant around the average value of -4.4 dbm, dipping just below -5 dbm near the upper edge of the band. Ph.D. Thesis K. Allidina

101 Fig. 4-9: The IIP3 of the LNA at a frequency of 500MHz. Fig. 4-10: The IIP3 of the LNA vs. frequency. The DC current consumption of the LNA is 425 μw from a 1 V supply, yielding a power consumption of 425 μw. The leakage current when the current source transistor M3 is used to power down the LNA is under 3 μa. The turn-on time of the LNA is ~1 ns. Table 4-3 summarizes the performance of the LNA and compares it to other published wideband LNAs operating below 1 GHz. The gain of this LNA is slightly lower than others, leading to a slightly higher noise figure, but both parameters are still comparable to other designs. The IIP3 of this LNA is also similar or better than others despite the fact that it operates from the lowest supply voltage. The power consumption of this LNA is the lowest among the circuits compared here. It should also be noted that the other Ph.D. Thesis K. Allidina

102 works in Table 4-3 have reported measurement results, while the results from this LNA are from simulations since it was designed to be a part of the overall UWB receiver. Table 4-3: Performance Comparison of Wideband LNAs in the Band of Interest This Work [114] (2002) [116] (2005) [19] (2006) [117] (2007) [118] (2009) Technology 90nm 0.25μm 0.18μm 0.13μm 90nm 0.18μm CMOS CMOS CMOS CMOS CMOS CMOS Bandwidth (MHz) Gain (db) NF (db) IIP3 (dbm) Supply Voltage (V) Power Consumption (mw) The Amplifier Chain The gain stage amplifiers are required to increase the amplitude of the input signal while maintaining the goal of low power operation. The chain must also provide a reference signal to the comparator such that variations in the DC bias of the output signal can be effectively canceled out. The amplifier chain is shown in Fig The 1 st and 2 nd stage common-source amplifiers formed by M1 and M2 provide a tunable gain that is controlled by the voltages V ctrl1 and V ctrl2. A large resistor (R1) is included to provide a small amount of shunt feedback in these amplifiers. This reduces the sensitivity of the gain variation caused by the tuning voltages V ctrl1 and V ctrl2, allowing for easier tuning at the price of a slightly reduced total gain. The buffers composed of M3 and R2 are placed between the gain stages to prevent loading effects from reducing the gain. The output of the 2 nd stage amplifier is split into two paths to generate the inputs to the comparator: the actual signal, and the bias point, which is the signal filtered by R LP and C LP. Special attention was given during the layout of these final two buffers to ensure the transistors and resistors were matched in the presence of process variations (e.g., common-centroid layout, dummy structures to make sure the resistances experienced the same boundary conditions, etc.). Ph.D. Thesis K. Allidina

103 V DD V ctrl1 M2 R2 V ctrl2 M2 R2 R1 R1 M3 V out,signal V in M1 M3 M1 1 st Stage Buffer 2 nd Stage R2 R LP V out,lp M3 C LP Output Stage Fig. 4-11: Schematic of the amplifier chain. To provide duty-cycled operation in the UWB receiver, switches must be added. The full schematic of the amplifier chain is shown in Fig. 4-12, where transistors M4 and M5 are used to cycle the operation of the circuits. Note that the buffers have both NMOS (M4) and PMOS (M5) switches. This is to help maintain the bias point, which decreases the required turn-on time of the circuits. V DD V SW,P M5 M5 M5 V in V ctrl1 R1 M2 M1 R2 M3 V ctrl2 R1 M2 M1 R2 R2 V out,signal M3 M3 R LP V out,lp C LP V SW,N M4 M4 M4 M4 M4 1 st Stage Buffer 2 nd Stage Output Stage Fig. 4-12: Schematic of the amplifier chain including the switches required for duty-cycled operation. The simulated response of the signal path through the amplifier chain using the maximum gain setting is shown in Fig The maximum gain is ~40 db with a bandwidth from 74 MHz to 1.14 GHz. (A decoupling capacitor was used at the input of the amplifier to Ph.D. Thesis K. Allidina

104 prevent the bias voltage on the input node from affecting the LNA, which leads to the bandpass response.) Fig. 4-13: Simulated response of the amplifier chain. The value of the gain can be tuned by ~40 db through the control voltages, and Fig shows how the gain at 500 MHz varies with V ctrl1. Fig. 4-14: Simulated tuning range of the gain with V ctrl1. The current consumption of the entire chain is 465 μa, and a turn-on time of ~45 ns is needed to reach full gain. This turn-on time can be reduced by removing the feedback resistors R1 in the common-source amplifiers, which increases the time needed to stabilize the bias points at these nodes. Ph.D. Thesis K. Allidina

105 The Comparator The comparator uses the two outputs from the amplifier chain to determine whether a pulse has been received, and its schematic is shown in Fig The comparator is based on a differential pair in which M2 is twice the size of M1 to avoid false detections in the presence of noise and process variations. This effectively creates a threshold that the received pulse must surpass in order to be detected. If the received signal is large enough, it will cause the output of the differential pair to increase past the threshold of the digital buffer and the output of the comparator will become a logic 1. It should be noted that alternative comparators based on positive feedback [38] or rectification to detect both positive and negative peaks [119] can also be used with this receiver architecture. V DD V in,signal M3 M1 M2 (2X M1) M4 Digital Buffer V in,lp Output of RF Front End V bias M5 Fig. 4-15: Schematic of the comparator. The switching threshold of this setup was determined through Monte Carlo simulations of this block over process and mismatch (assuming a matched layout for the input differential pair). The results are shown in Fig. 4-16, and the minimum threshold is 20 mv. This ensures that no spurious pulses will be generated in the presence of noise only, and gives an additional safety margin to prevent in-band interferers from triggering the comparator. Ph.D. Thesis K. Allidina

106 Number of Samples Switching Threshold (mv) Fig. 4-16: Monte-Carlo simulation results to determine the switching threshold of the comparator in the presence of process and mismatch. It should be noted that using a controlled mismatch in the differential pair with a fixed threshold voltage offers less flexibility than a matched pair with a tunable threshold voltage, however, the goal here was to realize a self-contained structure that provides protection against false detection in the presence of noise and interference. The digital buffer also performs a hold operation when the comparator is triggered to ensure that the narrow UWB pulse is detected by the CDR circuitry, and to provide some immunity against multipath echoes. Essentially, the digital buffer output remains high for ~20 ns whenever the comparator is triggered, regardless of the input pulse width and number of pulses received in this timeframe. This operation is implemented using a digital delay line composed of long-channel buffers and flip-flops that reset the digital buffer. The comparator is duty-cycled though the bias transistor M5. To ensure that feedthrough of the control signal does not incorrectly trigger an output pulse, the enable signal for the digital buffer in Fig is delayed relative to that for the amplifier and comparator enable signals. The current consumption of the comparator is 200 μa. Ph.D. Thesis K. Allidina

107 RF-Front End Summary Simulations were run on the entire front-end using a single cycle of a sinusoid to emulate an UWB pulse. The input was applied to the LNA and the output was taken from the digital buffer in the comparator. The minimum input signal needed to trigger the comparator and create a digitally compatible output is 550 μv. The turn-on time to achieve this is 80 ns, however, a reduced turn-on time can be used if the maximum gain is not needed. For instance, if a turn-on time of 40ns is used, the gain decreases by around 6 db due to non-optimal biasing of the transistors in the amplifier chain, and the minimum detectable signal is ~1 mv. As discussed before, the output of the RF front-end goes to the clock and data recovery system which is responsible for synchronizing the receiver and generating the signal to perform the duty-cycling of the front-end. This block will be discussed next Clock and Data Recovery System The clock and data recovery circuit is shown in Fig It consists of a phase / frequency detector (PFD), two charge pumps, a loop filter, and a VCO. Pulse Input Cycle Control Output Phase Frequency Detector Cycle Bias Gen. Phase Control Frequency Control Charge Pump Charge Pump Loop Filter VCO Output Data Output Clock Fig. 4-17: Block diagram of the clock and data recovery system. The PFD detects the phase and frequency difference between the clock and data signals and varies the output current of the charge pumps accordingly. This current is averaged and converted into a voltage by the loop filter and fed to the VCO, whose output clock is fed back into the PFD. The feedback loop synchronizes the clock and data signals by forcing their edges to align. Once the loop is locked (i.e., synchronization has been achieved), the operation of the front-end amplifiers can be cycled such that they only consume power when an incoming pulse is expected. Ph.D. Thesis K. Allidina

108 To determine how quickly the CDR system can synchronize the receiver clock to the received pulse, a brief review of CDR dynamics is needed. This analysis will focus on the case where the clock and data frequencies are close to equal and the phase detector is driving the loop towards synchronization. The behavior will be analyzed as if the CDR loop was a continuous time system, and the issues introduced by this approach will be pointed out. The open loop transfer function of the CDR system shown in Fig in terms of phase is given by: Φ OUT KVCO = H OL ( s) = K PD I CPZ LF ( s), (4.11) Φ s IN where Φ IN is the input to the phase detector, Φ OUT is the output of the VCO, K PD is the gain of the phase detector, I CP is the charge pump current, Z LF is the impedance (or current-to-voltage transfer function) of the loop filter, and K VCO is the gain of the VCO. The output of the VCO is a frequency signal, and is integrated (multiplied by 1/s) to get the phase. As will be shown later, the gain of the phase detector (PD) in this work is (1/2π V/rad) and the impedance of the loop filter is given by ( 1R 1) sc1 (4.11) yields the equation: sc +. Substituting these into H OL ( s) = I CP sc R + 2π sc1 1 1 K s VCO. (4.12) We can see that the open loop transfer function has two poles at the origin, and is thus referred to as a type II system. Due to the two poles, the zero at 1/C 1 R is needed to create a stable loop. The closed-loop transfer function of the CDR loop is given by: H CL ( s) I K ( src + 1) CP VCO 1 H OL ( s) 2πC1 = =. (4.13) 1+ H ( s) 2 I I CP K OL CP VCO s + s KVCO R + 2π 2πC1 This can be written in standard form for a second order system as follows: Ph.D. Thesis K. Allidina

109 H CL 2 n 2ζω ns + ω ( s) =, (4.14) 2 s + 2ζω s + ω where ω n is the natural frequency and ζ is the damping ratio. These parameters are given by: I CP KVCO ω n =, (4.15) 2πC 1 n 2 n R I CP KVCOC ζ = 1. (4.16) 2 2π From these parameters we can estimate the loop decay time constant, which is used as an estimate for the loop settling time in underdamped systems. τ DECAY 1 ω ζ =. (4.17) n From (4.15), (4.16), and (4.17), it appears as though increasing the charge pump current and VCO gain result in a wider loop bandwidth, a more stable system (due to the increase in the damping ratio), and a smaller settling time. This is one of the issues with approximating the discrete time loop with a continuous system as the bandwidth of the loop approaches the reference frequency, stability will be severely compromised. Typical PLL designs have a loop bandwidth of 1/10 th of the reference frequency, with the loop bandwidth being defined as the unity-gain frequency (or crossover frequency) of the open loop response. Since this CDR system is based on RZ data, information on the timing of the data pulse will only be available when a 1 is received. Reducing the loop bandwidth to account for this will result in a more stable system that can tolerate longer runs of consecutive 0 s, but will also increase the settling time of the loop and decrease its ability to track jitter in the received data. The approach chosen here is to ensure the loop is stable for a data stream that is composed of 50% 1 s, and 50% 0 s. For the desired 1 Mbps data rate, the loop bandwidth is chosen to be 1/20 th of the reference frequency, which is 50 khz. The loop bandwidth (ω c ) and phase margin (ϕ m ) of the open loop response can be related to the natural frequency and damping ratio by the equations [120]: Ph.D. Thesis K. Allidina

110 ω = ω cos( φ m ), (4.18) n c 1 sin( φm ) ζ =. (4.19) 2 cos( φ ) Since we know the damping ratio should be ~ 2 2 for a fast settling time, the framework to specify all of the loop parameters is now in place. Now that the overall dynamics of the CDR system have been reviewed, the design of the individual blocks of the system will be presented The Phase / Frequency Detector The functionality of a clock and data recovery loop is quite similar to that of a phaselocked loop, with the main difference being the phase detector. In a CDR system, the phase detector must be able to lock to a random data signal, rather than a periodic clock. Commonly used circuits for non-return-to-zero (NRZ) data transmission are the Hodge and Alexander PDs, [121] but these are not compatible with the narrow data pulse return-to-zero (RZ) communication scheme used here. A phase detector architecture that provides a linear output from pulsed data inputs was devised here specifically for this application, and the schematic is shown in Fig m V DD D Q CLK RST X1 DATA V DD CLK PHASE DOWN D Q CLK RST PHASE UP / DATA OUT CLK Fig. 4-18: Schematic of the phase detector. The data pulse is used to trigger two flip-flops, which are reset by the rising edges of the clock and its inverse. Subtracting the output of the XOR gate from the phase up signal Ph.D. Thesis K. Allidina

111 yields a signal whose average varies linearly with the delay between the rising edges of the data and clock signals, as will be shown in this section. Using the data signal to trigger the flip-flops ensures that no output is produced for a 0, which is the correct operation to maintain synchronization of the clock with the random data signal. Additionally, when the clock and data signals are synchronized, the phase up signal also represents the output data. Fig shows the clock and data waveforms for the cases where the data both leads and lags the clock signal. (a) Fig. 4-19: Phase detector waveforms for the cases where the (a) data leads the clock and (b) clock leads the data. When the data signal leads the rising edge of the clock (Fig. 4-19a), the phase up signal is on longer than the phase down signal, which means the clock must speed up. The Ph.D. Thesis K. Allidina (b)

112 opposite is true when the data signal lags behind the rising edge of the clock (Fig. 4-19b). Thus, the decision to either speed up or slow down the clock to synchronize its rising edge with the data can be made by evaluating the average value of the difference in these two signals, i.e., phase up phase down. Fig plots this signal vs. the data delay relative to the clock. 0.5 Average Voltage (V) < Linear with Delay 0.5 π/2 π/4 0 π/4 π/2 Data Delay (φ) Fig. 4-20: The average voltage output from the PD vs. the data delay relative to the clock. For a negative delay (i.e., the data signal leads the clock), the phase detector will indicate that the clock needs to speed up. For a positive delay (i.e., the data signal lags the clock), the phase detector will indicate that the clock needs to slow down. The PD is seen to present a linear output vs. delay with no dead zone, and the gain is 1/2π V/rad. A phase detector by itself will only allow the loop to lock if the frequencies of the data and clock signals are close enough for proper operation. A frequency detector (FD) is needed to create a more robust CDR. A common way to design a frequency detector is to use D flip-flops (DFFs) with both an in-phase and quadrature clock [121]. Fig shows the FD circuit devised for this work. CLK I D Q X1 D Q FREQ DOWN CLK CLK DATA CLK Q D Q X2 D Q FREQ UP CLK CLK Fig. 4-21: Schematic of the frequency detector. Ph.D. Thesis K. Allidina

113 The data signal is used to sample both the in-phase and quadrature clocks (CLK I and CLK Q, respectively), and these sampled values are used to trigger another set of DFFs. The data waveforms to illustrate how this serves as a frequency detector are shown in Fig. 4-22, where the internal signal X1 and X2 are shown on the schematic in Fig In Fig. 4-22a, the data is faster than the clock. When the two waveforms are compared, the data appears to be sliding to the left relative to the clock. Therefore, the rising edge of X1 will sample X2 when it is high, causing freq up to go high. The opposite situation occurs in Fig. 4-22b. The data is slower than the clock, and appears to be sliding to the right. This causes the rising edge of X2 to sample X1 when it is high, and causes freq down to go high. Similar to the phase detector, the decision to either speed up or slow down the clock can be made by evaluating the average value of the difference in these two signals, i.e., freq up - freq down. Ph.D. Thesis K. Allidina

114 (a) Fig. 4-22: Frequency detector waveforms for the cases where the (a) data is faster than the clock and (b) clock is faster than the data. Fig shows how the average values of the phase and frequency detector outputs ( phase up phase down and freq up freq down, respectively) change as the clock period is varied while the data period is fixed at 1 μs. It can be seen that the frequency control voltage will cause the clock to slow down if its period is smaller than the data period, and to speed up if its period is larger. It is also evident that the response of the frequency detector is not linear with respect to the frequency difference between the (b) Ph.D. Thesis K. Allidina

115 clock and data signals. Since the average value of the output jumps between +1 and -1, this is known as a bang-bang detector. The frequency control voltage in Fig appears to provide a narrow dead zone around the region where the clock and data periods are almost equal. This dead zone is actually an artifact due to the length of the simulation the data and clock signals are sliding past each other very slowly, leading to the illusion of a zero output from the FD within the simulation timeframe. Although this dead zone does not actually exist for the open loop FD, it will exist in the real CDR system due to the feedback; when the frequency of the data and clock signals are almost equal, the phase detector will take over the synchronization process and the frequency detector will be relatively quiet [122]. To ensure the FD does not affect the loop when the PD takes over, the frequency detector outputs are reset every 64 clock cycles. Fig also shows that the phase detector does not provide a usable output when there is a significant difference between the periods of the clock and data signals, which is the reason a frequency detector is needed. Ave. Voltage (V) Phase Control Voltage Lock Zone > 1 Frequency Control Voltage Ave. Voltage (V) Clock Period (µs) < Dead Zone Fig. 4-23: Average phase and frequency voltage outputs from the PD and FD, respectively, as the clock period is varied for a data period fixed at 1 μs. The results in this section have shown that the PFD can generate signals that can be used to control the clock frequency in order to align it with a data signal that has a different phase and frequency. To generate a usable VCO control voltage, circuits that can generate the average values of phase up phase down and freq up freq down from Ph.D. Thesis K. Allidina

116 the digital PFD outputs are needed. This is the function of the charge pumps and loop filter The Charge Pump The charge pump produces a current that corresponds to the control signals from the PFD. As shown in Fig. 4-17, there are two charge pumps in this design one for the phase control (PD output) and one for the frequency control (FD output). The same topology is used for each charge pump, and it is shown in Fig V DD V DD M12 M2 M15 M16 Up d M9 M10 Up d Up M5 M6 Up V DD Output M13 M14 Down Down d d M7 M8 M3 M4 Down Down M11 M1 Fig. 4-24: Schematic of the charge pump. The output branch of the charge pump is formed by M1-M6. Transistors M1 and M2 act as current sources, and are both long-channel transistors to reduce current mismatches due to channel length modulation. The complementary switches of M3-M6 determine when the current sources are connected to the output node, and a dummy branch of switches (M7-M10) is used to preserve the voltage at the drains of M1 and M2, thus avoiding current spikes due to charge leakage [123]. Complementary switches are used in both branches to mitigate non-idealities such as charge injection and clock feedthrough, provided proper layout techniques are used to match the transistors. The switches require eight control signals, and these are generated by an intermediate stage between the charge pumps and PFD. To eliminate changes in the drain voltage of M1 and M2 during transitions, the control signals are timed such that Ph.D. Thesis K. Allidina

117 there is a small overlap between when the output branch turns on and the dummy branch turns off, and vice-versa. A differential pair amplifier in a unity-gain configuration is also used to ensure that the voltage on the dummy branch matches that of the charge pump output [124]. The bias branch is formed by M11-M16, where transistors M13-M16 are present to reduce mismatch due to channel length modulation when mirroring currents to the active branches of the charge pump. As mentioned before, the charge pump topology used for both the phase detector and frequency detector outputs is the same. The only difference is amplitude of the charge pump current. The charge pump current controlled by the FD is four times smaller than that controlled by the PD to ensure a smooth transition between phase and frequency locking. The smaller FD current also reduces the current consumption of the CDR when the clock and data are synchronized and the FD does not have any effect The Loop Filter The output current of the two charge pumps (phase and frequency controls) are combined and sent to the loop filter, which is responsible for reducing the ripple on the VCO control line while ensuring a stable feedback loop. A passive loop filter is used in this design to minimize the power consumption, and its schematic is shown in Fig Capacitor C 1 produces a pole at DC, and resistor R provide a zero to stabilize the CDR loop. Capacitor C 2 is a small capacitor and is used to filter high-frequency noise. I in V out C 1 R C 2 Fig. 4-25: Schematic of the loop filter The Voltage Controlled Oscillator The VCO topology used in this design is shown in Fig A two-stage ring oscillator is chosen to minimize power consumption, and using an even number of stages directly produces both the in-phase and quadrature clocks necessary for proper PFD operation. Ph.D. Thesis K. Allidina

118 Once the system is synchronized, the quadrature clock is used to sample the data at the optimal point, and the inverse quadrature clock is used to generate the signal to dutycycle the RF front end. V Q + V I + V Q - V I - Fig. 4-26: Voltage controlled oscillator topology. The criterion for oscillation is to have a 360 phase shift around the loop with a gain that is greater than unity. In a differential ring oscillator, a phase shift of 180 comes from the signal inversion of the feedback, and an additional 180 comes from the poles of the system. The cascade of two single-pole amplifiers (as in Fig. 4-26) only produces a 180 phase shift at infinite frequencies, where the gain will be much less than unity. To create a two-stage oscillator, an additional phase shift must be introduced into each stage. Positive feedback is used to accomplish this additional phase-shift, and the block-level schematic of each delay stage is shown in Fig The inverters I1 and I2 form the delay elements for the signal path, while the latch formed by I3 and I4 is used to create the additional phase shift [125]. I1 and I2 are current-starved inverters so the delay of each stage, and thus the frequency of oscillation, can be tuned. V in + I1 I3 I4 V o - V in - V o + I2 Fig. 4-27: Block level schematic of each stage in the VCO. The circuit-level schematic of each stage in the ring oscillator is shown in Fig Inverters I1 and I2 are each formed by M1 and M2, and inverters I3 and I4 are each formed by M3 and M4. Transistors M5 and M6 limit the current through I1 and I2 based Ph.D. Thesis K. Allidina

119 on the value of V CTRL, which is the tuning voltage of the VCO. A fixed current is injected into I1 and I2 through M7 and M8 to reduce the gain of the VCO and to account for shifts in the frequency of oscillation due to process variations. The fixed current also prevents the stable zero current (no oscillation) state that would occur if V CTRL approached 0 V. Transistors M9-M12 are used to convert V CTRL and V BIAS into control voltages for the PMOS current limiting transistors (M6 and M8). V DD M10 M6 M8 M12 M2 M4 M4 M2 V in + M1 V o - V o + M3 M3 M1 V in - M9 M5 M7 M11 V CTRL V BIAS Delay Stage Fig. 4-28: Circuit-level schematic of each stage in the VCO. A plot of the oscillation frequency and power consumption vs. the control voltage V CTRL is shown in Fig It can be seen that the total tuning range of the oscillator is from 500 khz 1.4 MHz, while the usable region with a fairly linear gain is from 700 khz 1.2 MHz. The gain of the VCO at 1 MHz is 1.6 MHz / V. The power consumption increases with the frequency of oscillation as expected, and it ranges from 50 μw to 80 μw from a 1 V supply with output buffers included. Ph.D. Thesis K. Allidina

120 Fig. 4-29: VCO frequency and power consumption vs. the control voltage. Due to the low data rate of 1 Mbps, there is very little chance of jitter affecting the ability to sample the data waveform at the optimal point. However, excess jitter can cause uncertainty as to when the next input pulse will occur which may place a lower limit on the time the receiver can spend in low power state before turning back on for the next pulse. The simulated RMS cycle-to-cycle jitter (J CC ) of the VCO when oscillating at a frequency of 1 MHz is 134 ps. This is even smaller that the turn-on time of the amplifiers, so the VCO jitter will not be a limiting factor in how aggressive the duty cycling can be CDR Loop Dynamics As discussed earlier, the gain of the VCO at the desired operating frequency of 1 MHz is 1.6 MHz/V, and the charge pump current associated with the phase detector is chosen to be 12 μa. To achieve a fast settling time, the damping ratio should be ~ 2 2, and since the desired loop bandwidth is 50 khz, the equations presented earlier can be used to find the values of the loop filter components R and C 1. Ph.D. Thesis K. Allidina

121 A summary of the chosen loop parameters is given in Table 4-4. The loop filter capacitor C 2 is chosen to be 16 pf, and the loop bandwidth and phase margin reported in the table include this capacitor. Table 4-4: Parameters and Component Values of the CDR Loop. Parameter Value Phase Detector Charge Pump 12 μa VCO Gain at 1 MHz 1.6 MHz/V Loop Filter: C pf Loop Filter: R 16 kω Loop Filter: C 2 16 pf Loop Bandwidth 51.9 khz Phase Margin 59.8 Natural Frequency 34.9 khz Damping Ratio Settling Time Constant 6.51 μs The open loop response of the CDR with and without C 2 is shown in Fig and it can be seen that the extra capacitor has very little effect on the loop parameters Magnitude (db) khz Without C 2 With C Frequency (Hz) Phase (degrees) Without C 2 With C Frequency (Hz) Fig. 4-30: The open loop response of the CDR with and without C 2 in the loop filter. Ph.D. Thesis K. Allidina

122 The settling time constant of the phase detection loop is ~6.51 μs. This means that the settling time for a step input (within 2% of its final value) is ~26 μs. As stated earlier, the current associated with the frequency detector charge pump is chosen to be 4 times smaller than that of the phase detector charge pump. The frequency detector loop has a phase margin of 40, which will still result in a stable system Cycled Biasing of the RF Front-End As stated earlier, the CDR is also responsible for cycling the operation of the front-end. A synchronized control signal to perform this function can be derived from the inverse quadrature clock signal from the VCO. This signal will lag the rising edge of the clock (and thus the data) by 90. This signal could be used directly to provide 50% dutycycling of the front-end, but a modified signal is desired to provide more aggressive dutycycling. Fig shows how the signal to cycle the operation of the RF front end is generated. The inverse quadrature clock is first passed through a current starved buffer (I1) which delays the signal. A variable width pulse is then obtained using the current starved inverter I2 and the AND gate I3. This pulse is then sent to a series of analog multiplexors to control the biasing of the LNA, gain stages, and comparator. RF Front End Amplifier Biasing Analog Multiplexors Cycle Control Signal Clock and Data Recover Circuit I3 X2 X1 I2 I1 Inverse Quadrature Clock Bias Voltages Width Control Delay Control Fig. 4-31: Schematic of the cycled-bias signal generation circuitry. Waveforms that illustrate the operation of the cycled bias generation circuitry are shown in Fig The cycled bias pulse encompasses the rising edge of the clock as desired, and is skewed to give the amplifiers enough time to turn on before a pulse is expected. Ph.D. Thesis K. Allidina

123 Fig. 4-32: Waveforms showing the operation of the cycled bias generation circuitry. In this implementation, the ability to duty-cycle the RF front end is enabled manually to facilitate testing. This feature can be automatically controlled by adding lock-detect circuitry to determine when the CDR system has completed the synchronization process Clock and Data Recovery System Summary The preceding sections have described the clock and data recovery system that is responsible for synchronizing the receiver to the transmitted signal. This system also provides a digital output of the received data signal, a clock to sample it at the optimal point, and a control signal to cycle the RF front-end such that it is only on when a pulse is expected. It has been designed for a nominal data rate of 1 Mbps with a settling time constant of 6.5 μs. The total current consumption of the CDR system including all biasing branches and buffers is 140 μa. 4.4 Ultra-Wideband Transmitter Design Now that the details of the UWB receiver have been presented, the transmitter that generates the UWB pulses will be discussed. One of the advantages of UWB communications is the ability to design simple, energy efficient digital transmitters. The transmitter designed in this work is shown in Fig Ph.D. Thesis K. Allidina

124 Data in I1 I2 I3 I4 RF out V delay V filter Fig. 4-33: Schematic of the UWB transmitter. It uses a current starved inverter (I1) and an AND gate (I2) to create a short pulse from the rising edge of the data input. This pulse is then passed through a cascade of three current starved inverters (I3), which effectively forms a 3 rd order low-pass filter to attenuate high frequency components such that the signal meets the spectral requirements for UWB transmissions. A large inverter (I4) is used to drive the 50 Ω load of an antenna (or measurement equipment). The transmitting antenna is modeled as a differentiator [11], and an example of the transmitted pulse in the time domain and its corresponding power spectral density for a 1 MHz pulse repetition rate is shown in Fig Tuning the pulse width can be accomplished by varying the delay through I1, and the bandwidth of the pulse can be tuned by varying the speed at which the current starved inverters in I3 charge and discharge the capacitive input of I4. These pulse width and bandwidth adjustments are made by varying the tuning voltages V delay and V filter, respectively FCC Mask Voltage (V) Power Spectral Density (dbm/mhz) MHz 10dB ns Time (ns) (a) Frequency (GHz) (b) Fig. 4-34: Waveforms for the a) output pulse in the time domain and b) corresponding power spectral density for a 1 MHz pulse repetition rate. Ph.D. Thesis K. Allidina

125 4.5 Measurement Results The transceiver was designed and fabricated in an ST Microelectronics 90 nm CMOS process, and the chip micrograph is shown in Fig. 4-35a. As the top level metal fill covers up the chip features, the layout is shown in Fig. 4-35b. Fig. 4-35: a) Chip micrograph (covered by metal fill) and b) the layout showing chip features. The loop filter was not integrated on-chip to allow for more flexible testing. However, the component sizes used in this design would occupy an area of 0.21 mm 2 which means complete integration in the 0.94 mm 2 chip area is easily possible once the test structure shown in Fig. 4-35b is removed Transmitter Measurements The output pulse of the UWB transmitter was passed through a decoupling capacitor and captured using a Tektronix TDS8000 oscilloscope with a 10 GHz bandwidth. The measured pulse in the time domain and corresponding power spectral density for a 1 MHz pulse repetition rate for two different settings for the transmitter tuning voltages Ph.D. Thesis K. Allidina

126 are shown in Fig Fig. 4-36a shows a pulse with a 3 ns width, and from the power spectral density shown in Fig. 4-36b we can see that this pulse meets the FCC spectral requirements. It is also interesting to see what happens by tuning the transmitter control voltage to reduce the amount of filtering introduced by the current starved inverters. This yields the signal in Fig. 4-36c, which has higher amplitude and a short pulse width of 1.8 ns. The corresponding power spectral density in Fig. 4-36d shows that the bandwidth of this pulse is too wide to meet the FCC spectral requirements. Amplitude (V) ns Time (ns) 0.5 (a) Power Spectral Density (dbm / MHz) MHz dB FCC Mask Frequency (GHz) (b) Amplitude (V) ns Power Spectral Density (dbm / MHz) GHz 10dB FCC Mask Time (ns) (c) Frequency (GHz) (d) Fig. 4-36: Measured pulses from the transmitter in the time domain (a, c) and their corresponding power spectral densities for a 1 MHz pulse repetition rate (b, d). Ph.D. Thesis K. Allidina

127 To further verify that the pulse in Fig. 4-36a meets the FCC spectral requirements, the power spectral density of a pulse train with a 1 MHz repetition rate was measured using an Agilent E4440A spectrum analyzer. The measured spectrum is shown in Fig. 4-37, and this matches the spectrum obtained by taking the FFT of the time domain pulse MHz Power Spectral Density (dbm / MHz) dB FCC Mask Frequency (GHz) Fig. 4-37: Measured spectrum of a pulse train with a 1 MHz repetition rate from the UWB transmitter. Ideally, the transmitted signal would occupy the entire 960 MHz bandwidth, and then drop sharply to meet the required mask shape. As discussed earlier, this type of brick wall response is not attainable in practical transmitters. Since the bandwidth of the pulse generated by this transmitter is 530 MHz, the spectral efficiency with regards to the FCC mask is 59%. A comparison of recently published transmitters in the MHz UWB band is shown in Table 4-5. Note that the transmitters in [39, 70] assumed that the maximum PSD is dbm/mhz as in the GHz band, while the limit is actually dbm/mhz. The energy associated with these pulses has been scaled down accordingly to provide a fair comparison. Ph.D. Thesis K. Allidina

128 While the output pulse in [40] does have a wider bandwidth, the maximum PSD in the output spectrum is -65 dbm. This trade-off is necessary to meet the emission requirement in the GPS band, and leads to lower energy in the output pulses. The energy contained in each pulse for this transmitter is 2.27 pj, and the power consumed by the transmitter for a 1 MHz pulse repetition rate is 115 μw. This gives an efficiency of ~2%. While other transmitters have higher efficiencies, the transmitter designed here produces the highest energy per pulse while meeting FCC requirements. This allows for a longer communications distance, which may be more important than the transmitter efficiency in some applications. It should also be noted that the average power consumption in this work can be reduced by duty-cycling the bias circuitry, which would increase the efficiency of the transmitter. Table 4-5: Comparison of IR-UWB transmitter with recent works. Measured Transmitter [70] [40] [39] This Work Results (2008) (2012) (2006) Technology 90nm 0.18μm 0.15μm FD- 90nm CMOS CMOS CMOS SOI CMOS Centre Frequency 300 MHz 250 MHz 400 MHz 250 MHz 10dB Bandwidth 530 MHz 400 MHz 750 MHz 400 MHz Peak PSD (dbm / MHz) Pulse Energy 2.27pJ 0.022pJ* 0.59pJ 1.04pJ* Power Consumption 115μW 220μW 1.93μW 1μW (at 1 Mbps) (at 100Mbps) (at 300kbps) (at 125kbps) Transmitter Efficiency 2% 1% 9.2% 4.2% FCC Compliant? Yes No Yes No *Assumed that the PSD limit in the MHz band is dbm/mhz, as in the GHz band. The pulse energy has been adjusted to reflect the maximum PSD of dbm/mhz for a fair comparison Receiver Measurements The receiver was tested using the already characterized UWB transmitter. For all of these tests, the transmitter was set to generate pulses that meet the FCC spectral mask. Fig shows measured waveforms from the system when the transmitter is connected to the receiver through a 33 db attenuator. The description of the waveforms is given in Table 4-6. Ph.D. Thesis K. Allidina

129 Data In 500 mv per Division Comparator Out Clock Front-End Enable Quad Clock Data Out Time (µs) Fig. 4-38: Measurement results of the transmitter connected to the receiver through a 33 db attenuator. Table 4-6: Description of the waveforms in Fig Signal Description Data In The data input of the transmitter. Comparator Out The output of the comparator in the RF front-end. Clock The in-phase VCO output that is used to synchronize the receiver to the transmitter. Front-End Enable The signal used to duty-cycling the RF front-end. Quad Clock The quadrature clock output from the VCO, which is used to sample the output data. Data Out The received data output from the phase detector. From these waveforms, we can make the following observations that show the receiver is operating as designed: The receiver is properly detecting the incoming UWB pulses as can be seen by the comparator output. This output has a width of ~20 ns, and as mentioned earlier, this is to ensure the pulse is detected by the PFD and also prevents multipath echoes from triggering multiple pulses. Ph.D. Thesis K. Allidina

130 It can be seen that the rising edge of the clock is indeed synchronized to the comparator output which shows that the CDR circuitry is functioning properly. The phase detector is providing the correct output data, and the rising edge of the VCO s quadrature clock is in the correct location for optimal sampling of the data. The front-end enable signal rises prior to the clock edge to allow for the turn-on time of the RF front-end. Fig shows synchronization times for a 1 Mbps data stream composed of all 1 s for various initial values of the VCO control voltage. 50 mv / Div. Initial Control Voltage Synch. Control Voltage Time (µs) Fig. 4-39: Measured control voltage synchronization results for various initial control voltages. As expected, setting the initial VCO frequency close to that of the anticipated data rate reduces the synchronization time. By setting the initial VCO frequency close to that of the anticipated data rate (which would be fixed in advance), the number of pulse periods needed for pulse-level synchronization is ~25. This is because the CDR loop does not have to synchronize the VCO to the frequency of the received signal, and can immediately start synchronizing the phase. The receiver also synchronizes faster when the VCO is initially operating at a frequency higher than that of the data stream, which is likely due to mismatches in the charge pumps. The ability of the CDR to tolerate runs of 0 s was measured by purposefully introducing consecutive 0 s and measuring the pk-pk clock jitter. Fig shows the results of this test. Ph.D. Thesis K. Allidina

131 Pk-Pk Jitter (ns) Number of Consecutive 0's Fig. 4-40: Measured pk-pk clock jitter vs. the number of consecutive 0 s. This defines the worst-case uncertainty in when the next UWB pulse will be, and thus the level of duty cycling that can be achieved. Even with runs of 14 consecutive 0 s, the on period of the receiver can be less than 2.5% at 1 Mbps. (Note: long runs of consecutive 0 s can be avoided by proper coding of the data to be transmitted.) The receiver sensitivity was measured by using an FPGA as a bit error rate tester (BERT). An example of this measurement setup is shown in Fig FPGA (BER Tester) Attenuators Transmitter Receiver Fig. 4-41: Picture of the BER measurement setup. A 23 bit pseudo random bit sequence was transmitted and the errors in the received bitsream were evaluated at different levels of attenuation. As in other works, correct receiver operation is defined as having a BER of less than Fig shows a plot of the BER vs. the received signal power. The receiver sensitivity of dbm exceeds the sensitivity of dbm required for a 5 m link as calculated earlier in the link budget. It should also be noted that the sensitivity in this implementation can be improved by Ph.D. Thesis K. Allidina

132 adding additional gain stages after the LNA, at the cost of higher power consumption. Specifically, each additional gain stage would increase the sensitivity by ~11 db (until the noise floor is reached) at a cost of 230 μw (34 μw during 15% cycled operation) BER Received Signal Power (dbm) Fig. 4-42: Plot of the BER vs. the received signal power. The system can accommodate data rates from 700 kbps to 1.2 Mbps without modifications to the loop bandwidth. Table 4-7 provides a summary of the receiver s performance, along with comparisons to similar recently published works. The receiver sensitivity obtained here is comparable to the receivers in [73, 79], while the receivers in [88, 90] achieve better sensitivity at the cost of higher front-end power consumption. Ph.D. Thesis K. Allidina

133 Table 4-7: Comparison of this IR-UWB receiver with recent works. This Work [79] (2010) [90] (2010) [88] (2009) [73] (2011) Technology 90nm CMOS 0.13μm CMOS 90nm CMOS 0.13μm CMOS 90nm CMOS Receiver Type Peak Detector Quad. Analog Correlator Energy Detector Mostly Digital Peak Detector Supply 1 V 1.2 V 1 V 1.2 V 0.9 V 1 V Die Size 0.94mm mm mm 2 8 mm mm 2 Data Rate 700 kbps to 305 kbps to 1.2 Mbps 39 Mbps Up to 16 Mbps Up to 31 Mbps 1 Mbps Modulation OOK BPSK OOK, PPM OOK, PPM S-OOK Operating Frequency 80 MHz 1.1 GHz* MHz GHz 4 5 GHz GHz Maximum Front-End Gain 40 db 50 db 45 db 80 db 38 db Front-End Noise Figure <9 db* 23.5 db <9 db Not Reported Not Reported Receiver Sensitivity dbm -64 dbm -76 dbm kbps Mbps Receiver Sensitivity Normalized to 1 Mbps dbm dbm -88 dbm dbm -66 dbm Pulse Synchronization Time 990 pulse 64 pulse 250 pulse < 25 pulse periods (at 1 Mbps) periods*** periods**** periods**** Not Described Front-End Power (mw) Digital / Backend Power (mw) ***** Energy per Bit (nj / bit) 1 Mbps 1.3 Mbps** 16 Mbps 31 Mbps 1 Mbps Average Power at Highest Mbps 2.5 mw 22.4 mw Efficiency (Duty Cycle of Mbps * Simulated result (output unavailable on-chip). ** Using the reported PN code of 15 pulses / bit in LPP mode. *** Using the reported preamble length used in the receiver sensitivity measurement. **** Details were not given. Number of pulses is based on the duration of the detection window. ***** Does not include hardware for duty-cycling control and synchronization. These features were implemented off-chip Mbps Mbps (Duty Cycle of 60%) Ph.D. Thesis K. Allidina

134 Comparing the power consumption in the digital back-ends shows the benefits of the analog CDR-based synchronization scheme proposed here, which is significantly lower than the correlation, energy detection, and mostly digital receivers. The backend power is comparable to the work in [73], but the hardware for duty-cycling and synchronization was not included in that work. The chip area is also significantly smaller than the other fully implemented receivers, which require large digital blocks to handle the synchronization and signal processing. The average power consumption of the receiver is 292 μw at a data rate of 1 Mbps, which is the lowest of the receivers presented here and is well suited for power-sensitive wireless applications. As mentioned earlier, this receiver can achieve pulse-level synchronization in 25 pulse periods, which is the quickest out of the receivers shown here. Additionally, this receiver only requires a clock frequency equal to the data rate, and since the CDR circuitry provides real-time correction of clock drift between the transmitter and receiver, an external high precision crystal reference is not necessary. The receiver s performance in the presence of in-band interference was tested by injecting a tone at 300 MHz, which is at the center of the transmitted pulse spectrum. A BER of less than 10-3 was observed for signal to interference (SIR) ratios of -22 db at a data rate of 1 Mbps. The energy detector receiver in [89] reports a BER of less than 10-3 for an SIR ratio of -15 db for an in-band interferer at a data rate of 100 kbps with a 30 ns long detection window. This translates to a required SIR of -5dB when normalizing to a data rate of 1 Mbps, which means the peak detection receiver presented here performs significantly better in the presence of interference. This is due to the relatively long detection window used in [89]. The quadrature analog correlation receiver in [79] reports a required SIR of -16 to -23 db (depending on the frequency of the interference) for a packet error rate (PER) of 10% for in-band interferers at a data rate of 1.3 Mbps. Even though the receiver is based on correlation, its performance is roughly equivalent to the peak detection receiver presented here. This is quite interesting since a correlation receiver should theoretically provide interference suppression and perform better than peak detection. The reason for this discrepancy is that a QAC receiver does not use an exact UWB template pulse for correlation, but rather approximates the template with a sine wave. Since narrowband interference is also sinusoidal, interferers in the middle of Ph.D. Thesis K. Allidina

135 the pulse spectrum (at the frequency of the approximated template pulse) will also have a high correlation, reducing the receiver s performance in the presence of interference. As an experiment, wireless communications was also attempted by using narrowband 300 MHz antennas. The S11 of the antenna was measured using an Agilent E5061B VNA, and the results are shown in Fig While the narrow bandwidth severely reduces the energy of the transmitted and received signals, communications over a very short range should still be possible. 0-5 S11 (db) f L = 286 MHz f H = 299 MHz -20 f = 294 MHz C BW = 13 MHz Frequency (MHz) Fig. 4-43: Measured S11 of the 300 MHz narrowband antenna. Successful communication was achieved at a distance of 45 cm, as shown in Fig The fact that the TX data and the RX clock are both synchronized on the oscilloscope show that the receiver has locked onto the transmitted signal. Fig shows what happens when the transmitter is moved away from the receiver. The waveforms on the oscilloscope screen are no longer synchronized, showing the transmitted signal cannot be detected by the receiver. Ph.D. Thesis K. Allidina

136 TX Data RX Clock 45cm Transmitter Receiver Fig. 4-44: Measurement setup showing successful wireless communications with narrowband antennas. Ph.D. Thesis K. Allidina

137 TX Data RX Clock Transmitter Receiver Fig. 4-45: Measurement setup showing unsuccessful wireless communications with narrowband antennas. Ph.D. Thesis K. Allidina

138 To simulate the shape of the pulse at the receiver using these narrowband antennas, a digital filter was applied to measure the approximate the pulse shape. Fig shows the passband of the filter is superimposed on the S11 curve of the antennas dB Bandwidth = 42 MHz -10 db S 11 of Antenna Corresponding Pulse Filter Frequency (MHz) Fig. 4-46: Passband of the digital filter superimposed on the S11 of the antenna. To account for both the transmit and received antenna, the pulse was passed through the digital filter twice and attenuated by 15 db, which is the path loss for a 300 MHz signal at a distance of 45 cm. The resulting waveform is shown in Fig. 4-47, and the peak amplitude is ~4.3 mv, which is within the detection range of the receiver. The pulse has also spread out significantly due to the narrowband nature of the antenna, and this explains an interesting observation during the measurements when the transmitter is moved closer to the receiver, errors in communication start to appear! This counter-intuitive behaviour is due to the length of the pulse. As the transmitter approaches the receiver, the amplitude of the received pulse increases enough that the signal is still above the detection threshold after the ~20 ns safety margin to prevent the reception of multipath echoes. In this case, the receiver erroneously detects another pulse and cannot synchronize to the data. This situation can be avoided by reducing the gain of the RF front-end. Of course, the preferred solution is to simply use an antenna with a wider bandwidth! Ph.D. Thesis K. Allidina

139 Amplitude (mv) 4.6 Summary Time (ns) (a) 5 Amplitude (mv) Time (ns) (b) Fig. 4-47: Plots of the amplitude vs. time for a) the output of the transmitter and b) the pulse shape at the receiver. This chapter presented a low power, low complexity UWB transceiver. By transferring the pulse synchronization to the analog domain in the form of a clock and data recovery loop, a reduction in the size and power consumption of the digital circuitry is obtained. Using this technique, the implemented receiver has a nominal data rate of 1 Mbps using on-off keying, a receiver efficiency of 292 pj/pulse, and a synchronization time of 25 pulse periods. The receiver has a sensitivity of dbm and showed increased tolerance to in-band interferers as compared to other works. A transmitter capable of using 59% of the allotted FCC spectral mask was also designed with an efficiency of 115 pj/pulse at a data rate of 1 Mbps. The transmitter meets the FCC spectral mask including the GPS stopband, and the energy contained in each pulse is 2.27 pj. The entire transceiver consumes an average power of 407 μw and occupies a chip area of 0.94 mm 2. This level of power consumption and efficiency is well suited to wireless sensor network nodes that require increased battery lifetime or that rely on energy harvesting techniques for power. Ph.D. Thesis K. Allidina

140 Chapter 5 - A Low Power Sensor Interface with Temperature Compensation for Frequency Domain Sensors A Low Power Sensor Interface with Temperature Compensation for Frequency Domain Sensors 5.1 Introduction The largest power consumer in each sensor node is the wireless transceiver, which has been the focus of the previous chapters. However, energy efficient circuits are also needed to interface with the sensors and convert their output into a digital signal for wireless transmission. Wireless sensor networks present a need for compact, low power, and low cost sensing solutions that can function over a wide range of environmental conditions. Due to their small form factor and configurability through custom fabrication processes, capacitive and resonant sensors based on micro-electromechanical systems (MEMS) technology are an attractive option for these applications. And, as with integrated circuit technology, batch fabrication of these sensors can lead to a low cost solution. In order to realize the full potential of these MEMS devices in a full sensing system, a robust electronic interface is needed. This chapter describes the system architecture for an electronic interface targeted towards integrated capacitive humidity sensors. The capacitance of such sensors changes with humidity, and the interface converts this capacitance to a frequency whose period can be measured. This approach is chosen for the advantages inherent in frequency domain signals as compared to amplitude-based signals, including less sensitivity to noise, a large dynamic range that is not limited by the voltage supplies, and the ability to implement a simple time-to-digital conversion using a counter [126]. As is the case with integrated electronics, the behavior of environmental sensors is dependent on temperature. Even if the parameter of interest, be it humidity, pressure, Ph.D. Thesis K. Allidina

141 gas, etc. is held constant, changes in the ambient temperature will cause changes in the sensor output. The proposed architecture is capable of inherent temperature compensation of both the environmental sensor, and the electronics of the sensor interface itself. This not only increases the accuracy of the sensing system over temperature, but can also reduce the time to calibrate the sensor, since measurements at different temperatures can be avoided. The proposed architecture is targeted towards low power, low complexity implementations such as those required in wireless sensor network nodes. While this chapter focuses on applications involving capacitive sensors, it should be noted that this architecture can be applied to frequency domain sensors in general. This chapter will first provide a brief background on methods of capacitance to digital conversion, and methods of temperature compensation. The humidity sensor used here will be described next, followed by an analysis of the proposed architecture. System level simulation results that illustrate the performance of the architecture using measured sensor characteristics will then be presented, followed by a summary of its advantages. 5.2 Background of Capacitive Sensor Interfaces Capacitive sensors exist for numerous applications, including inertial sensors [127], pressure sensors [128, 129], chemical sensors [130], and relative humidity (RH) sensors [131, 132]. The purpose of the sensor interface is to convert the changes in capacitance due to the environmental phenomenon of interest into a digital signal for processing or analysis. Since environmental conditions generally have a slow time constant, it is desirable to perform a measurement quickly and then put the circuitry into a low power sleep mode until another measurement is needed. A typical measurement rate reported for the current consumption of a sensor is 1 measurement / second. [ ]. This can be done in a few different ways, with the most common being to use a switchedcapacitor front-end in a delta-sigma (ΔΣ) modulator [ ] or to use the capacitive sensor to modulate either the pulse duration [140] or frequency [128, 141, 142] of a signal and convert this to the digital domain using a counter. Ph.D. Thesis K. Allidina

142 Delta-sigma modulators offer a high resolution (> 16 bits) which is required in some applications such as atmospheric pressure sensing for indoor navigation [143] or displacement sensors for precision systems such as wafer steppers [139]. However, the required oversampling ratio can lead to relatively high power consumption due to the charging and discharging of large capacitors (5 to 20 pf) [144], and time needed to apply the decimation filter can lead to a relatively high measurement times, which means the circuitry be active for a greater portion of the measurement cycle [145]. For example, the systems reported in [134, 137] require a measurement time of 2-3 ms for a low resolution 8 bit conversion. During this time the measurement and all supporting circuitry (regulators, biasing circuits, etc.) must be active. The required digital filter can also lead to relatively large chip areas of 2.6 mm 2 [139] or more [137]. These factors make ΔΣ modulators less attractive for low power systems that do not require a high resolution. In contrast, quasi digital approaches that convert that capacitance to two-level signals where information is encoded in either the frequency or pulse duration have a less complex front-end, and can produce a digital output by simply using a counter [145]. While careful design can lead to a resolution of up to 15 bits [141], the low implementation complexity also makes them attractive for low power systems that do not need high resolution [128]. A perfect example of such a system is a relative humidity sensor. The parameter of relative humidity has a fixed range from 0 to 100%, and the achievable accuracy of a low cost polymer-based smart sensor is typically in the range of 1.5% to 2% RH [134, 135]. Even a relative humidity sensor that costs over $200 USD can only achieve an accuracy of ~0.8% RH [146, 147]. This leads to a necessary resolution of only 6-7 bits over the entire RH range. This is easily achievable by low complexity systems, and these will be the focus of the rest of this chapter. (Note that the achievable accuracy of relative humidity measurements is limited by the fact that the metric of relative humidity is strongly dependent on temperature. At a relative humidity of 50% RH, even a temperature fluctuation of less than 0.4 C will result in a 1% change in RH. The temperature dependence becomes even more pronounced at higher humidity levels.) Ph.D. Thesis K. Allidina

143 One of the most important features of the electronic interface is the ability to compensate for changes in the ambient temperature. These temperature changes will invariably change the capacitance of the sensor and be misinterpreted as a change in humidity. Fig. 5-1 shows three methods of compensating for temperature changes in capacitive sensors. The first method uses a sensor to measure the ambient temperature, and uses this signal to correct the output of the capacitive sensor based on a digital look-up table (LUT) or fitting equation [138, 148, 149]. In order to realize a high resolution sensor using this method, a precise and accurate temperature sensor is required. The method also requires precise measurements of the sensor itself to obtain the coefficients or values needed in the LUT or equation, and a temperature insensitive clock to operate the timeto-digital converter. The second method uses a heater integrated onto the sensor to keep it at a constant temperature that is equal to the maximum operating temperature or higher [150]. This ensures that any ambient temperature change will have minimal effect on the sensor s local temperature, and hence on the sensor output. However, driving the heater requires a relatively high current, making this method unsuitable for low power applications. This method also requires a temperature control system to regulate the heater and a temperature insensitive clock to operate the time-to-digital converter. The third method uses a reference sensor placed in close proximity to the desired sensor. Both devices will experience the same temperature fluctuations, but the reference sensor is fabricated in such a way that it does not respond to variations in the desired parameter (e.g., humidity, pressure, etc.) [132, ]. The final temperature compensated output is the difference between the actual sensor and the reference, and this can be converted to a digital signal via a counter, as in [ ]. However, as with the previous architectures, a temperature insensitive clock is required for the time-to-digital conversion. Ph.D. Thesis K. Allidina

144 Capacitive Sensor and Oscillator Temperature Sensor Temp. Insensitive Clock Time-to-Digital Converter Analog-to-Digital Converter (a) DSP with Look Up Table Output Heater Control Capacitive Sensor and Oscillator Integrated Heater Temp. Insensitive Clock (b) Time-to-Digital Converter Output Capacitive Sensor and Oscillator Reference Capacitor and Oscillator Frequency Subtraction (c) Temp. Insensitive Clock Time-to-Digital Converter Output Fig. 5-1: Examples of temperature compensated sensor architectures based on a) a temperature sensor and a look-up table, b) a heater integrated with the sensor, and c) compensation using a reference sensor. The architecture proposed in this chapter is shown in Fig It produces a temperature compensated digital output without the need for a high-resolution temperature sensor, an integrated heater, or a temperature compensated oscillator. In this system, the temperature compensation is inherent in the time-to-digital conversion by using the oscillator formed by the reference capacitor as the clock. This allows for a potential reduction in the cost, size, and complexity of the system. This temperature compensation will also apply to performance variations due to temperature of the analog circuits that compose the sensor and reference oscillator, as long as they are close together on-chip and proper layout techniques are used. Reference Capacitor and Oscillator Capacitive Sensor and Oscillator Clock Signal Divide by N Time-to-Digital Converter Output Fig. 5-2: Proposed temperature compensated sensor architecture. Ph.D. Thesis K. Allidina

145 An analysis of the temperature compensation will be provided after a brief description of the MEMS capacitive humidity sensor used here. 5.3 The MEMS Capacitive Humidity Sensor The humidity sensor design is a capacitive type sensor which consists of a moisture sensitive dielectric sandwiched between two metal electrodes, forming a parallel plate capacitor whose capacitance changes with the amount of moisture present in the dielectric. Capacitive-type sensing was chosen since it offers better mechanical resilience, simpler conditioning circuitry, lower power consumption, better linearity, and wider humidity measuring range [155, 156] than other types of sensors including resistive, thermal conductivity, and gravimetric type sensors. The type of dielectric used is critical, since its properties influence the parameters which determine the overall performance of the sensor (sensitivity, response time, linearity, etc.). Several possibilities exist, including ceramics, porous silicon, carbon nanotubes and polymers. A polymer known as polyimide was chosen here due to its good linearity, low hysteresis, high sensitivity, resistance to chemicals, and IC compatibility [ ]. Polyimide is non-ionic and highly polar, which makes it hydrophobic, but somewhat hygroscopic. This is essential to prevent drops in performance or dissolving of the polymer in high humidity or dewforming atmospheres. The hygroscopicity helps in absorbing moisture which occupies the spaces between the polyimide molecules and hence changes its dielectric constant. Also, polyimide is very easy to prepare and, since it is IC compatible, the sensor can be integrated on the same chip as its interface circuitry allowing a fully integrated solution. The capacitive humidity sensor was fabricated in-house using a CMOS-compatible MEMS process. The basic structure of the sensor is shown in Fig The device on the left is the actual sensor and the device on the right is a replica covered with oxide to create the reference capacitance shown in Fig As can be seen, the sensor simply consists of a polyimide layer fixed between two metal layers. Ph.D. Thesis K. Allidina

146 Fig. 5-3: Capacitive humidity sensor alongside the reference capacitor used in the temperature compensation scheme. A polyimide that is very sensitive to moisture and has a high moisture diffusion coefficient should be chosen in order to enhance the sensitivity and response time of the sensor. Once the dielectric material is chosen, the sensor performance can only be improved by sensor geometry design. The design goal is to maximize the area of contact between the polyimide and vapor and minimize the pathway of vapor absorption so as to maximize sensitivity and minimize the response time. Admittance openings (squares in this case) were introduced into the top electrode (as shown in Fig. 5-3) in order to increase the exposure of polyimide to surrounding moisture. To reduce the low sensitivity capacitance area created by these openings, the bottom electrode was patterned in the same fashion and aligned to the top electrode. This increases the ΔC/C ratio, hence increasing the sensitivity. The sensor geometry was optimized to minimize the largest distance between the polyimide and the surface of the capacitor, thus reducing the sensor response time. While the dielectric constant of the polyimide changes with humidity, it is also affected by temperature. This means that the output capacitance will also change with temperature, and this effect needs to be compensated for in order to get an output that only changes with humidity. In order to achieve this compensation, a reference structure was fabricated next to the sensing structure as shown in Fig This reference device is covered with oxide to prevent access to moisture, and hence the capacitance of this reference device only varies with temperature. This feature is exploited to realize the temperature compensated architecture described in the next section. Ph.D. Thesis K. Allidina