ULTRA-WIDEBAND (UWB) is defined as a signal that occupies

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL A CMOS Ultra-Wideband Impulse Radio Transceiver for 1-Mb/s Data Communications and 2.5-cm Range Finding Takahide Terada, Shingo Yoshizumi, Muhammad Muqsith, Yukitoshi Sanada, Member, IEEE, and Tadahiro Kuroda, Fellow, IEEE Abstract A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of 2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mw, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mw. The range for data communication is 1 m with BER of For ranging applications, the transmitter can reduce the power to 0.7 W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 V/m, and thus the UWB system can be operated even under the current Japan radio regulations. Index Terms CMOS, impulse radio, low power, range finder, RF, transceiver, ultra-wideband. Fig. 1. Proposed UWB-IR transceiver architecture for (a) the transmitter and (b) the receiver. I. INTRODUCTION ULTRA-WIDEBAND (UWB) is defined as a signal that occupies a bandwidth wider than 500 MHz or a fractional bandwidth larger than 20% [1]. The fractional bandwidth is the ratio of the signal bandwidth at 10 db to the center frequency. UWB technology is expected to improve the performance and reduce the power consumption and cost of short-range wireless communications in applications such as remote controllers, RF-IDs, and sensor networks [2], [3]. There are several architectures that satisfy UWB definitions, and two standards have been discussed in IEEE Task Group 3a and Task Group 4a. Task Group 3a has discussed the use of multiband-ofdm and DS-SS for the high-data-rate PHY. Manuscript received August 19, 2005; revised December 22, This work was supported by the Semiconductor Technology Academic Research Center (STARC). T. Terada was with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan. He is now with the Central Research Laboratory, Wireless Systems Research Department, Hitachi, Ltd., Tokyo , Japan ( t-terada@crl.hitachi.co.jp). S. Yoshizumi was with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa , Japan. He is now with Sony, Tokyo, Japan. M. Muqsith, Y. Sanada, and T. Kuroda are with the Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa , Japan. Digital Object Identifier /JSSC Task Group 4a has chosen impulse UWB radio (UWB-IR) as a good candidate for low-power radio in applications like sensor networks We evaluated several UWB systems and selected UWB-IR for the following reasons. First, the UWB-IR transceiver can be designed at a low cost and with low power consumption. It will be low in complexity and can be implemented using CMOS technology with a few or no off-chip passive components [2]. Second, UWB-IR can provide high accuracy in ranging due to the narrow pulsewidth of a few nanoseconds. These features make UWB-IR the best solution for RF-IDs and sensor networks. Many papers have discussed theoretical or simulated systems, but few have reported experimental results for actual ICs [4]. In this paper, a CMOS UWB-IR transceiver design and experimental results are presented. Fig. 1 shows the proposed transceiver architecture. An all-digital transmitter and a clocked correlator reduce both layout area and power consumption. The layout area is as small as mm. The clocked correlator saves the area and power that would have been required for an over-1-ghz analog-to-digital converter (ADC) designed with conventional receiver architecture [4]. Japanese radio regulations allow extremely low-power radio stations to use weak radio waves without a license. Electric field intensities permitted at 3 m are 500 V/m at frequencies up to 322 MHz and 35 V/m from 322 MHz to 10 GHz as shown in /$ IEEE

2 892 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 Fig. 3. All-digital transmitter. the delay controller. These are LNA bias switching, template pulse generation, mixer/integrator reset, and flip-flop operation. Fig. 2. Radio regulations in Japan. Fig. 2. The transceiver is designed to comply with these regulations. The rest of this paper is organized as follows. Section II introduces the UWB-IR transceiver architecture. Section III describes the all-digital transmitter. Section IV describes the receiver circuit design for low power consumption, covering LNA bias switching and the clocked correlator and the synchronization and ranging scheme. Section V presents the experimental results. Section VI summarizes the paper. II. ARCHITECTURE OVERVIEW Fig. 1 shows the transceiver architecture. We selected UWB-IR modulated with on off keying (OOK) for easy implementation and low power consumption. A conventional transmitter design consists of a pulse generator, modulator, analog amplifier, and antenna [5], [6]. The proposed transmitter is an all- digital design, and a CMOS output buffer drives the antenna directly, which eliminates the need for an analog power amplifier [7]. The receiver consists of an LNA and a clocked correlator. A conventional LNA and a conventional correlator consume large DC current. However, in UWB-IR, signals are not continuous and the duty cycle is extremely small. This means that the LNA and correlator can be operated intermittently to reduce power consumption for UWB-IR system. The clocked correlator consists of a mixer/integrator, comparator, template pulse generator, and delay controller. It requires a much smaller layout area and consumes much less power than the conventional design, in which a high-speed ADC is required for digital signal processing [4]. The mixer and the integrator are combined, and consume current only when received signals and template pulses are synchronized. The template pulse generator is implemented in a simple digital circuit [8]. The template pulse is digital impulse and detects the energy of the received signal. The comparator is a standard flip-flop. The voltage amplitude of the mixer/integrator output is enough to distinguish data 1 from data 0 by a flip-flop. The delay controller provides timing not only for synchronization in data communications but also for measurement of relative distance in range finding. Acquisition is detected by output signal of the comparator. All blocks of the receiver are controlled by III. TRANSMITTER CIRCUITS The transmitter is shown in Fig. 3. It is designed using all-digital circuits without an analog power amplifier. A clock generates an impulse of 2-ns width. The pulse trains are modulated by input data with OOK modulation and the differential signal is provided to the antenna by the CMOS buffer. The pulse waveform is modulated by the slew rate and the impulse width, as well as frequency response of the antenna. The slew rate and impulse width are changed over process, supply voltage, and temperature (PVT) variations so that the pulse waveform is also changed, but this change is not large because the frequency response of the antenna is not changed over PVT variations. As the current flows into the transmitting antenna, an electric field is generated in the air. Because the spectrum of the output of the CMOS buffer is much lower than the frequency response of the transmitting antenna, it is possible to assume the transmitting antenna as a short dipole antenna. The output of the CMOS buffer is digital impulse so that the spectrum is proximity of DC. The electric field generated from short where is the distance between antennas, is the antenna length, is the current flowing into the antenna, and is the wave number. The received voltage is calculated as Therefore, the received voltage is the first derivative of the current flowing into the transmitting antenna. Fig. 4 shows simulation results for the all-digital transmitter using the equivalent circuit of a dipole antenna [9]. The current is induced only when the transmitted data is 1. In other words, the CMOS output buffer consumes current once when the pulse is transmitted. Thus, the power consumption of the transmitter is extremely low and can be reduced in proportion to the pulse rate. IV. RECEIVER CIRCUITS A. LNA The LNA is an analog circuit and accounts for most of the power consumption of a receiver. An effective way to reduce the LNA s power consumption is to reduce the current of the (1) (2)

3 TERADA et al.: A CMOS ULTRA-WIDEBAND IMPULSE RADIO TRANSCEIVER FOR 1-MB/S DATA COMMUNICATIONS AND 2.5-CM RANGE FINDING 893 Fig. 4. Simulation results for the all-digital transmitter. Fig. 6. Simulation results for the LNA with bias switching. Fig. 7. Settling time of the LNA with bias switching. Fig. 5. Differential low noise amplifier. LNA. The UWB-IR system sends signal intermittently so that intermittent operation of LNA becomes possible. The differential LNA design is shown in Fig. 5. The LNA is an ordinary common-source cascode amplifier. The LNA requires noise factor not so low, because the transceiver is used for short-range wireless communications. The cascade amplifier is not so bad noise performance and is enough to use for short-range wireless communications. The load impedance is a pmos operating in deep triode region. The input node and output node are connected to the antenna and the mixer with capacitive coupling, respectively. Input matching network is only inductance of bonding wire. Bandwidth, gain, and noise figure (NF) of the LNA are 1 GHz, 16 db, and 5.6 db, respectively. The bias voltage of the cascode transistor and that of the load pmos are switched between supply voltage and ground. The delay controller controls the timing of the bias switching. Fig. 6 is a simulation result for the LNA with bias switching. While the bias is switched off, the LNA does not consume the current and the output node is floated. The current of the LNA is reduced to less than 1% of that of an LNA without bias switching. The output pulse waveform is a little changed from the input pulse waveform in Fig. 6 because the received signal is synchronized with a template signal at a clocked correlator. How the clocked correlator operates is described in Section IV-B. The settling time of the LNA is shown in Fig. 7. Settling takes 2 ns by the time the gain of the LNA is constant. When the received pulsewidth and margin are added to the settling time, the LNA consumes only 7 ns per pulse. In 1-Mb/s data communications, the LNA consumes current in 7-ns period and shuts down during the other 993 ns. The control logic circuit for bias switching is simple and consumes extremely low power. The LNA does not use inductors, whereas conventional LNAs usually do [10] [12]. Inductors in an LNA circuit cause ringing and thus settling time increases. The ringing is especially long when the inductors have a high quality factor. Therefore, an LNA with intermittent operation must have a low quality factor component, such as an inductor placed in series with a resistor. In addition, there is a risk of oscillation when the bias is off. B. Clocked Correlator The mixer and the integrator are combined as shown in Fig. 8(a). The lower half of the circuit is a typical passive mixer, and the correlation signal can be integrated to discharge the parasitic capacitance of the output node depending on the degree of the correlation and the received signal amplitude. is a reset switch. A digital template pulse is fed into an input of the mixer, and the received signal from the LNA is fed into the other input. is biased to ground.

4 894 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 Fig. 9. Simulated waveforms of (a) the clocked correlator and (b) the conventional correlator. Fig. 8. (a) Proposed mixer/integrator. (b) Conventional mixer. and are multiplied at the lower half of the circuit. Output signal of the lower half of the circuit is fed into gate and source of transistors and.if is synchronized with, parasitic capacitance of is discharged through or. After the comparator detects signal at, is switched from ground to supply voltage (also bar is switched from supply voltage to ground) and is reset to supply voltage. Simulated waveforms of the clocked correlator and conventional mixer [Fig. 8(b)] are shown in Fig. 9. A UWB pulse is fed into of the proposed correlator and conventional mixer and of the conventional mixer. A digital impulse is fed into of the proposed correlator. of the proposed correlator is integrated. Even if the UWB pulse is fed into of the proposed correlator, of the proposed correlator is integrated. Since the clocked operation consumes power only when the data is synchronized, power consumption is reduced significantly. It is only 0.1 A at 1 Mb/s, whereas a mixer with DC current typically consumes 0.9 ma in the conventional design. This scheme also simplifies template pulse generation, resulting in power consumption of 0.01 mw. The correlation is less sensitive to the shape of the template pulse, but more sensitive to the timing because the pulsewidth is narrow. Fig. 10. Synchronization and ranging scheme. (a) Delay controller. (b) Range finding. C. Synchronization and Ranging Scheme A sliding scheme (Fig. 10) is used for data synchronization. The controller selects one tap from the delay line, and the output signal of the multiplexer is fed into the template pulse generator. Acquisition can be detected by the signal from the mixer/integrator through the comparator (rxdata). When correlation is not detected, the controller continues to change the selection of the taps until correlation is acquired. For the first acquisition, the tap is selected is by sliding incrementally. When synchronization is out, the controller seeks a tap back and forth around the point where the synchronization got lost. Relative range can be measured by finding the tap selected in the delay line. For instance, assume that a transmitter backs away from a receiver a few centimeters, where the tap at the receiver was the tap synchronized before the motion. Then, after the motion, the arrival time of the received signal is delayed and synchronized with another tap. The number of relative taps synchronized corresponds to the relative distance. Ranging accuracy is set by the propagation delay of the delay line. Typical delay in the design is 160 ps, leading to 2.5-cm error in ranging. A supply voltage change of 10% causes a 10%

5 TERADA et al.: A CMOS ULTRA-WIDEBAND IMPULSE RADIO TRANSCEIVER FOR 1-MB/S DATA COMMUNICATIONS AND 2.5-CM RANGE FINDING 895 Fig. 13. Measured transmitted and received data at 1 Mb/s. Fig. 11. Chip microphotograph. Fig. 14. Measured BER versus distance at 1 Mb/s. 1.8 V; the exception is that of the output buffer at the transmitter, which ranges from 1.8 to 2.5 V. Experiments were carried out using two transceiver chips with 15-cm-long dipole antennas in a typical office environment. The chips were mounted on ceramic packages and assembled on FR4 printed circuit boards. Fig. 12. Measured impulse. (a) Waveform. (b) Spectrum. change in the propagation delay, resulting in error of around 0.25 cm. Delay change due to condition changes (changes in the supply voltage and temperature) and process variations can be suppressed by the circuit techniques widely used in DLLs. Location awareness is available with four transceivers through time difference of arrival (TDOA) measurement. Absolute distances can also be found by measuring impulse propagation time for a round trip between the two transceivers. V. EXPERIMENTAL RESULTS A test chip was fabricated in m CMOS technology. A chip microphotograph is shown in Fig. 11. The layout areas for the transmitter and the receiver are and 0.38 mm, respectively. The supply voltage of the transceiver is basically A. UWB-IR Signals Fig. 12 shows the measured waveforms of transmitted and received signals and the spectrum of received signals. These signals were measured at the input of the transmitting antenna and the output of the receiving antenna. The transmitted signal at the antenna input has 2-ns pulsewidth and 2.5-V amplitude when the supply voltage is 2.5 V at the CMOS output buffer. The CMOS output buffer is designed by using MOSFETs that are for I/O buffering. The received signal is 100 mv peak to peak at 1 m. The tail in the received signal waveform is caused by the multipath and impedance mismatch, and could degrade the performance of the OOK system. If an external input matching network is used, the received signal waveform can be improved to some degree. The center frequency of the signal is about 400 MHz and the bandwidth at 10 db is 250 MHz. The spectrum satisfies the UWB definition because the fractional bandwidth is larger than 20% of the center frequency. The electronic field intensity of received signals for 1-Mb/s data communications is lower than 35 V/m, which is in compliance with the regulation for extremely low-power radio stations. B. Data Communications Measured transmitted and received data at 1 Mb/s are shown in Fig. 13. The bit error rate (BER) was measured, and its dis-

6 896 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 Fig. 15. Measured ranging accuracy. TABLE I MEASURED POWER CONSUMPTION AT 1 MB/S Fig. 16. Measured ranging error versus supply voltage. tance dependence is plotted in Fig. 14. The BER is lower than 10 for distances of up to 95 cm and 10 for distances of up to 100 cm at 2.5-V supply of the transmitter. The data stream was a pseudo-random binary sequence 2 1 pattern. A maximum communication range is proportional to the supply voltage of the transmitter because the voltage amplitude of the transmitted signal is proportional to the supply voltage of the transmitter. The power consumption of the transmitter and receiver is summarized in Table I. Measured power consumptions of the transmitter and the receiver are 0.7 and 4.0 mw, respectively. The power consumption of the receiver is reduced 30% from that of a conventional design because the clocked correlator reduces the power for correlation to 1/24. In addition, the LNA operates intermittently through bias switching, the receiver consumes only 0.3 mw, and the power consumption of the transceiver is just 1 mw at 1 Mb/s. As a result, the proposed transceiver can operate at 1 Mb/s at a distance of 1 m at 1 mw. C. Range Finding Fig. 15 shows the distance dependence of ranging error. The ranging error is within 2.5 cm. The supply voltage dependence of the maximum error is plotted in Fig. 16. The range was measured by finding the tap selected in the delay line. The experiments were carried out ten times and the range was calculated from a most selected tap. The typical delay of the taps in the design was 160 ps, leading to 2.5-cm error in ranging. The range finder is calibrated at each. Error caused by change is negligibly small in the transmitter. In the receiver, the higher the is, the smaller the error becomes. Error of 0.25 cm is caused by a 10% change in, unless a circuit Fig. 17. Measured maximum ranging distance and power consumption. technique is used for suppressing the influence of on the delay line. The maximum ranges where the BER is lower than 10 was measured at each of the receiver, and the results are plotted in Fig. 17 together with the power consumption. The maximum range is proportional to the of the transmitter, and the power consumption is proportional to square of. This can be understood as follows. When transmitted voltage becomes times higher, radiated power becomes times larger. On the other hand, when distance becomes times longer, received power density becomes times smaller. Therefore, the maximum distance for ranging is proportional to the as transmitted voltage. VI. CONCLUSION A CMOS UWB-IR transceiver chip was developed in m CMOS technology. Measured performance is sum-

7 TERADA et al.: A CMOS ULTRA-WIDEBAND IMPULSE RADIO TRANSCEIVER FOR 1-MB/S DATA COMMUNICATIONS AND 2.5-CM RANGE FINDING 897 TABLE II PERFORMANCE SUMMARY [6] Y. Zheng, Y. Tong, J. Yan, Y. Xu, W. G. Yeoh, and F. Lin, A low power noncoherent CMOS UWB transceiver ICs, in Proc. IEEE RFIC Symp. Dig. Papers, Jun. 2005, pp [7] S. Yoshizumi, T. Terada, J. Furukawa, Y. Sanada, and T. Kuroda, All digital transmitter scheme and transceiver design for pulse-based ultra-wideband radio, in Proc. IEEE Conf. UWBST, Nov. 2003, pp [8] T. Terada, S. Yoshizumi, Y. Sanada, and T. Kuroda, Transceiver circuits for pulse-based ultra-wideband, in Proc. ISCAS, May 2004, vol. 4, pp [9] T. G. Tang, Q. M. Tieng, and M. W. Gunn, Equivalent circuit of a dipole antenna using frequency-independent lumped elements, IEEE Trans. Antennas Propagat., vol. 41, no. 1, pp , Jan [10] A. Bevilacqua and A. M. Niknejad, An ultrawideband CMOS lownoise amplifier for GHz wireless receivers, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [11] A. Ismail and A. A. Abidi, A 3 10 GHz low-noise amplifier with wide-band LC-ladder matching network, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp , Dec [12] C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, and S. G. Lee, An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system, IEEE J. Solid-State Circuits, vol. 40, no. 2, pp , Feb marized in Table II. The chip can be used for 1-Mb/s data communication as well as for range finding within an error of 2.5 cm. A digital transmitter and clocked correlator significantly reduce both layout area and power consumption. Chip layout areas of a transmitter and a receiver are and 0.38 mm, respectively. Power consumption for 1-Mb/s data communications is 0.7 mw for the transmitter and 4.0 mw for the receiver. When the LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mw. The BERs are lower than 10 for ranges shorter than 95 cm and 10 for 1 m. When used a 2.5-cm range finder at 1k pulses per second, the power consumption of the transceiver is 1 W. The electronic field intensity is lower than 35 V/m, in compliance with the regulations for extremely low-power radio stations. Takahide Terada received the B.S. and M.S. degrees in electrical engineering from Keio University, Yokohama, Japan, in 2003 and 2005, respectively. In 2005, he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, where he has been engaged in the research and development of an ultrawideband transceiver. Shingo Yoshizumi received the B.S. and M.S. degrees in electrical engineering from Keio University, Yokohama, Japan, in 2003 and 2005, respectively. In 2005, he joined Sony, Tokyo, Japan, where he has been engaged in the development of power supply circuits. ACKNOWLEDGMENT The authors are grateful to members of STARC. The VLSI chip in this work was fabricated in the chip fabrication program of the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Hitachi Ltd. and Dai Nippon Printing Corporation. REFERENCES [1] Federal Communications Commission (FCC), Ultra-Wideband (UWB) First Report and Order, Feb [2] M. Z. Win and R. A. Scholtz, Impulse radio: how it works, IEEE Commun. Lett., vol. 2, no. 2, pp , Feb [3] I. D. O Donnell, M. S. W. Chen, S. B. T. Wang, and R. W. Brodersen, An integrated, low-power, ultra-wideband transceiver architecture for low-rate indoor wireless system, presented at the IEEE CAS Workshop on Wireless Communications and Networking, Pasadena, CA, Sep [4] R. Blazquez, P. P. Newaskar, F. S. Lee, and A. P. Chandrakasan, A baseband processor for pulsed ultra-wideband signals, in Proc. CICC, Oct. 2004, pp [5] A. Kasamatsu, A. Tanaka, H. Kodama, S. Tanoi, Y. Kaizaki, J. Nakada, M. Hagio, Y. Kuraishi, K. Li, H. Utagawa, T. Matsui, and R. Kohno, Overview of experimental device implementation in CRL UWB R&D consortium, in Proc. Int. Workshop on UWBST&IWUWBS, May 2004, pp Muhammad Muqsith was born in Jakarta, Indonesia, on December 12, He is currently working toward the B.S. degree in electrical engineering at Keio University, Kanagawa, Japan. He has been engaged in research on RF CMOS integrated circuit design for wireless applications. Yukitoshi Sanada (S 93 M 97) was born in Tokyo, Japan, in He received the B.E. degree in electrical engineering from Keio University, Yokohama, Japan, the M.A.Sc. degree in electrical engineering from the University of Victoria, BC, Canada, and the Ph.D. degree in electrical engineering from Keio University, Yokohama, Japan, in 1992, 1995, and 1997, respectively. In 1997, he joined the Faculty of Engineering, Tokyo Institute of Technology, as a Research Associate. In 2000, he joined the Advanced Telecommunication Laboratory, Sony Computer Science Laboratories, Inc., as

8 898 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 an associate researcher. In 2001, he joined the Faculty of Science and Engineering, Keio University, where he is now an Assistant Professor. His current research interest is in software defined radio and ultra-wideband systems. Dr. Sanada received the Young Engineer Award from IEICE Japan in Tadahiro Kuroda (M 88 SM 00 F 06) received the Ph.D. degree in electrical engineering from the University of Tokyo,Tokyo, Japan, in In 1982, he joined Toshiba Corporation, where he designed CMOS SRAM, gate arrays, and standard cells. From 1988 to 1990, he was a Visiting Scholar with the University of California, Berkeley, where he conducted research in the field of VLSI CAD. In 1990, he was back to Toshiba, and engaged in the research and development of BiCMOS ASICs, ECL gate arrays, high-speed CMOS LSIs for telecommunications, and low-power CMOS LSIs for multimedia and mobile applications. He invented a variable threshold-voltage CMOS (VTCMOS) technology to control VTH through substrate bias, and applied it to a DCT core processor and a gate array in He also developed a variable supply-voltage scheme using an embedded DC DC converter, and employed it to a microprocessor core and an MPEG-4 chip for the first time in the world in In 2000, he moved to Keio University, where he has been a Professor since His research interests include low-power, high-speed CMOS design for wireless and wireline communications, human computer interactions, and ubiquitous electronics. He has published more than 200 technical publications including 50 invited papers, and 18 books/chapters, and filed more than 100 patents. Dr. Kuroda served as a conference chair for the Symposium on VLSI Circuits, a vice chair for ASP-DAC, a TPC chair for the Symposium on VLSI Circuits, an invited program chair for A-SSCC, sub-committee chairs for ICCAD and SSDM, and program committee members for the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC, ISLPED, SSDM, ISQED, and other international conferences. He is a recipient of the 2005 P&I Patent of the Year Award. He is a Senior Member of the Institute of Electronics, Information, and Communication Engineers of Japan (IEICE).