SMD Type. DC-to-DC Converter Control Circuits. Features. Absolute Maximum Ratings Ta = 25

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1 SOP- Features Operation from.0 to 0 Input Low Standby Current Current Limiting Output Current to. A Output oltage Adjustable Frequency Operation to 00 khz Precision % eference PIN CONNEIONS epresentative Schematic Diagram Emitter Timing Capacitor Gnd (Top iew) Driver Sense CC Comparator Inverting Input Drive Sense CC Comparator Inverting Input Oscillator Comparator S Q Q 00 (Bottom iew). eference egulator Q Emitter Timing Capacitor Gnd This device contains active transistors. Absolute Maximum atings Ta = Parameter Symbol ating Unit Power Supply oltage CC 0 Comparator Input oltage ange I -0. to 0 oltage C(switch) 0 Emitter oltage (Pin = 0 ) E(switch) 0 to Emitter oltage CE(switch) 0 Driver oltage C(driver) 0 Driver Current (Note ) (driver) 00 ma Current ISW A SOP Package, D Suffix TA = C PD mw Thermal esistance JA 0 C/W Operating Junction Temperature TJ 0 C Operating Ambient Temperature ange TA 0 to0 C Storage Temperature ange Tstg -to0 NOTES:.Maximum package power dissipation limits must be observed..esd data available upon request.

2 DC-to-DC Converter Control Circuits KM0 ELEAL CHAAEISTS (CC =.0, TA = Tlow to Thigh [Note ], unless otherwise specified.) OSCILLATO Characteristics Symbol Min Typ Max Unit Frequency (Pin =0, =.0nF,TA = ) fosc khz Charge Current (CC =.0to0,TA = ) Ichg A Discharge Current (CC =.0to0,TA = ) Idischg A Discharge to Charge Current atio (Pin to CC, TA = ) Idischg/Ichg... Current Limit Sense oltage (Ichg =Idischg, TA = ) ipk(sense) m OUTPUT SWITCH (Note ) Saturation oltage, Darlington Connection (Note ) (ISW =.0 A, Pins, connected) Saturation oltage, Darlington Connection (ISW =.0 A, Pin = to CC, Forced 0) CE(sat).0. CE(sat) DC Current Gain (ISW =.0 A, CE =.0,TA = ) hfe 0 Off State Current (CE = 0 ) (off) A COMPAATO Threshold oltage th TA = TA =Tlow to Thigh Threshold oltage Line egulation (CC =.0to0) egline..0 m Input Bias Current ( = 0 ) IIB 0 00 na TOTAL DEE Supply Current (CC =.0to0, =.0 nf, Pin = CC, Pin >th, Pin = Gnd, remaining pins open) C.0 ma NOTES:.Low duty cycle techniques are used during test to maintain junctain juntion temperature as close to ambient temperature as possible..if the output switch is driven into hard saturation (non-darlington configuration)at low switch currents( 00mA) and high driver currents( 0mA),it may take up to.0 for it to come out of saturation.this condition will shorten the off time at frequencies 0 khz,and is magnified at high temperatures.this condition does not occur with a Darlington configuration,sincethe output switich cannot saturare.if a non-darlington configuration is used,the following output drive sondition is tecommended: output Forced of output switch: driver.0 ma * 0 *The 00 resistor in the emitter of the driver requires about ma before the output switch conducts. Marking Marking 0

3 I SMD Type DC-to-DC Converter Control Circuits KM0 on off, OUTPUT SWITCH ON-OFF TIME ( s) t CE(sat), SATUATION OLTAGE () IPK(sense), CUENT LIMIT SENSE OLTAGE () Figure. Output On Off Time versus Oscillator Timing Capacitor CC =.0 Pin=CC Pin = Gnd TA = , OSCILLATO TIMING CAPACITO (nf) Figure. Emitter Follower Configuration Output Saturation oltage versus Emitter Current. CC =.0. Pins,, = CC Pins, = Gnd. TA = (See Note ) IE, EMITTE CUENT (A) Figure. Current Limit Sense oltage versus Temperature 00 0 CC =.0 0 Ichg = Idischg TA, AMBIENT TEMPEATUE( ) ton toff CE(sat), SATUATION OLTAGE () CC, SUPPLY CUENT (ma), OSCILLATO OLTAGE () OSC Figure. Timing Capacitor Waveform CC =.0 Pin=CC Pin = Gnd Figure. Common Emitter Configuration Output Saturation oltage versus Current CC =.0 Pin = CC Pins,, = Gnd TA = (See Note ) Pins,, = Open =.0nF TA = 0 s/di Darlington Connection Forced = , COLLEO CUENT(A) Figure. Standby Supply Current versus Supply oltage =.0nF Pin = CC Pin = Gnd CC, SUPPLY OLTAGE () 00 m/di NOTE:. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.

4 Figure. Step Up Converter 0 H L 0 S Q Q Q CC Osc. Comp. ef eg 00 pf N9. k k.0 H / ma 0 CO 00 Optional Filter Test Conditions esults Line egulation =.0to,IO = ma 0 m =± 0.0% Load egulation =,IO = ma to ma 0 m =± 0.0% Output ipple =,IO = ma 00 mpp Efficiency =,IO = ma.% Output ipple With Optional Filter =,IO = ma 0 mpp. Figure. External Current Boost Connections for Peak Greater than A a. External NPN b. External NPN Saturated (See Note ) 0for constant NOTE:. If the output switch is driven into hard saturation (non Darlington configuration) at low switch currents 00 ma) and high driver currents 0 ma), it may take up to.0 s to come out of saturation. This condition will shorten the off time at 0 khz, and is magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a non Darlington configuration is used, the following output drive condition is recommended.

5 Figure 9. Step Down Converter S Q Q Q CC Osc Comp.. ef eg N9 L 0 pf 0 H. k. k 0 CO.0 /00 ma.0 H 00 Optional Filter Test Conditions esults Line egulation =to,io = 00 ma m =± 0.% Load egulation =,IO = 0mAto00mA.0 m =± 0.0% Output ipple =,IO = 00 ma 0 mpp Short Circuit Current =,L =0.. A Efficiency =,IO = 00 ma.% Output ipple With Optional Filter =,IO = 00 ma 0 mpp Figure 0. External Current Boost Connections for Peak Greater than A 0a. External NPN 0b. External PNP Saturated

6 Figure. oltage Inverting Converter S Q Q Q 0. Osc L H. to.0 00 CC Comp.. ef eg 00 pf N9. k f CO.0 H /00 ma 00 Optional Filter Test Conditions esults Line egulation =. to.0, IO = 00 ma.0 m =± 0.0% Load egulation =.0,IO = 0mAto00mA 0.0 =± 0.09% Output ipple =.0,IO = 00 ma 00 mpp Short Circuit Current =.0, L =0. 90 ma Efficiency =.0,IO = 00 ma.% Output ipple With Optional Filter =.0,IO = 00 ma 0 mpp Figure. External Current Boost Connections for Peak Greater than A a. External NPN b. External PNP Saturated

7 Figure. Design Formula Table Calculation Step Up Step Down oltage Inverting ton/toff out F in(min) out F out F in(min) sat in(min) sat out in sat (ton toff) f toff f f ton (ton toff) toff (ton toff) toff (ton toff) toff.0 x 0 ton.0 x 0 ton.0 x 0 ton (switch) I out(max) I out(max) I out(max) 0./(switch) 0./(switch) 0./(switch) L(min) ( in(min) sat ) ( in(min) sat out ) ( in(min) sat ) t t I on(max) I on(max) I pk(switch) pk(switch) pk(switch) (max) CO 9 I out I (t pk(switch) on t ) off 9 ripple(pp) ripple(pp) I out ripple(pp) sat = Saturation voltage of the output switch. F = Forward voltage drop of the output rectifier. The following power supply characteristics must be chosen: in Nominal input voltage. out Desired output voltage, I out Desired output current. out. f min Minimum desired output switching frequency at the selected values of in and I O. ripple(pp) Desired peak to peak output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its equivalent series ripple(pp) resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the line and load regulation.