Preliminary. TFT-LCD DC-DC Converters with Operational Amplifiers FP6793. Description. Features. Applications. Ordering Information.

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1 TFT-LCD DC-DC Converters with Operational Amplifiers Description The includes a high performance step-up regulator, two linear regulator controllers, and high current operational amplifiers for active-matrix, thin film transistor liquid-crystal displays (TFT-LCD). Also included is a logic-controlled, high-voltage switch with adjustable delay. The step-up DC-DC converter provides the regulated supply voltage for the panel source driver ICs. The converter is a high frequency (1.2MHz) current mode regulator with an integrated 22 N-channel MOSFET that allows the use of ultra-small inductors and ceramic capacitors. It provides fast transient response to pulsed loads while achieving efficiency over 85%. The gate-on and gate-off linear-regulator controllers provide regulated TFT gate-on and gateoff supplies using external charge pumps attached to the switching node. The includes five highperformance operational amplifiers. These amplifiers are designed to drive the LCD backplane ( COM ) and/ or the gamma-correction divider string. The device features high output current (±150mA), fast slew rate (13/μs), wide bandwidth (12MHz), and rail-to-rail inputs and outputs. The is available in a 32-pin thin TQFN package with a maximum thickness of 0.8mm for ultrathin LCD panels. Features 2.6 to 5.5 Input Supply ange 1.2MHz Current-Mode Step-Up egulator : Fast Transient esponse to Pulsed Load High Accuracy Output oltage Built-in 22, 0.16Ω N-Channel MOSFET High Efficiency at 90% Linear egulator Controllers for GON and GOFF Five High Performance Operational Amplifiers : ± 150mA Output Short-Circuit Current 13/μs Slew ate 12MHz, - 3dB Bandwidth ail-to-ail Inputs/Outputs Logic Controlled, High oltage Switch with Adjustable Delay Timer Delay Fault Latch for All egulator Outputs Thermal Overload Protection 0.6mA Quiescent Current ohs Compliant Applications Notebook Computer Displays LCD Monitor Panels Automotive Displays Pin Assignments WQ Package (TQFN-32) (5mm x 5mm) COMP FB IN LX OUT5 NEG5 POS5 OUT FBP DP FBN DN DEL CTL DN COM 32 9 NEG4 POS4 SUP OUT3 POS3 BGND POS2 NEG2 Ordering Information T: Tape / eel Blank: Tube P: Pb Free with Commercial Standard (ohs Compliant) G:Green Package Type WQ: TQFN-32 (5x5) SC EF AGND PGND OUT1 NEG1 POS1 OUT2 Figure 1. Pin Assignment of

2 Typical Application Circuit CP CN MAIN IN LX IN FB STEP-UP CONTOLLE COMP PGND AGND CP SUP NEG1 OUT1 POS1 _ OP1 + GATE-ON CONTOLLE DP FBP ON DEL NEG2 OUT2 POS2 OUT3 _ OP2 + _ OP3 + SWITCH CONTOLLE CTL SC COM DN CN POS3 NEG4 OUT4 _ OP4 + GATE-OFF CONTOLLE DN FBN OFF POS4 NEG5 OUT5 _ OP5 + EF EF POS5 BGND Figure 2. Typical Application Circuit of

3 Functional Pin Description Pin Name SC EF AGND PGND OUT1 NEG1 POS1 OUT2 NEG2 POS2 BGND POS3 OUT3 SUP POS4 NEG4 OUT4 POS5 NEG5 OUT5 LX IN FB COMP FBP DP FBN DN DEL CTL DN COM Pin Function Switch Input. Source of the internal high-voltage P-channel MOSFET. Bypass SC to PGND with a minimum 0.1μF capacitor close to the pins. eference Bypass Terminal. Bypass EF to AGND with a minimum of 0.22μF close to the pins. Analog Ground for Step-up egulator and Linear egulators. Connect to power ground (PGND) underneath the IC. Power Ground. PGND is the source of the main step-up N-channel power MOSFET. Connect PGND to the output capacitor ground terminals through a short, wide PC board trace. Connect to analog ground (AGND) underneath the IC. Operational-Amplifier 1 Output Operational-Amplifier 1 Inverting Input Operational-Amplifier 1 Non-inverting Input Operational-Amplifier 2 Output Operational-Amplifier 2 Inverting Input Operational-Amplifier 2 Non-inverting Input Analog Ground for Operational Amplifiers. Connect to power ground (PGND) underneath the IC. Operational-Amplifier 3 Non-inverting Input Operational-Amplifier 3 Output Operational-Amplifier Power Input. Positive supply rail for the operational amplifiers. Typically connected to MAIN. Bypass SUP to BGND with a 0.1μF capacitor. Operational-Amplifier 4 Non-inverting Input Operational-Amplifier 4 Inverting Input Operational-Amplifier 4 Output Operational-Amplifier 5 Non-inverting Input Operational-Amplifier 5 Inverting Input Operational-Amplifier 5 Output N-Channel Power MOSFET Drain and Switching Node. Connect the inductor and Schottky diode to LX and minimize the trace area for lowest EMI. Supply oltage Input. IN can range from 2.6 to 5.5. Step-up egulator Feedback Input. egulates to (nominal). Connect a resistive voltage-divider from the output (MAIN) to FB to analog ground (AGND). Place the divider within 5mm of FB. Step-up egulator Error-Amplifier Compensation Point. Connect a series C from COMP to AGND. Gate-On Linear-egulator Feedback Input. FBP regulates to (nominal). Connect FBP to the center of a resistive voltage-divider between the regulator output and AGND to set the gate-on linear regulator output voltage. Place the resistive voltage-divider close to the pin. Gate-On Linear-egulator Base Drive. Open drain of an internal N-channel MOSFET. Connect DP to the base of an external PNP pass transistor. Gate-Off Linear-egulator Feedback Input. FBN regulates to 250m (nominal). Connect FBN to the center of a resistive voltage-divider between the regulator output and EF to set the gate-off linear regulator output voltage. Place the resistive voltage-divider close to the pin. Gate-Off Linear-egulator Base Drive. Open drain of an internal P-channel MOSFET. Connect DN to the base of an external NPN pass transistor. High-oltage Switch Delay Input. Connect a capacitor from DEL to AGND to set the high-voltage switch startup delay. High-oltage Switch Control Pin Switch Input. Drain of the internal high-voltage back-to-back P-channel MOSFETs connected to COM. Internal High-oltage MOSFET Switch Common Terminal. Do not allow the voltage on COM to exceed SC

4 Block Diagram fitipower integrated technology lnc. CLOCK ESET DOMINANT S LX PGND Q ILIM COMPAATO SLOPE COMP SOFT- STAT LIMIT PWM COMPAATO M CUENT SENSE OSCILLATO FAULT COMPAATO TO FAULT LATCH 1.0 FB COMP Figure 3. Step-Up egulator Functional Diagram LX BOOST LX 0.1µF 0.9 LDO_ON 0.1µF LDO_OFF CP (to -26) PG_LDOP 36 ESD CLAMP BP 700Ω CP (to 36) 0.1µF PG_LDON 0.4 FBN N2 20kΩ EF 0.1µF DP FBP P1 P2 20kΩ ON (to 35) C ON 1:Nn DN N1 OFF (to -20) C OFF GMP 1:Np GMN 36 ESD CLAMP BN 700Ω Figure 4. Gate-on Functional Block Diagram Figure 5. Gate-off Functional Block Diagram

5 Block Diagram (Continued) IN 5µA 2.5 FB OK FBP OK FBN OK DEL Q1 SC EF COM CTL 1kΩ Q2 Q3 DN Figure 6. Switch Control Functional Block Diagram

6 Absolute Maximum atings IN, CTL to AGND to + 6 COMP, FB, FBP, FBN, DEL, EF to AGND to ( IN + 0.3) PGND, BGND to GND ± 0.3 LX to PGND to + 22 SUP to AGND to + 22 DP, SC to AGND to + 30 POS, NEG, OUT to AGND to ( SUP + 0.3) POS1 to NEG1, POS2 to NEG2, POS3 to NEG3, POS4 to NEG4, POS5 to NEG to + 6 DN to AGND ( IN - 30) to ( IN + 0.3) COM, DN to AGND to ( SC + 0.3) DN to COM to + 30 OUT_ Maximum Continuous Output Current ± 200mA LX Switch Maximum Continuous MS Output Current A Continuous Power Dissipation (T A = + 70 C), 32-Pin TQFN W Package Thermal esistance, 32-Pin TQFN (θ JA ) C/W Junction Temperature C Storage Temperature ange C to C Lead Temperature (Soldering, 10s) C ESD Susceptibility HBM(Human Body Mode) K MM(Machine Mode) Note:Stresses beyond those listed under Absolute Maximum atings" may cause permanent damage to the device. ecommended Operating Conditions Supply oltage ( IN ) to OP Supply oltage( SUP ) to +20 Operation Temperature ange C to + 85 C

7 Electrical Characteristics ( IN = 5, SUP = 10, PGND= AGND= BGND= 0, I EF = 25μA, T A =+ 25 C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Units IN Supply ange IN IN ULO Threshold ULO 2.5 Quiescent Current I IN FB = FBP = 1.4, FBN = ma Fault Condition Duration 210 ms EF Output oltage Thermal Shutdown 160 o C MAIN STEP-UP EGULATO Output oltage ange MAIN IN 20 Operation Frequency f OSC 1.2 MHz Max. Duty 90 % FB egulation oltage FB FB Fault Trip Level FB falling 1.0 LX On-esistance LX (ON) 160 mω LX Leakage Current I LX LX = μa LX Current Limit I LIM FB = 1, duty cycle = 65% 3.0 A Current-Sense Transconductance 3.8 S Soft-Start Period t SS 14 ms OPEATIONAL AMPLIFIES SUP Supply ange SUP SUP Supply Current I SUP Buffer configuration, POS = 5, no load 3.2 ma Input Offset oltage OS ( NEG, POS, OUT ) SUP / 2, T A = + 25C 0 m Input Bias Current I BIAS ( NEG, POS, OUT ) SUP / na Output oltage Swing, High Output oltage Swing, Low OH OL I OUT = 100μA SUP -3 I OUT = 5mA SUP -80 m I OUT = -100μA 2 I OUT = -5mA 70 m Short-Circuit Current To SUP / 2, source or sink 200 ma Output Source and Sink Current ( NEG, POS, OUT ) SUP / 2, OS < 10m 100 ma Power-Supply ejection atio PS DC, 6 SUP 13, ( NEG, POS ) SUP / 2 60 db Slew ate 13 /μs -3dB Bandwidth L = 10kΩ, C L = 10pF, buffer configuration 12 MHz Gain-Bandwidth Product GBW Buffer configuration 8 MHz GATE-ON LINEA-EGULATO CONTOLLE FBP egulation oltage FBP I DP = 100μA FBP Fault Trip Level FBP falling 1.00 FBP Input Bias Current I FBP FBP = na FBP Effective Load-egulation Error (Transconductance) DP = 10, I DP = 50μA to 1mA % FBP Line (IN) egulation Error I DP = 100μA, 2.6 < IN < 5.5 ± 1.5 m DP Sink Current I DP FBP = 1.1, DP = 10 5 ma

8 Electrical Characteristics (Continued) DP Off-Leakage Current FBP = 1.4, DP = μa Soft-Start Period t SS 14 ms GATE-OFF LINEA-EGUALTO CONTOLLE FBN egulation oltage FBN I DN = 100μA 250 m FBN Fault Trip Level FBN rising 420 m FBN Input Bias Current I FBN FBN = 0 1 na FBN Effective Load-egulation Error (Transconductance) DN = -10, I DN = 50μA to 1mA 11 m FBN Line (IN) egulation Error I DN = 0.1mA, 2.6 < IN < m DN Source Current I DN FBN = 500m, DN = ma DN Off-Leakage Current FBN = 0, DN = μa Soft-Start Period t SS 14 ms Soft-Start Step Size EF /128 POSITIE GATE-DIE TIMING AND CONTOL SWITCHES DEL Capacitor Charge Current During startup, DEL = 1 5 μa DEL Turn-On Threshold TH(DEL) 1.25 DEL Discharge Switch On- esistance During ULO, IN = Ω CTL Input Low oltage IN = 2.6 to CTL Input High oltage IN = 2.6 to CTL Input Leakage Current CTL = AGND or IN μa CTL-to-SC Propagation Delay 100 ns SC Input Current I SC 1 ma SC to COM Switch On- esistance DN to COM Switch On- esistance SC(ON) DEL = 1.5, CTL = IN 6 Ω DN(ON) DEL = 1.5, CTL = AGND 35 Ω

9 Typical Performance Curves Efficiency(%) Switching Frequency (MHz) in = Load Current (ma) Temperature (oc) Figure 7. Step-up Efficiency vs. Load Current Figure 8. Switching Frequency vs. Temperature Switching Frequency (MHz) Supply Current (ua) in = Input oltage () Temperature (oc) Figure 9. Switching Frequency vs Input oltage Figure 10. Step-up Supply Current vs. Temperature Supply Current (ma) SUP = 10 Supply Current (ua) Temperature Supply oltage () Figure 11. OP Supply Current vs. Temperature Figure 12. Step-up Supply Current vs. Supply Current

10 Typical Performance Curves (Continued) GON = GATE-OFF = -8 Output oltage() Output oltage () Load Current (ma) Load Current (ma) Figure 13. Gate-on egulator Load egulation Figure 14. Gate-off egulator Load egulation GON = Output oltage () Output oltage (%) Input oltage () Input oltage () Figure 15.Gate-on egulator Line egulation Figure 16.Gate-off egulator Line egulation Figure17.Power-up Sequence Figure 18.Step-up Pulsed Load-Transient esponse

11 Typical Performance Curves (Continued) Figure19. Timer Delay Latch esponse to Overload Figure 20. Gate-on Slice Waveform Figure21.Operational Amplifier ail-to-ail Input/Output Figure22. Operational-Amplifier Large-Signal Step esponse Figure23. Operational-Amplifier Small-Signal Step esponse Figure24. Operational-Amplifier Load Transient esponse

12 Application Information Operation The series are multiple-output DC-DC converter IC which is designed primarily for use in thin-film transistor (TFT) liquid crystal display (LCD) applications. It features a PWM step-up converter operating with a fixed switching frequency of 1.2 MHz and uses internal N-MOS to provide maximum efficiency. The output voltage of the main step-up converter can be set from IN to 15 with external resistive divider. A pair of charge-pump independently regulate a positive output CP and a negative output CN for TFT gate-on and gate-off supplies. These charge-pump regulators consist of an external diode-capacitor charge pump powered from the power N-MOS (LX) of the boost converter. The internal gate pulse modulator is independent from this system to improve flicker. also consists of a precision reference, logic shutdown, current-limited, soft-start, power-up sequencing and thermal shutdown. Main Boost Converter The boost converter operates in fast transient response, current-mode PWM and a constant frequency of 1.2 MHz, allowing the use of smaller external inductor and output capacitors. Depending on duty cycle of each switching cycle can regulate output voltage. Figure 3 shows main step-up converter block diagram. On the rising edge of the internal clock, the control and driver logic block sets internal flip-flop when the output voltage is too low, which turns on the N-MOS. The external inductor current ramps up linearly, storing energy in a magnetic filed. Once peak current of inductor over trans-conductance output level, the N-MOS turns off, the flip-flop resets, and external schottky diode turns on. This forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and load. To add higher flexibility to the selection of external component values, the device uses external loop compensation Negative Linear-egulator Controller ( OFF ) Negative linear-regulator controller inverts the supply voltage ( CN ) and provides a regulated negative output voltage to power the row driver in the LCD panel. Figure 5 shows gate-off functional block diagram block. The controller regulates charge-pump output voltage ( CN ) to OFF from -5 to -25 and suppliers up to 50mA by an external NPN transistor as the pass element. The gate-off linear-regulator output voltage can be adjusted by a resistive voltage-divider from the OFF output to AGND with the center tap connected to FBN Positive Linear-egulator Controller ( ON ) Positive linear-regulator controller also inverts the supply voltage ( CP ) and provides a regulated positive output voltage to power the row driver in the LCD panel. Figure 4 shows gate-on functional block diagram block. The controller regulates charge-pump output voltage ( CP ) to ON from 15 to 30 and suppliers up to 50mA by an external PNP transistor as the pass element. The gate-on linear-regulator output voltage can be adjusted by a resistive voltage-divider from the ON output to AGND with the center tap connected to FBP. Gate-On Slice Modulator The includes a gate-on slice modulator to control row driver power by CTL and DEL signal to reduce flicker. Active the first step by connecting positive linear regulator output ( ON ) to SC. There are two different modes of operation. In mode 1, DEL pin connect an external capacitor to adjust gate-on slice pulse-width. When CTL is logic high, Q1 turns on and Q2, Q3 turns off, connecting SC to COM. When CTL is logic low and DEL exceeds 1.25, Q1 turns off and Q2 turns on, connecting COM to DN. COM can be discharged through a resistor connected between COM and Q3. Q3 turns off and stop discharging COM when DN reaches setting voltage by connecting a resistive from the DN output to MAIN to AGND. The rising edge of CTL discharges an external capacitor between DEL and AGND. The falling edge of TCI enables an internal 5 ua current source to start charging the DEL capacitor. Once DEL exceeds 1.25(Typ.), gate-line data is latched on line buffer. In mode 2, DEL pin tied to IN, therefore gate-on slice pulse-width couldn t be adjusted and just follow CTL timing to control ON/Off time of COM voltage. Power-Up Sequencing The goes through start-up sequence after power-up or exiting shutdown. First, the reference power-up, then the main DC-DC step-up converter powers up with soft-start enable. Once the main DC-DC step-up converter starts, the negative charge pump and positive charge pump turns on until output voltage of step-up converter and two linear- regulator controllers to nominal voltage, see figure

13 Application Information (Continued) When the junction temperature exceeds Tj= +140 C, the thermal sensor signals the shutdown logic and turns off most of the internal circuitry. The thermal sensor turns internal circuitry on again after the IC cycle the input voltage to clear the thermal shutdown latch. Under oltage Lockout The under voltage lockout (ULO) circuit provides the save operation to keeps the device from turning on when IN is smaller than typically 2.5. Soft-Start Figure 25 Power Sequence OP Amps The series have 5 amplifiers. The op amps are typically used to drive the TFT-LCD backplane (COM) or the gamma-correction divider string. They feature rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (typical 3.2mA per amplifier). The series have a 3dB bandwidth of 12MHz while maintaining a 13/us slew rate. Delay Control Circuit A capacitor from DEL pin to AGND modulates delay of gate-on slice pulse-width. When the positive linear-regulator output voltage ( ON ) reaches approximately of its nominal value, a 5.0uA current source charges C DEL. Once the capacitor voltage exceeds 1.25, enabling the gate-on slice modulator startup. Select C DEL using the following equation: C DEL = T DELAY 5uA Current Limit Protection The provides cycle-by-cycle over-current protection. Current limit is accomplished by sensing voltage drop across the drain to source of power switch. If the current sense amplifier output voltage is larger than current-limited threshold level (Typ. 3.0 A), it will be immediately turned off power MOS. The current-limit feature protects over current fault at the output. Thermal Overload Protection Thermal-overload protection limits total power dissipation in the. Soft-start allows a gradual increase of the internal current-limit level for the main step-up converter during power-up to reduce input surge currents. As the internal constant current source charges the internal soft-start capacitor, the peak N-MOS current is limited by the voltage on the capacitor. Output Fault Trip Circuit Protection If feedback voltage of the main regulator falls below 1.0, positive linear-regulator falls below 1.0 and negative linear regulator falls below 420m, the internal logic controller will delay a time to turn off all output drivers. However, the reference remains active. When short- circuit problem is to eliminate, cycle the input voltage to clear the fault latch. Adjustable Step-up Converter Output oltage The output voltage of ranges from IN to 15.0 which is set by the external feedback resistor. It can be calculated as: MAIN = ( 1 + MAIN 1 MAIN 2 Adjustable Gate-on Linear egulator Output oltage The Gate-on Linear egulator output voltage can be set by the external feedback resistor from ON to AGND. A resistor network in the order of 20kΩ is recommended. It can be calculated as: ON = ( 1+ P1 P2 Adjustable Gate-off Linear egulator Output oltage ) )

14 Application Information (Continued) The Gate-off Linear egulator output voltage can be set by the external feedback resistor from OFF to AGND. A resistor network in the order of 20kΩ is recommended. It can be calculated as: OFF = FBN ( 1 + N1 N2 ) N1 N2 where EF =1.233 as specified. Positive and Negative Charge Pump EF The contains two independent charge pump. The regulation of both the negative and positive charge pumps is generated by external diode-capacitor connecting to LX pin. The single stage of positive charge-pump is given by: CP ON + MAIN 2 EC PNP DF MAIN where EC-PNP is the dropout margin for the PNP linear regulator, DF is the forward-voltage drop of the charge-pump diode. The single stage of negative charge-pump is given by: CN OFF MAIN + 2 CE NPN DF where CE-NPN is the dropout margin for the NPN linear regulator, DF is the forward-voltage drop of the charge-pump diode. Applications Information External components of main boost converter can be designed by performing simple calculations. It need to follow regulation by the output voltage and the maximum load current, as well as maximum and minimum input voltages. Begin by selecting an inductor value. Once L is know, choose the diode and capacitors. Inductor Selection A 3.3uH to 10uH is recommended for general used. The value of inductor depends on the operating frequency. Higher frequency allows smaller inductor and capacitor but increase internal switching loss. Two inductor parameters should be considered, current rating and DC. The DC of inductor affects the efficiency of the converter. The inductor with lowest DC is chosen for highest efficiency. The inductor value can be calculated as: I L : inductor ripple current, which defined as: O Δ I L = O[( 1 ) /( L * f )] I The inductor should be rated for the maximum output current (IO ( MAX )) plus the inductor ripple current ( IL) to avoid saturation. The maximum inductor current (IL( MAX )) is given by: I L( MAX ) = I O(max) Capacitor Selection ΔI + 2 The is permissible in using ceramic capacitor for TFT LCD panel application. The value of capacitor depends on acceptable voltage ripple. The input capacitor can reduced peak current and noise at power source. It should have 22uF at least and can be increased for better input voltage filtering. Select the input capacitor to meet the input ripple current and voltage rating. When selecting an output capacitor, consider the output ripple voltage and the ripple current. The ES of capacitor is a major factor to the output ripple. For best performance, a low ES output capacitor is required. The ripple voltage is given by: Δ O = ΔI L ( ES + L 1 ) 8* f * Co The common aluminum-electrolytic capacitors have high ES and should be avoided. Ceramic capacitors have the lowest ES in general. It uses 22uF ceramic output capacitors for the. Diode Selection For diode selection, both forward voltage and diode capacitance need to be considered. The output diode should be rated to the output voltage and peak switch current. Schottky diodes, with Their low forward voltage drop and fast reverse recovery, are the ideal choices for applications. Make sure the diode s peak current rating is at least IPK and its breakdown voltage exceeds MAIN

15 Application Information (Continued) Compensation The Main step-up loop can be compensated by adjusting the external components connected to the COMP pin. The COMP pin is connected to the output of the internal trans-conductance error amplifier. The compensation capacitor adjusts the low frequency gain, and the series resistor value adjusts the high frequency gain. The following formula calculates at what frequency the resistor increases the high frequency gain. f Z 1 = 2 π C C C If the device operates over the entire input voltage range from 2.6 to 5.5, a larger compensation capacitor up to 220pF is recommended. For a good load transient where no oscillation should occur, 180 KΩ is recommended for C resistor. Layout Consideration Careful printed circuit layout is extremely important to avoid causing parasitical capacitance and line inductance. The following layout guidelines are recommended to achieve optimum performance. Please the Boost converter diode and inductor close to the LX pin and no via. Please ceramic bypass capacitors near the IN pin and EF pin. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace. Place Cout next to schottky diode as possible. Use wide traces and trace length is short as possible to the LX node. Keep the noise-sensitive feedback (FB, FBP, and FBN) away from the switching node. The power ground (PGND) and signal ground (AGND) pins should be connected at only one point. The exposed pad, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers

16 Outline Information TQFN- 32 Package (Unit: mm) SYMBOLS DIMENSION IN MILLIMETE UNIT MIN NOM MAX A A A (TYP) --- E 4.95 ) D L b e (TYP) --- Y E D Note 1:Followed From JEDEC MO-220-J Life Support Policy Fitipower s products are not authorized for use as critical components in life support devices or other medical systems