MIXED SIGNAL VLSI WIRELESS DESIGN. Circuits and Systems

Transcription

1 MIXED SIGNAL VLSI WIRELESS DESIGN Circuits and Systems

2 MIXED SIGNAL VLSI WIRELESS DESIGN Circuits and Systems Emad N. Farag Lucent Technologies and Mohamed I. Elmasry University of Waterloo KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

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4 Contents List of Figures List of Tables Preface Acknowledgments List of Acronyms ix xvii xix xxi xxiii 1. INTRODUCTION The History of Wireless Communications Wireless Communications Basics Wireless Communications Standards Terminology Book Organization WIRELESS COMMUNICATION SYSTEMS - OVERVIEW Introduction Digital Communication Systems Minimum Bandwidth Requirement (The Nyquist Limit) The Shannon Limit Optimum Receiver Design for Band-pass Digital Systems THE MOBILE RADIO Introduction The Cellular Concept Channel Impairments Large Scale Fading Doppler Shift Small Scale Fading Diversity Techniques in Wireless Communications DIGITAL MODULATION SCHEMES Introduction 87

5 vi MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS Amplitude Shift Keying Phase Shift Keying Frequency Shift Keying Digital Modulation Techniques Comparisons SPREAD SPECTRUM Introduction Basic Principles of Spread Spectrum Spread Spectrum Techniques Pseudorandom Noise Sequence Practical Considerations in Spread Spectrum Systems RECEIVER ARCHITECTURES Introduction Noise Figure Intermodulation distortion The Superheterodyne Receiver The Homodyne Receiver Software Radio ANALOG TO DIGITAL CONVERSION Introduction Performance Metrics of Analog-to-Digital Converters Sampling Band-pass Sampling Quantization Types of Analog-to-Digital Converters Sigma-Delta Analog-to-Digital Converters VLSI DESIGN ISSUES IN WIRELESS TRANSCEIVER DESIGN Introduction Transceiver Design Constraints Baseband Subsystem Design RF Subsystem Design LOW-POWER DESIGN TECHNIQUES Introduction Sources of Power Dissipation Estimating the Power Dissipation Low-Power Examples of Portable Systems Reducing the Power Dissipation at the Device and Circuit Levels Low-Voltage Low-Power Operation Reducing the Power Dissipation at the Architecture and Algorithm Levels

6 Contents vii 10. AMPLIFIER DESIGN FOR WIRELESS COMMUNICATION SYSTEMS Introduction Amplifier Design Low Noise Amplifier Automatic Gain Control Amplifiers Power Amplifiers PHASE LOCKED LOOPS Introduction Operation of the Phase Locked Loop Phase Detectors Frequency Dividers Oscillator Design FREQUENCY SYNTHESIZERS Introduction Frequency synthesizer (FS) parameters Frequency Synthesizer Techniques Analyzing phase noise in frequency synthesizers Summary Bibliography 306 Index 317

7 List of Figures Frequency assignments made to terrestrial and satellite FPLMTS (IMT-2000) systems by WARC-92. Classification of wireless communication systems. Electromagnetic spectrum of radio waves. A generic transceiver. A single-stage up conversion transmitter. Direct conversion (homodyne) receiver. A Two-stage superheterodyne receiver. Allocated frequency spectrum for the AMPS system. Frame structure for IS-136. Slot format for a forward link digital traffic channel. Slot format for a reverse link digital traffic channel. Coding of a voice channel in IS-136. Signal processing in the forward link transmitter of a CDMA system. Signal processing in the reverse link transmitter of a CDMA system. A wireless telecommunications system. Generic block diagram of a digital transmitter. Generic block diagram of a digital receiver. Inter-symbol interference-free filters. The transfer function of a raised cosine filter. The impulse response of a raised cosine filter. The impulse response of a realizable approximation of the impulse response of a raised cosine filter. The input impulse sequence to a raised cosine filter having a truncated and delayed impulse response. The output response of a raised cosine filter having a truncated and delayed impulse response

8 x MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS The peak-to-peak jitter, versus the roll-off factor, of a raised cosine filter. A rate-1/2 convolution encoder, with a constraint length of 3. The finite state machine representation of a convolution encoder. The trellis diagram of a convolution encoder. Interleaving and De-interleaving. Block Interleaving and de-interleaving. Convolution Interleaver and De-interleaver. Additive white Gaussian noise channel model. Conditional probability density function at the output of the receiver s sampler. Correlation receiver. Wireless system satisfying the Nyquist criteria for no inter-symbol interference and the matched filter criteria for optimum bit error rate performance. Cell shape. Base station location relative to the cell boundary. Co-channel interference in the cellular system. Relative positioning of two cells allocated the same portion of the frequency spectrum in a cellular system. Cellular system cell plan having a cluster size of seven cells. Cell splitting in cellular systems. Intersystem handoff. Two ray propagation model: Direct line of sight (LOS) ray and ground reflected ray. Illustration of the Doppler shift. Small scale fading in a multi-path time-variant channel. Rayleigh fading: Multi-wave reception. Probability distribution function (pdf) and cumulative distribution function (CDF) for a Rayleigh distributed random variable. Envelope variation of a band-limited Rayleigh distributed random process versus time. Envelope probability density function in a Ricean fading environment. A three rake finger receiver. Amplitude shift keying (ASK) waveforms. The power spectral density of an amplitude shift keying (ASK) modulated signal

9 List of Figures Bit error rate for coherent and non-coherent amplitude shift keying (ASK) demodulation. Binary phase shift keying (BPSK) waveforms. Differential binary phase shift keying (DBPSK) modulation and demodulation. Differential binary phase shift keying (DBPSK) waveforms. Signal-space diagram for quadrature phase shift keying (QPSK) modulation. Quadrature phase shift keying (QPSK) modulator. Quadrature phase shift keying (QPSK) waveforms. Quadrature phase shift keying (QPSK) demodulator. Offset quadrature phase shift keying (OQPSK) waveforms. Differential quadrature phase shift keying (DQPSK) demodulator. The space diagram of a system showing all allowable phase state transitions. The carrier recovery circuit for a modulated signal. Limiter discriminator detector for a modulated signal. Differential detector for a modulated signal. The bit error rate of a modulation scheme. Minimum Shift Keying (MSK) waveforms. Minimum Shift Keying (MSK) Modulator. Minimum Shift Keying (MSK) Demodulator. Pulse response of a Gaussian low-pass filter. Gaussian Minimum Shift Keying (GMSK) Modulator. Power spectrum density for digital modulation schemes. Bit error rate for digital modulation schemes. The operation of spread spectrum systems. The direct sequence spread spectrum (DSSS) approach. Waveforms of a direct sequence spread spectrum (DSSS) system. The frequency hopping spread spectrum (FHSS) approach. The time hopping spread spectrum (THSS) approach. The Fibonacci Linear Feedback Shift Register. xi

10 xii MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS The Galois Linear Feedback Shift Register. A four stage linear feedback shift register used to generate PN sequences. A direct sequence spread spectrum (DSSS) system. Probability of false acquisition versus Early Late Tracker. On-time, early and late correlator outputs of an early late tracker. Noise figure in a one stage receiver. The noise figure of a two stage receiver. The noise figure of an n-stage receiver. Receiver used in the calculation of the noise figure. A two port non-linear network to illustrate non-linear distortion. The frequency spectrum of the output of a third-order non-linear two-port network. Intercept points for a third-order non-linear amplifier. Intercept points of a two-stage non-linear receiver. Intercept points of a n-stage non-linear receiver. Block diagram of a single-stage superheterodyne receiver. Image frequency in a superheterodyne receiver. A two-stage superheterodyne receiver. Single side-band mixer. Alternative single side-band mixer. The homodyne (zero-if) receiver. Aliasing in a homodyne receiver. The software radio architecture. Block diagram of an analog-to-digital converter (ADC). Block diagram of a digital-to-analog converter (DAC). Block diagram of a digital communications system. Non-linear transfer characteristic of an analog-to-digital converter. Sampling models. Ideal Sampling. The spectrum of a sampled-signal sampled at less than the Nyquist rate. Frequency spectrum of a pulse sampled signal. Frequency spectrum of a band-pass signal. Allowable band-pass sampling rates. Staircase transfer function of a mid-tread quantizer. Staircase transfer function of a mid-rise quantizer

11 List of Figures Quantization error versus input signal s magnitude for a mid-tread quantizer. Probability density function of the quantization error. Block diagram of an n-bit flash analog-to-digital converter. Transfer function of the amplifier used in the interpolative analog-to-digital converter. Interpolative analog-to-digital converter with an interpolation factor of 2. A three-bit interpolative analog-to-digital converter with an interpolation factor of three. Relation between and for different values of the amplifier gain (A), for the interpolative analog-to-digital converter of Figure A two-step analog-to-digital converter. A two-stage pipelined analog-to-digital converter. A two-step recycling analog-to-digital converter. Block diagram of a subranging analog-to-digital converter. Quantization intervals in a subranging analog-to-digital converter. Block diagram of a folding analog-to-digital converter. Block diagram of a folding circuit consisting of two amplifiers. Block diagram of a folding analog-to-digital converter having a coarse analog-to-digital converter with 4 quantization intervals. Folding analog-to-digital converter with a folding factor of 4. Output waveform of a 4-bit successive approximation analog-to-digital converter. Block diagram of a successive approximation analogto-digital converter. A Sigma-Delta Analog-to-Digital Converter. Block diagram of a first-order Sigma-Delta modulator. Frequency response of a first-order Sigma-Delta modulator. Block diagram of a second-order Sigma-Delta modulator. Block diagram of a second-order band-pass Sigma- Delta modulator. The decimation filter. xiii

12 xiv MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS The transfer function of a Sine decimator. Partitioning of a wireless mobile terminal. Block diagram of a Field Programmable Gate Array (FPGA). The FPGA design flow. The RF subsystem of a wireless communications system, Single-stage heterodyne receiver. Direct conversion receiver. Heterodyne transmitter having a single IF statge. Direct conversion transmitter. Direct conversion transmitter using two local oscillators. Four-input AND gate built using two-input AND gates. A simplified system consisting of two building blocks and the interconnection busses. The effect of reducing the supply voltage in CMOS circuits on delay and power dissipation. Unbalanced pipeline example. A two-datapath parallel system. Combining parallelism with pipelining to balance pipestage delays. Tree-Structured Vector Quantization. Circuit diagrams of BJT and FET amplifiers High-frequency hybrid pi-model of a bipolar junction transistor (BJT). High-frequency hybrid pi-model of a field effect transistor (FET). Noisy two-port network. A gain-controlled differential amplifier. A gain-controlled linearized differential amplifier. A gain-controlled amplifier. Class A power amplifier. The output waveform of a class A power amplifier. Class A power amplifier. Load line of a class A power amplifier. Class B power amplifier. Transfer characteristics of a class B power amplifier. Class C Power Amplifier. Waveforms of the collector current and output voltage for a class C power amplifier. Class F power Amplifier. Collector current and voltage waveforms for a class F power amplifier

13 List of Figures Block diagram of a phase locked loop (PLL). Block diagram of a phase locked loop (PLL) in the frequency-domain. Step response of a phase locked loop. Loop filter output versus phase error at the input of a multiplier phase detector. Input and output waveforms to an XOR digital phase detector. Output voltage of the loop filter versus the phase shift between the two inputs to an XOR digital phase detector. Block diagram of a digital phase detector using edgetriggered flip flops. State machine representation of the digital phase detector of Figure Transfer function of the digital phase detector of Figure Block diagram of an edge-triggered phase detector. Timing diagram for the edge-triggered phase detector of Figure 11.10, having a 180 phase shift between its inputs. Timing diagram for the edge triggered phase detector of Figure 11.10, having higher frequency on the reference input. Timing diagram for the edge triggered phase detector of Figure 11.10, having higher frequency on the oscillator input. Toggle flip flop. n-stage ripple counter. A synchronous divide-by-six counter. Timing diagram for a divide-by-six counter. A programmable comparator. Block diagram of a positive feedback oscillator Circuit diagram of a phase shift oscillator Generalized circuit diagram of the Colpitts/Hartley Oscillator. Small signal model for active devices. Generalized equivalent circuit for the Colpitts/Hartley Oscillator. Circuit diagram of a Colpitts Oscillator. Circuit diagram of a Hartley Oscillator. Equivalent circuit of the Colpitts/Hartley oscillator illustrating the oscillator s negative resistance. xv

14 xvi MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS Circuit diagram of the Clapp-Gouriet Oscillator. Crystal oscillator. Crystal oscillator reactance versus frequency. Circuit diagram of the Pierce Oscillator General frequency synthesizer structure. Frequency representation of a sine wave (a) in ideal form and (b) corrupted by phase noise. Typical output spectrum of a frequency synthesizer. Fractional-N PLL architecture. Block diagram of a generic fractional-n frequency divider. Divide-by-4/5 prescaler. Typical values stored in an accumulator of a pulse swallower counter. Frequency spectrum of spurs in a fractional-n divider [1]. Block diagram of API used in a fractional-n PLL synthesizer. Digital Sigma-Delta modulator. Conventional first-order Sigma-Delta modulator. Effect of Sigma-Delta modulator on spurs of fractional- N synthesizers [2]. Direct digital frequency synthesizer architecture. Phase noise in a closed-loop PLL system

15 List of Tables Spectrum allocation for mobile communications systems. Comparison of analog and digital communication techniques. Vocoder output rates. Zero crossing time variations of a raised cosine filter. Code-words for a (7,4) Systematic Block Code. Path loss exponent for different wireless environments. Differential encoding for quadrature phase shift keying. Number of one and zero runs of length n of a PN sequence generated using a 5-stage linear feedback shift register. Number of primitive polynomials of degree The output sequence of the linear feedback shift register of Figure 5.8. Power gain, noise figure, effective noise temperature for each stage of the receiver shown in Figure 6.4. The thermometer code of a binary coded signal. Latch outputs for an interpolative analog-to-digital converter with an interpolation factor of 2. Dynamic range versus OSR for first, second and third order Sigma-Delta modulators. Vector quantization: Computation and memory requirements. Conventional versus Fractional-N Frequency Dividers

16 Preface Wireless is coming was the message received by VLSI designers in the early 1990 s. They believed it. But they never imagined that the wireless wave would be coming with such intensity and speed. Today one of the most challenging areas for VLSI designers is VLSI circuit and system design for wireless applications. New generation of wireless systems, which includes multimedia, put severe constraints on performance, cost, size, power and energy. The challenge is immense and the need for new generation of VLSI designers, who are fluent in wireless communication and are masters of mixed signal design, is great. No single text or reference book contains the necessary material to educate such needed new generation of VLSI designers. There are gaps. Excellent books exist on communication theory and systems, including wireless applications and others treat well basic digital, analog and mixed signal VLSI design. We feel that this book is the first of its kind to fill that gap. In the first half of this book we offer the reader (the VLSI designer) enough material to understand wireless communication systems. We start with a historical account. And then we present an overview of wireless communication systems. This is followed by detailed treatment of related topics; the mobile radio, digital modulation and schemes, spread spectrum and receiver architectures. The second half of the book deals with VLSI design issues related to mixed-signal design. These include analog-to-digital conversion, transceiver design, digital low-power techniques, amplifier design, phase locked loops and frequency synthesizers. The book can be used in a senior undergraduate or graduate course on VLSI Design For Wireless Applications and can be also used by practicing engineers and managers working in this area. Basic background in both communication systems and VLSI design are assumed.

17 xx MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS We are aware of the hazards of trying, in a 300-plus page book, to bridge the gap between two engineering disciplines. Trading depth and breadth is only one such hazard. But our conviction for the need of such a book motivated us to write it. Moreover, the experience of writing it was enjoyable and we hope the book proves useful to our readers. Emad Farag Mohamed Elmasry Waterloo, Ontario, Canada

18 Acknowledgments We first acknowledge the blessings of God Almighty in our lives. The contributions of many people to this book, through discussions, is very much appreciated. The partial support received from Canadian Research granting agencies, and from Canadian, U.S. and Japanese industry and the University of Waterloo is acknowledged. Lucent Technology has provided to one of us (Farag) an excellent environment to complete this book. The VLSI Research Group at the University of Waterloo has been instrumental during the different phases of writing and we thank the faculty, staff and students. Finally, our families offered the necessary support to complete this book and we thank them dearly.

19 List of Acronyms 3G: ACI: ACTS: ADC: AGC: AM: AMPS: ARIB: ASIC: ASK: AWGN: BCCH: BER: BiCMOS: BJT: BPSK: CDF: CDMA: CDPD: CDVCC: CELP: CEPT: CMOS: CRC: CSMA: DAC: DBPSK: DCCH: DDFS: Third Generation Adjacent Channel Interference Advanced Communications Technologies and Services Analog-to-Digital Converter Automatic Gain Control Amplitude Modulation Advanced Mobile Phone Service Association of Radio Industries and Businesses Application Specific Integrated Circuit Amplitude Shift Keying Additive White Gaussian Noise Broadcast Control Channel Bit Error Rate Bipolar Complementary Metal Oxide Semiconductor Bipolar Junction Transistor Binary Phase Shift Keying Cumulative Distribution Function Code Division Multiple Access Cellular Digital Packet Data Code Digital Verification Color Code Code Excited Linear Prediction Conference of European Posts and Telecommunications Complementary Metal Oxide Semiconductor Cyclic Redundancy Check Carrier Sense Multiple Access Digital-to-Analog Converter Differential Binary Phase Shift Keying Dedicated Control Channel Direct Digital Frequency Synthesis

20 xxiv MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS DECT: Digital European Cordless Telephone DDI: Daini-Denden, Inc. DQPSK: Differential Quadrature Phase Shift Keying DSSS: Direct Sequence Spread Spectrum DSP: Digital Signal Processing/Processor DTC: Dedicated Traffic Channel EEPROM: Electrical Erasable Programmable Read Only Memory EIRP: Effective Isotropic Radiated Power EPROM: Erasable Programmable Read Only Memory ETACS: Extended Total Access Communication System ETSI: European Telecommunications Standards Institute FACCH: Fast Associated Control Channel FCC: Federal Communications Commission FCW: Frequency Control Word FDD: Frequency Division Duplexing FDMA: Frequency Division Multiple Access FEC: Forward Error Correction FET: Field Effect Transistor FHSS: Frequency Hopping Spread Spectrum FM: Frequency Modulation FPLMTS: Future Public Land Mobile Telecommunications System FS: Frequency Synthesizer FSK: Frequency Shift Keying FSVQ: Full Search Vector Quantization GaAs: Gallium Arsinide GHz: Giga Hertz GMSK: Gaussian Minimum Shift Keying GSM: Global System for Mobile communications previously known as Group Speciale Mobile HDL: Hardware Description Language IF: Intermediate Frequency IMPS: Improved Mobile Phone System IMT-2000: International Mobile Telecommunications 2000 IS: Interim Standard ISI: Intersymbol Interference ITU: International Telecommunications Union JFET: Junction Field Effect Transistor JTACS: Japanese Total Access Communication System JTC: Japanese Cordless Telephone kbps: Kilo bits per second Kcps: Kilo chips per second LAN: Local Area Network

21 XXV LNA: LOS: Mbps: Mcps: MHz: MIPS: MMIC: MOSFET: MSC: MSK: MTS: NAMPS: NF: NMOS: NMT: NTACS: NTT: OOK: OQPSK: PCS: PDC: pdf: PHS: PLL: PN: ppm: PSD: PSK: PSTN: QAM: QPSK: RACE: RAM: RF: ROM: QAM: QPSK: RACH: RAM: RSSI: SACCH: SCF: Low Noise Amplifier Line of Sight Mega bits per second Mega chips per second Mega Hertz Million Instructions Per Second Microwave Monolithic Integrated Circuit Metal Oxide Semiconductor Field Effect Transistor Mobile Switching Center Minimum Shift Keying Mobile Telephone System Narrow-band Advanced Mobile Phone Service Noise Figure N-type Metal Oxide Semiconductor Nordic Mobile Telephone Narrow-band Total Access Communication System Nippon Telephone and Telegraph On Off Keying Offset Quadrature Phase Shift Keying Personal Communications System Personal Digital Cellular Probability Density Function Personal Handy (phone) System Phase Locked Loop Pseudorandom Noise Part-Per-Million Power Spectral Density Phase Shift Keying Public Switched Telephone Network Quadrature Amplitude Modulation Quadrature Phase Shift Keying Research into Advanced Communications in Europe Random Access Memory Radio Frequency Read Only Memory Quadrature Amplitude Modulation Quadrature Phase Shift Keying Random Access Channel Random Access Memory Received Signal Strength Indicator Slow Associated Control Channel Shared Channel Feedback

22 xxvi MIXED SIGNAL VLSI WIRELESS DESIGN CIRCUITS AND SYSTEMS SiGe: SMS: SNR: SOI: SPACH: TAGS: TDD: TDMA: THSS: TIA: TSVQ: UE: UMTS: VCO: VHDL: VHSIC: VLSI: VSELP: W-CDMA: WARC: Silicon Germanium Short Message Service Signal-to-Noise Ratio Silicon-On-Insulator SMS Point-to-Point and Access Response Channel Total Access Communication System Time Division Duplexing Time Division Multiple Access Time Hopping Spread Spectrum Telecommunications Industry Association Tree Structured Vector Quantization User Equipment Universal Mobile Telecommunications System Voltage Controlled Oscillator VHSIC Hardware Description Language Very High Speed Integrated Circuit Very Large Scale Integration Vector Sum Excited Linear Prediction Wideband Code Division Multiple Access World Administrative Radio Conference