Methodology of Stable Probe Card Power Path Design for Wafer Level Testing

Transcription

1 Intel Test Operation Methodology of Stable Probe Card Power Path Design for Wafer Level Testing Sayed Mobin Intel Test Operation, Intel Corporation 2006 SouthWest Test Workshop 1

2 Agenda Example of Instability Instability in Probe Card Power Path Concept of Stability Analysis Stability Indicator Tool Performance of Closed Loop System Conclusion & Acknowledgement 2

3 Instability An Example Consider an automatic control system such as the stabilizer on a ship ๑ In the even of a roll the stabilizer change angle to correct it ๑ Suppose due to the delay in the response system, by the time the stabilizer responded the ship has already corrected the roll ๑ The stabilizer will now be in the wrong position and roll the ship further in the wrong way ๑ If this continues, rolling will go out of control and eventually the ship will sink. Effect of instability. 3

4 Instability An Example Instability can make any system go out of control and eventually destroy the system Stable Operation Happy Cruise Instable Operation?? Learning: Design your system as stable as possible. Or pay the consequences. 4

5 Probe Card Power Path Top-side Stiffening Hardware ATE Power Supply PCB Space Transformer Contact Probes DIE (DUT) Power Supply PCB Space x- former Probes Cres DUT (DIE) 5

6 Probe Card Power Path Vcc Tester SIU Feedback Sense Line DUT ATE power supply constantly sense the DUT voltage ๑ If DUT voltage is smaller than Vcc, ATE injects more current until the DUT voltage is Vcc Probe card power path constitute a Closed Loop System Response time of ATE power supplies are fast ( 1µs)( 6

7 Probe Card Power Path Stability Vcc 1.5V 1.4V Tester 5A 10A 15A SIU t=0 t=1us t=2us 2µs delay Feedback Sense Line DUT Vdut 1.4V Vdut 1.6V Vdut 1.8V At t=0 ๑ ATE sense 1.4V at Suppose there is 2µs 2 s delay in sense line ๑ ATE will inject more and more current for next 2µs2 7

8 The Problem Trend of ATE power supply output current with time Less Aggressive; Right Hand Turn 5X 15X 8

9 The Problem Higher power and fast response time causes the power supplies to be inherently less stable Instability can lead to ๑ Huge current surge and uncontrolled large voltage swings (Oscillation) on the power supply output 9

10 Probe Card Design Consideration Design a stable system with out compromising performance Power supply cannot protect against stability by itself It requires an optimum design of the rest of the power path, or more specifically, of the test interface board (Probe Card) 10

11 Concept of Closed Loop System V IN + _ V1 A V OUT V OUT OUT = Ax(V IN - βxv xv OUT ) βxv OUT β Gain = V V OUT IN = A 1+ Aβ 1+Aβ>1 (Negative Feedback) ๑ System is stable (gain<a) 1+Aβ<1 (Positive Feedback) ๑ System is unstable (gain>a) Computing A and β for a complex circuit is very hard Easier to work with voltages (V IN, V OUT ) in real life 11

12 Stability Indicator Tool t delay Input Signal Voltage (V) V OUT V IN time Gain Phase = 20 log = 10 V V OUT IN,dB t delay freq Output Signal Bode Plot: Plot of gain and phase of a closed loop system ๑ Powerful tool for ensuring stability 12

13 Bode Stability Criterion Gain Phase Phase Margin Phase Cross Over Freq 0 freq Gain Cross Over Freq Gain Margin For a closed loop system to be stable ๑ The gain should be below zero db at phase cross over freq ๑ The phase should be above zero deg at gain cross over freq 13

14 Performance Indicator Two fundamental characteristics of a closed loop system are Responsiveness and Stability Responsiveness is the transient response of the system Stability measures the quality of that response For optimum design both transient and stability requirements need to be met 14

15 Simulated Results Stability analysis has been performed on a Intel Chipset Product Simulations have been performed for the following two decoupling schemes ๑ Option 1: 2x2.2uF (ST) + 1x10uF (PCB) + 1x100uF (PCB) ๑ Option 2: 2x2.2uF (ST) + 2x10uF (PCB) + 3x100uF (PCB) Results have been validated with actual measurement 15

16 Bode Plot - Option 1 Gain Area of Interest Phase 16

17 Bode Plot Option 1 Gain Phase Gain Margin 1dB Gain Cross Over Freq 956KHz Phase Cross Over Freq 929KHz Phase Margin -5 deg Bode Stability Criterion violated. System Unstable. 17

18 Bode Plot Option2 Gain Phase Phase Margin 72 deg Phase Cross Over Freq 2MHz Bode Stability Criterion Met. System Stable. Gain Cross Over Freq 218KHz Gain Margin -21dB 18

19 Responsiveness Transient analysis is performed to meet the voltage droop, response and recovery time requirements Transient requirements are ๑ Voltage droop Allowable voltage droop target ๑ Response time 1 us ๑ Recovery time 25 us ๑ Overshoot 50mV Response Time ๑ Time difference between the start of voltage droop to the minimum of voltage droop Recovery Time ๑ Time difference between the start of voltage droop to the voltage when it reaches to -1% of Vcc nominal after the minimum droop 19

20 Transient Response Option2 Vcc nominal Recovery Time < 25µs -1% of Vcc nominal Vdut (V) 2 nd Droop 12% 1 st Droop 14% Response Time < 1µs Transient Response Requirements are met Time (us) 20

21 Conclusion Tester (ATE) power supply instability is a significant problem in tooling power path design Stable power path can be designed following power supply decoupling guide line However for an optimum design it requires to perform both stability and transient analysis ๑ Particularly true if active components are introduced in probe cardc 21

22 Acknowledgements Author would like to thank Ai Ssa Chai, Arthur Isakharov & Kevin Zhu for their contribution in stability model development Author would like to thank SWTW to give the opportunity to present the work Author would like to thank all audiences for the interest & questions 22