670 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE /$ IEEE

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1 670 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE 2009 Progress in Design of Improved High Dynamic Range Analog-to-Digital Converters Amol Inamdar, Sergey Rylov, Andrei Talalaevskii, Anubhav Sahu, Saad Sarwana, Dmitri E. Kirichenko, Igor V. Vernik, Timur V. Filippov, and Deepnarayan Gupta Abstract We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulationdemodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to GHz; a db signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to GHz and GHz for chips fabricated using the 4.5 and 1 ka cm 2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at GHz, the SNR is db in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 db. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 db performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 ka cm 2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is db, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 db performance enhancement. Index Terms Analog-to-digital converters, dynamic range, quarter-rate quantizer. I. INTRODUCTION SINCE its inception, significant progress has been made in the design of the delta modulator based on phase modulation-demodulation (PMD) architecture [1] [3]. These ADCs are suitable for high dynamic range radio frequency (RF) receivers. Manuscript received August 27, First published May 27, 2009; current version published July 10, This work was supported in part by the Office of Naval Research Contracts N C-0452, and N A. Inamdar, A. Talalaevskii, A. Sahu, S. Sarwana, D. E. Kirichenko, I. V. Vernik, T. V. Filippov and D. Gupta are with HYPRES, Inc., NY 10523, USA ( ainamdar@hypres.com; andrei@hypres.com; asahu@hypres.com; sarwana@hypres.com; dkir@hypres.com; ivernik@bbn.com; tfil@hypres.com; gupta@hypres.com). S. Rylov is with the IBM T. J. Watson Research Center, NY USA ( sergey.rylov@gmail.com). Digital Object Identifier /TASC [4], [5] The oversampled PMD architecture relies on high sampling frequencies for improved performance. For a given bandwidth, every doubling of the sampling frequency gives an additional 9 db in signal-to-noise ratio (SNR). As a general rule, simpler integrated circuits can be fabricated with higher yield, and operated up to higher frequencies. Both fabrication yield and maximum operating frequency diminish with increasing circuit complexity. Similarly, the front-end of the PMD delta ADC is much simpler in design ( 200 junctions) and can operate at very high sampling frequencies [4]. However, the decimation filter [6] following the ADC is more complex ( 2500 junctions), and in the conventional PMD ADC design limits the sampling frequency of the front-end. To circumvent this problem, the front-end clock needs to be decoupled from the decimation filter clock. In this paper, we discuss several multi-rate schemes that enable different clock frequencies for various circuit components. In the following sections we describe recent experimental results for the existing ADC and discuss the progress in design of the multi-rate ADC and the quarter-rate ADC. We also describe functional simulation results for the subranging ADC. II. EXPERIMENTAL RESULTS FOR PMD ADC In the PMD ADC with a single junction quantizer (SJQ), the analog signal modulates the phase of a continuous stream of fluxons, pumped at half the clock frequency. The resultant phase modulated pulse stream is demodulated by passing it through a synchronizer, which converts the pulse positions to a differential code. The oversampled differential code at the clock rate is then integrated at full speed, and averaged further, to reduce the output bandwidth and increase the effective number of bits (ENOB). A 2-channel synchronizer version of this ADC, with 16 hardware bits, was designed on a 1 chip, and fabricated using the standard HYPRES Nb process for equal to 4.5 [7] and tested in liquid helium. Fig. 1 shows the spectrum for a single 10 MHz tone, sampled at GHz, and decimated by 256. To reduce the harmonic distortion of the signal generator, this spectrum was recorded with a 10 MHz bandpass filter with about 1 MHz bandwidth, reflecting in a characteristic noise cusp in vicinity of the tone. In the Nyquist band, it shows db spurious-free dynamic range (SFDR), and 78.2 db signal-tonoise-and-distortion ratio (SINAD), translating into 12.7 effective number of bits. To take full advantage of oversampling for our ultrafast ADC, additional post-process filtering in software was employed to effectively reduce the output sampling rate and remove higher frequency components. This averaging of noise in the MHz band, /$ IEEE

2 INAMDAR et al.: DESIGN OF IMPROVED HIGH DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTERS 671 Fig. 2. Multi-rate ADC with the modulator being sampled at twice the decimation filter clock frequency. Fig. 1. FFT of a single 10 MHz input sinewave sampled at GHz and acquired at 115 MS/s. This ADC with 2-channel synchronizer is fabricated using the 4.5 ka=cm fabrication process. gives an SNR of db or ENOBs, compared to a reference 10 MHz bandwidth. III. MULTI-RATE ADC The basic idea of a multi-rate ADC is to use different clocking rates for sampling of the modulator and clocking the digital filter [3]. To provide a rate transition between different clocks, the ADC synchronizer output is demultiplexed into multiple data streams, the speed of each stream being proportionally lower than the sampling frequency. An increase of the ADC sampling frequency, and hence a 1 bit/octave performance enhancement is achieved by the increased slew-rate saturation limit. Another 0.5 bits/octave enhancement can be achieved by employing additional averaging on the demultiplexed outputs. A multi-rate ADC, where the modulator sampling frequency is double the clock frequency for the digital filter, was realized without any upgrade in the fabrication process. The synchronizer output is demultiplexed in two data streams ( Fig. 2), with the speed of each stream being half that of the sampling frequency. The demultiplexed outputs are phase shifted and processed by the 2-channel time interleaved filter [6], originally designed for use with the time- interleaved modulator. In this preliminary design, additional averaging of the demultiplexed outputs is not employed. Thus, for this particular design, we expect the performance to be same as the regular ADC with a 2-channel synchronizer, since we gain 1-bit by extending the slew-rate saturation limit, but lose 1-bit by reducing the number of synchronizer channels in half [1]. The ADC with standard front-end and 2-channel time interleaved digital filter, was designed on a 1 chip, and fabricated with the HYPRES 1 process. The FFT of a single 9.92 MHz tone, sampled at GHz, and decimated by 512, is presented in Fig. 3. It is important to note that this multi-rate ADC, fabricated with the 1 process, could be operated up to the same clock frequency as that of the regular ADC, fabricated with the 4.5 process. Since, the increased critical current density is expected to double the maximum clock frequency; the doubling of the modulator sampling frequency by the multi-rate approach can be ascertained. The SFDR in the Fig. 3. FFT result for multirate ADC with 2-channel time interleaved digital filter for single 9.92 MHz tone sampled at GHz clock acquired at 57.5 MS/s. The ADC is fabricated in 1 ka=cm fabrication process. Nyquist band is db, and the SINAD is db, translating into ENOBs. Additional averaging of noise in a reference 10 MHz band (from MHz), gives a band equivalent SNR of db or ENOBs for a 10 MHz bandwidth. A similar version of this chip was fabricated with the HYPRES 4.5 process and tested in liquid helium. The ADC could be sampled at GHz, but the performance was lower than expected. Fig. 4 shows the FFT result for this chip with a single 9.9 MHz tone. The SFDR in the Nyquist band is db and the SINAD is db. Compared to the noise in a reference 10 MHz band (from MHz), the SNR is db or ENOBs. Although the higher harmonic content on this particular test significantly reduces the SINAD and SFDR, the test results prove the ability to clock the ADC at such high frequencies. IV. QUARTER-RATE ADC A. Quarter-Rate ADC With 2-Channel Synchronizer Another approach to increase dynamic range is to increase the maximum signal that can be digitized. For a delta modulator, the largest signal amplitude is defined by the slew-rate limit of the ADC. The quarter-rate ADC employs a quarter-rate quantizer (QRQ) that provides a way to quadruple the maximum fluxon

3 672 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE 2009 Fig. 4. FFT result for multirate ADC with 2-channel time interleaved DF for single 9.9 MHz tone sampled at GHz clock acquired at 90 MS/s. The ADC is fabricated using the 4.5 ka=cm fabrication process. Fig. 5. QRQ ADC operated in half-rate mode. A 10 MHz input signal is sampled at 25.6 GHz and output samples acquired at 50 MHz. transport rate and hence the slew-rate limit of the ADC [8]. In order to leave the decimation filter clock unchanged, the QRQ divides the data on four quantizer outputs such that the data rate per output is 1/4th. The data on the four quantizer outputs are phase locked and hence a single output can be used to demodulate the input signal without any loss of information. The quadrupled also quadruples the quantization step. Assuming that the intrinsic flux noise floor remains the same as the SJQ front-end, we now can quadruple the number of synchronizer channels before we get to the noise floor. Increasing the synchronizer channels is functionally equivalent to increasing the number of quantization levels. Every doubling of the synchronizer channels gives an additional bit in SNR [1], provided the quantization step is above the noise floor. Hence, the quadrupling of the synchronizer channels in the QRQ ADC should enable a 2-bit performance enhancement. In order to better characterize the QRQ front-end and to ascertain extension of the slew-rate as compared to the SJQ ADC, we designed a preliminary version of the QRQ ADC with 2 quantizer outputs going in to a 2-channel synchronizer followed by an on-chip decimation filter. To equalize their current sensitivity, the same input transformer is used on both the ADCs. A 1 chip with the QRQ ADC was fabricated using the HYPRES 4.5 fabrication process and was tested in liquid helium. Initially the front-end was stabilized at low clock frequencies by monitoring the output from SFQ-to-DC converters connected to clock and data paths of the front-end. Moreover, data rate on some of the quantizer outputs was monitored and verified to be one fourth of the pump rate, as expected. However, it was difficult to operate the quantizer at higher clock frequencies. Hence, to simplify the operation of the quantizer, it was operated in the half-rate mode by disabling the flux bias to the top most divider, thereby forcing it to work as a divide by two circuit. Similarly, the bias to the flux pump was reduced so as to inject one fluxon per clock period, instead of the desired two fluxons per clock period for the quarter-rate operation. Disabling the top divider results in an inductive splitting of the input between the bottom two dividers. Thus, the quantizer responds in steps of two fluxons by simultaneously releasing data on the two quantizer outputs. For the next increment of two fluxons, the quantizer simultaneously releases data on the other two quantizer outputs. In this mode of operation, the slew-rate limit of the ADC is expected to be twice that of the SJQ ADC, and doubling the synchronizer channels is expected to enhance the performance by 1-bit. Fig. 5 shows the spectrum for the ADC operated in the half-rate mode, with a single-tone 10 MHz input, sampled at 25.6 GHz and decimated by 512. A 10 MHz bandpass filter with about 1 MHz bandwidth was used on the input. In the Nyquist band, the ADC shows db SFDR and a SINAD of db, translating into ENOBs. Additional averaging of noise in the 10 MHz band gives an SNR of db or ENOBs. Moreover, the maximum amplitude of the input signal is twice that of the SJQ ADC with similar transformer. The performance of the ADC is 1.1 bits lower than the SJQ ADC. One probable reason for the lower performance is that the two quantizer outputs going to the 2-channel synchronizer are not out of phase, resulting in effectively working as a single channel synchronizer. Operating the ADC in half-rate mode helped us optimize the front-end biases. After further tuning of the quantizer biases, the ADC could be operated in the quarter-rate mode. However, it could be clocked only up to 12 GHz, resulting in ENOBs in the 10 MHz bandwidth for a 10 MHz input tone. While we continue to investigate the causes of failure of the quantizer in the quarter-rate mode, we are working in parallel on designing the ADC with a multi-channel synchronizer to further enhance the ADC performance. B. Quarter-Rate Front-End With 8-Channel Synchronizer Fig. 6 shows the block diagram of the ADC with an 8-channel synchronizer. Eight replicated copies of one of the quantizer output goes to an 8-channel synchronizer, with a mutual delay of between them. A 5 mm by 5 mm chip containing the QRQ front-end with an 8-channel synchronizer was fabricated using the HYPRES 4.5 process. A low frequency test of the front-end was

4 INAMDAR et al.: DESIGN OF IMPROVED HIGH DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTERS 673 Fig. 6. Quarter-Rate ADC with 8-channel synchronizer. Fig. 8. Functional schematic of the parallel counter. Wider lines represent increasing weights in the binary code. C. Parallel Counter Fig. 7. Low frequency test results for front-end with quarter-rate quantizer and a 8-channel synchronizer. A slowly changing ramp is applied as the analog input. Whenever the analog input changes by one flux quantum the outputs change by a single bin at the next synchronizer clock. performed without the analog input signal, and with a flux pump as the input. In the absence of the analog signal, the pulse positions at the output of the phase demodulator are fixed. We correctly observed replicated outputs on all 8-channels, every alternate clock period. Data skewing amongst channels cannot be observed at low frequency. To test the front-end with a slowly changing analog input signal, the positive edge transitions from a single synchronizer channel were plotted ( Fig. 7) as a function of their bin number (modulo four of the clock count). The test procedure has been described in detail in [8]. The outputs from the synchronizer channel continue to remain in the same bin, and either advance or retard bins, in response to the analog input signal. For a slowly changing signal the transitions move in increment of a single bin. The shift in the bin position corresponds to the number of fluxons injected in the quantizer by the analog input. The multiple dots in Fig. 7 correspond to the output being in the same bin for multiple clock periods, and the transition in the bin number corresponds to additional fluxon received from the input signal. Unwrapping of the plot should enable reconstruction of the applied ramp. Each bit-slice in the decimation filter is binary weighted and is designed to accept binary inputs. Hence, a parallel counter is necessary to convert the differential code from the multi-channel ( -channel) synchronizer, each with equal weight, to a binary code. The first slice of decimation filter accepts two least significant inputs, and hence, one of the synchronizer channels is directly fed to one of these inputs. The remaining inputs are converted to a binary code. A bit routing interface assigns delays and routes weighted inputs to appropriate slices of the decimation filter. Fig. 8 shows the schematic of an 8-to-4 parallel counter that consists of a 7-to-3 binary converter and an additional synchronizer channel (Ch1) being directly fed to the decimation filter. In this pipe-lined design, full-adders are used to sum the inputs with appropriately weighted inputs being summed at every pipe and being forwarded to the next pipe for further processing. Latches are used to appropriately delay and synchronize the data at every pipe. We fabricated a 5 mm by 5 mm chip to test the 8-to-4 parallel counter. The parallel counter contains approximately 1200 junctions and occupies 2.9 mm by 0.75 mm. The chip was fabricated with the HYPRES 4.5 process, and tested in liquid helium. The low speed testing was performed using the automated test setup, called Octopux [9]. Fig. 9 shows a sequence of input codes from 1 to 8, and back from 8 to 1, and the resulting output from the parallel converter. The output S0 corresponds to Ch1 input, whereas the remaining seven inputs are converted to a 3-bit binary code. D. Quarter-Rate ADC With 8-Channel Synchronizer We have designed an ADC chip with quarter-rate quantizer, 8-channel synchronizer, 8-to-4 parallel counter, bit routing interface and multi-input digital decimation filter. Fig. 10 shows the photograph of the ADC. Passive transmission lines are used to transfer data from the parallel counter to the decimation filter. The chip contains approximately 7000 junctions and has been taped-out for fabrication.

5 674 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE 2009 Fig. 11. Subranging ADC architecture using two PMD delta ADCs. Fig. 9. Low speed test results for the 8-to-4 parallel counter. Fig. 10. Chip photograph showing the quarter-rate ADC with an 8-channel synchronizer. The 1 cm chip contains approximately 7000 junctions. To accommodate the additional length of the parallel counter between the decimation filter and the QRQ front-end with 8-channel synchronizer, we rotated the front-end relative to the decimation filter and connected using passive transmission lines. We anticipate a 2-bit performance enhancement from the ADC operated in quarter-rate mode, compared to the SJQ ADC with 2-channel synchronizer. V. SUBRANGING ADC In a subranging ADC, multiple ADCs are used to significantly enhance the dynamic range. In a subranging ADC with two ranges, the signal to be digitized is split between a coarse ADC and a fine ADC. The coarse ADC output is converted back to analog, and subtracted from the input, so as to generate a residue representing the error of the coarse ADC. The residue signal is then digitized by the fine ADC. The two ADC outputs are summed to obtain improved dynamic range. For our first implementation, we envision using the PMD delta ADCs as the coarse and fine ADC [4]. However, the thermal noise floor limitations apply to the subranging architecture as well. Hence, to enable dynamic range extension, the fine ADC needs to be sensitive enough to digitize the residue with few bits, while maintaining the least significant bit above the noise floor. Another approach, shown in Fig. 11, is to extend the top of the dynamic range. Limited by their maximum slew-rate, delta ADCs are constrained to a maximum input signal amplitude for given signal and sampling frequencies. To get extended dynamic range the subranging ADC needs to accept a signal with K times higher slew-rate than that of a single PMD ADC. This is accomplished by coupling a fraction (1/K) of the input signal to the coarse ADC while the rest is applied to the fine ADC. The 1-bit oversampled output of the coarse ADC is integrated and averaged in the decimation filter to reduce the output bandwidth and increase ENOB. The digital output is amplified by to compensate for the attenuation at its input. To extract additional bits with the subranging technique, the oversampled coarse ADC output needs to be integrated and amplified to match the full-scale input signal. In our subranging ADC, the 1-bit oversampled output of the coarse ADC is directly converted to analog, removing the requirement of multi-bit digital-to-analog conversion. However, the quantization noise present in this oversampled signal extends up to half the sampling frequency and has very high instantaneous slew rate. Therefore, the amplified coarse ADC output needs to be lowpass filtered to reject the out of band quantization noise before subtracting it from the input. The two signal inputs to the subtractor, the analog full-scale input and the integrated, amplified, and filtered coarse ADC output must be delay matched to ensure minimum residual input signal applied to the fine ADC. The coarse and fine ADC outputs are then summed to produce a higher total dynamic range. In order to estimate the performance enhancement from the subranging architecture, we performed functional simulations using Matlab Simulink. Both, subranging ADC and the single range PMD delta ADC were simulated, and their results compared to measurement results from the ADC with 2-channel synchronizer. In the subranging ADC simulation, the coarse and fine ADCs are implemented with a single channel synchronizer. Noise from various sources like jitter was not included in the simulation. Fig. 12 shows the SNR as a function of the sampling frequency. The simulated results are for a 10 MHz sinusoidal signal and the SNR is calculated in a 10 MHz bandwidth. Amplification factor of 128 is assumed. A second order analog lowpass Bessel filter with 40 MHz cutoff frequency is used to reject out-of band quantization noise. The subranging ADC shows a

6 INAMDAR et al.: DESIGN OF IMPROVED HIGH DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTERS 675 Fig. 12. Matlab simulation results for subranging ADC and the single range PMD delta ADC. Measured SNR of the PMD ADC with 2-channel synchronizer is also shown. Fig. 13. Simulated spectra for a 10 MHz sinusoidal signal sampled at GHz. Spectra for subranging and PMD ADC are shown. The signals from both ADCs fall on top of each other and cannot be differentiated. potential 23 db gain in dynamic range, compared to the PMD ADC with 2-channel synchronizer. Moreover, the SNR in the subranging ADC is 6 db lower since only 1-channel synchronizer is used. For the first order delta modulator, every doubling of the sampling frequency gives an additional 9 db in SNR for the same bandwidth. Hence, a 9 db per octave slope is shown for reference. The measured performance from the ADC with 2-channel synchronizer is about 11 db lower than the simulated performance for the given sampling frequency. The measured performance is expected to be lower since noise sources and implementation losses are not taken into account in the simulation model. Fig. 13 shows the spectrum for 10 MHz signal, sampled at GHz, and decimated by 256. The same parameters mentioned above are used for amplification and the analog low pass filter. As seen, the noise floor for the subranging ADC is significantly lower than that of the PMD delta ADC. VI. CONCLUSIONS The SJQ ADC with a 2-channel synchronizer has been operated at GHz sampling frequency and delivers db SNR in a reference 10 MHz bandwidth. We are pursuing several paths in parallel to further enhance the performance of this ADC. Preliminary results from the multi-rate ADC have been achieved and the design is being further characterized to attain the projected gain. The quarter-rate ADC with 8-channel synchronizer has been designed. The ADC is expected to enable a 12 db performance enhancement compared to the existing SJQ ADC with a 2-channel synchronizer. Matlab simulation results for subranging ADC based on two PMD delta ADCs are presented. The subranging ADC shows a potential for about 20 db performance enhancement. ACKNOWLEDGMENT The authors thank H. Engseth, A. F. Kirichenko, O. Mukhanov, and A. M. Kadin for useful discussions, and S. Tolpygo, D. Yohannes, R. Hunt, J. Vivalda, and D. Donnelly for fabricating the chips. REFERENCES [1] S. V. Rylov and R. P. Robertazzi, Superconductive high-resolution A/D converter with phase modulation and multi-channel timing arbitration, IEEE Trans. Appl. Superconduct., vol. 5, pp , [2] O. A. Mukhanov, V. K. Semenov, D. K. Brock, A. F. Kirichenko, W. Li, S. V. Rylov, J. M. Vogt, T. V. Filippov, and Y. A. Polyakov, Progress in the development of a superconductive high-resolution ADC, in Extended Abstracts ISEC 99, Berkeley, CA, pp [3] I. V. Vernik, D. E. Kirichenko, T. V. Filippov, A. Talalaevskii, A. Sahu, A. Inamdar, A. F. Kirichenko, D. Gupta, and O. A. Mukhanov, Superconducting high-resolution low-pass analog-to-digital converters, IEEE Trans. Appl. Superconduct., vol. 17, pp , June [4] A. Inamdar, D. Gupta, and T. V. Filippov et al., Superconductor analog to digital converter for SIGINT applications, in MILCOM-08, submitted for publication. [5] I. V. Vernik, D. E. Kirichenko, V. V. Dotsenko, R. Miller, R. J. Webber, P. Shevchenko, A. Talalaevskii, D. Gupta, and O. A. Mukhanov, Cryocooled wideband digital channelizing RF receiver based on low-pass ADC, Superconductor Science and Technology, vol. 20, pp. S323 S327, Oct [6] T. V. Filippov, S. V. Pflyuk, V. K. Semenov, and E. B. Wikborg, Encoders and decimation filters for superconductor oversampling ADCs, IEEE Trans. Applied Superconductivity, vol. 11, pp , March [7] The standard HYPRES, Niobium Integrated Circuit Fabrication Process The process flow and design rules are available online [Online]. Available: [8] A. Inamdar, S. Rylov, A. Sahu, S. Sarwana, and D. Gupta, Quarter-rate superconducting modulator for improved high resolution analog-todigital converter, IEEE Trans. Appl. Supercond., vol. 17, pp , June [9] D. Y. Zinoviev and Y. A. Polyakov, Octopux: An advanced automated setup for testing superconductor circuits, IEEE Trans. Appl. Superconduct., vol. 7, pp , June 1997.