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1 Homework Assignment 08 Question 1 (2 points each unless noted otherwise) 1. Sketch a two-transistor configuration using npn and pnpp BJTs that iss equivalent to a single pnpp BJT, and label the effective base, collector, and emitter. Explain in one/two sentences why such a strategy is needed: why not use a single pnp transistor? Answer: Below left are a pnpp and npn transistor pair, and below right is the equivalent pnp transistor The reason for this configuration is because it is difficult to make high-β pnp transistors. 2. In the circuit below, what is the maximum current that can flow through? Make reasonablee assumptions. Answer. Assume that for, 0.7 V. Thus, will turn on and starve from additional base current when the current through (which is alsoo the current through ) is A. 1

2 3. Consider the following drive circuit for an IR remote control. The drive signal is a 0 5 V square wave and 9 V. The IR diode is replaced with another IR diode that has a turnon voltage that is 20% lower. The new peak current through the IR diode will be a) Unchanged b) Increased by 20% c) Decreased by 20% d) Decreased much than 20%, since / Answer: (a) 4. Consider the following drive circuit for an IR remote control. The drive signal is a 0 5 V square wave and 9 V. The BJT is replaced with an NPN Darlington transistor. The new peak current through the IR diode will be a) Increased by b) Increased by c) Halved d) Doubled e) Stay the same Answer: for a Si Darlington is about double that of a normal BJT. Thus, about double the current must flow before the Darlingtonn turns on. 5. The internal circuitry of the 555 timer consists of, an R-S flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider. (a) a comparator (b) a voltage amplifier (c) two comparators (d) peak detector Answer: two comparators 2

3 6. Briefly explain why the duty cycle of the basic 555-timer astable multivibrator is always more than 50%. Answer: The timing capacitor charges through and and during this time, the output is high. The capacitor discharges through and during this time the output is low. ON time is always larger than OFF time, duty cycle is always more than 50% Question 2 Electronics engineers are often interested in the input- and output resistancee of amplifiers. Provide two reasons for this and briefly explain. Consider using a diagram. (6 points) Solution The amplifier shown has an input resistance and output resistance. The source has an internal resistancee and the load is. and are the input- and output coupling capacitors. The coupling capacitor sees a resistance and the time constant is and with corresponding bandwidth 1 2. Similarly, sees and this time-constant is with corresponding bandwidth 1 2. Thus, the input and output resistances play a role in the overall amplifier bandwidth, hence it is important to know what their values are. The second reason is that the input- and output resistances affect the overall gain. The terminal gain (the gain from the input terminal to the output terminal) is but the overall gain is. Assuming the capacitors are shorts at the operating frequency, then Clearly this is smaller than. I many cases it is advantageous to make as large as possible and as small as possible, in which case the overall gain is the same ass the terminall gain. 3

4 Question 3 The circuit shown is a current-to-vo ltage converter. The current source has an output resistance and the op-ampp has a finite open-loop gain. The amplifier is ideal otherwise. (a) Show that the amplifier input resistance is 1 (4 points) (b) If 10K, and 1,0000 determinee the range of such that the output voltage deviates from its ideal (meaning the current source is ideal) value by less than 1%. (5 points) Solution Part (a) Determine the input resistancee in the usual way add a test source, determine the resulting current and then calculate. KCL at the inverting node gives 0. However,, substituting this in the expression above gives Part (b) With 10K, and 1,000, the input resistance is 10K 1 1, Ω. A deviation of less than 1% from ideal means that less than 1% of flows through. That is, Solving yields 989 Ω. Model for current source and amplifier input 4

5 Question 4 The transistor in the amplifier shown has 350 and 0.65 V. (a) Make reasonable assumptions and show that 1 ma (3 points) (b) Show that 13.7K (5 points) (c) Estimate the lower 3-dB frequency if 1 F. You may assume that this is an STC. (4 points) (d) Estimate the voltage gain. (1 point) (e) Draw a frequency-response plot for the amplifier. Show both the phase and magnitude. (8 points) (f) Assume 0.1sin2 where 5Hz. Write an expression for. (5 points) Solution Part (a) Since is large, ignore so that V. Since 0.65 V, then V. Consequently, K ma 1 ma. Part (b) K. Using BJT scaling, 65K18K 11.3K13.68K Part (c) The coupling capacitor sees a resistance 13.68K, so the time constant is and K Hz Part (d) db. Part (e) See below. Part (f) The magnitude of the amplifier s gain at high frequencies (far from the pole, say at 1 khz) is db. Further, 5 Hz is log decades below Hz. Thus, the magnitude of the amplifier s gain at 5 Hz is db. Thus, the amplifier s gain is at 5 Hz.. The amplifier s phase, ignoring the fact that it inverts the signal, is The dc voltage at the collector is 95.6K1mA3.4 V. Finallyy sin sin V Here the negative sign shows that the amplifier inverts. 5

6 Part (e) Frequency response. An alternative and more accurate calculation is that the phase is 90 tan

7 Question 5 For the circuit shown, the op-amp is ideal except that it has an input bias current. Further, 1.2 F, 10K, and 0V when the switch is closed. At 0 the switch is opened and at 90 s, is 2 V. Determine. Considering the sign of, does flow into or out of the inverting terminal? (8 points) Solution Shown is a model that incorporates. The direction of is consistentt with its definition. Note that since the open-loop gain is infinite, the non-inverting input is at ground potential, so no current flows through. KCL at the inverting input gives is assumed to be constant and is initially uncharged so that solving forr gives Substituting the measured values gives na This current is positive indicating that the assumption that flows into the inverting input is correct. 7

8 Question 6 The figure shows a phototransistor that converts light intensity to an outputt current. The transistor must be biased as shown. Also shown are the transistor s outputt characteristics. Use an op- amp and design a current to voltage converter to produce an output voltage between 0 and 8 V for an input light intensity between 0 and 20 mw cm. 10 V power supplies are available. (10 points) Solution One possible design is shown. By op-amp action, the transistor s collectorr is at 0 V, and with the emitter at 10,, the biasing requirement for the transistor is met. Att 10 V, the transistor produces 08 ma for light intensities 0 20 mw cm. Consequently,, 1K will provide the required 0 8 V output voltage. 8

9 Question 7 Shown is the functional diagram of dual current source IC, REF200. In addition to two 100-A sources, the IC incorporates a current mirror. Below are a collection of circuits that use the IC. For each of the circuits, determine. (12 points) (a) (b) (c) (d) (e) (f) Solution (a) 50 A, (b) 400 A, (c) 50 A, (d) 1100 A (e) A (f) 300 A 9

10 Question 8 (a) For the circuit, determine,, and (8 points) (b) Determine the outputt resistance using BJT scaling (4 points) (c) What is the lower 3 db corner frequency? (6 points) 110K 82K V Solution Part (a) The Theveninn equivalent circuit for the base-emitter bias circuit iss 47K V A 1 1 ma Part (b) ms, and 3K Part (c) Using BJT impedance scaling 1 3K 4K 25Ω Part (d) Use the time-constant technique to determine the lower corner frequency. The time constant associated with the coupling capacitor is ms The lower corner frequency is then Hz 10