Time Varying Signals Chemistry 838

Transcription

1 Chemistry 838 Thomas V. Atkinson, Ph.D. Senior Academic Specialist Department of Chemistry Michigan State University East Lansing, MI Table of Contents TABLE OF CONTENTS... 1 TABLE OF TABLES... 3 TABLE OF FIGURES OSCILLOSCOPE CRT OSCILLOSCOPE SCHEMAT PROJECTION OF TWO TIME VARYING SIGNALS TIME SHARING THE BEAM LISSAJOUS PATTERNS - VARYING PHASE ANGLE LISSAJOUS PATTERNS - PHASE ANGLE MEASUREMENT LISSAJOUS FIGURES - DIFFERENT FREQUENCIES OSCILLOSCOPE (Y VERSUS TIME EXAMPLES) ASYNCHRONOUS SWEEP, WITH AND WITHOUT BLANKING SYNCHRONIZED SWEEP TRIGGERED SWEEP, SIMPLE SIGNAL TRIGGERED SWEEP, COMPLEX SIGNAL TRIGGERED SWEEP, COMPLEX SIGNAL RASTER DEVICES (TV, MONITOR) ON THE CRT TIMING EXAMPLES Black and White Black and White (Multiple Frames Example) Gray Scale Gray Scale (Multiple Frames Example) Interlaced RASTER IMAGES Black and White November 9, Version

2 Table of Contents Gray Scale Interlaced CRT MODES SUMMARY SWITCHES IDEAL AND REAL MECHANICAL SOLID STATE APPLICATIONS MULTIVIBRATORS Monostable Applications APPLICATIONS ANALOG MULTIPLEXER MEASUREMENT OF TIME AND FREQUENCY DEVICE SIGNALS DERIVATION REQUIREMENTS TIME BASE COMPUTER INTERFACE HARDWARE UNIPOLAR DAC Unipolar DAC Example (n = 4) DAC Example (n = 4 with Error in Bit 2) DAC (Bipolar) SUCCESSIVE APPROXIMATION ADC Successive Approximation ADC Example (4 Bit Linear Search) Successive Approximation ADC Example (8 Bit Binary Search) ADC Example 2 (8 Bit Binary Search) DUAL SLOPE ADC FLASH ADC (2 BIT) MEASUREMENT AND CONTROL SYSTEMS GENERAL ACQUISITION SYSTEMS (INPUT) - ANALOG EFFECT OF RESOLUTION ACQUISITION TIMING SCHEMES SIMPLE ADC OPERATOR TRIGGER SOFTWARE TRIGGER SIMPLE ADC WITH HARDWARE TRIGGER PROGRAMMABLE CLOCK PROGRAM ACCESS TO THE ADC AND A PROGRAMMABLE CLOCK DIRECT COUPLED CLOCK AND TRIGGER SAMPLE/HOLD MULTIPLEXED INPUTS LOCAL BUFFER, HARDWARE TRIGGER November 9, Version

3 Table of Tables MULTIPLE ADCS CIRCULAR BUFFERS ACQUISITION SYSTEMS - DIGITAL CONTROL OF THE EXPERIMENT, OUTPUT ANALOG DIGITAL COMPUTERIZED MEASUREMENT OF TIME AND FREQUENCY FIGURES OF MERIT FOR ACQUISITION SYSTEM COMPONENTS DAC ADC MULTIPLEXER SAMPLE AND HOLD COUNTER INSTRUMENT SYSTEMS COMMUNICATION (A BRIEF INTRODUCTION) TWO PARTICIPANTS MANY PARTICIPANTS TIME VARYING SIGNAL DETAILS VARYING DUTY CYCLE SIGNAL DETAILS SIGNAL DETAILS - ANOTHER PART OF THE SIGNAL ACQUISITION STRATEGIES SCENARIO ACQUISITION STRATEGIES SCENARIO ACQUISITION STRATEGIES SCENARIO ACQUISITION STRATEGIES BOXCAR ACQUISITION STRATEGIES RECONSTRUCTING SIGNAL FROM VARIABLE WINDOWS REVISION HISTORY Table of Tables TABLE 1 - NOMINAL SWITCH CHARACTERISTICS...26 TABLE 2 - DAC CIRCUIT PARAMETERS...41 TABLE 3 - DAC CIRCUIT PARAMETERS (II)...41 TABLE 4 - UNIPOLAR DAC EXAMPLE - TABLE OF STATES...41 TABLE 5 - DAC WITH ERROR - CIRCUIT PARAMETERS...42 TABLE 6 - DAC WITH ERROR - CIRCUIT PARAMETERS (II)...42 TABLE 7 - DAC WITH ERROR TABLE OF STATES...43 TABLE 8 - BIPOLAR DAC EXAMPLE - CIRCUIT PARAMETERS...44 TABLE 9 - BIPOLAR DAC EXAMPLE - CIRCUIT PARAMETERS (II)...44 TABLE 10 - BIPOLAR DAC EXAMPLE - TABLE OF STATES...45 TABLE 11-4-BIT SUCCESSIVE APPROXIMATION ADC...46 TABLE 12 - DUAL SLOPE ADC - SWITCH CONTROL...50 TABLE 13 - FLASH ADC - TABLE OF STATES...52 November 9, Version

4 Table of Figures TABLE 14 FREQUENCY/PERIOD/TIME/COUNT METER - INTERNAL CONNECTIONS...79 TABLE 15 - NUMBER OF LINKS IN A FULLY CONNECTED NET...87 Table of Figures FIGURE 1 - IDEAL SWITCH...26 FIGURE 2 - REAL SWITCH - 1ST ORDER MODEL...26 FIGURE 3 - GENERIC SWITCH WITH ELECTRONIC CONTROL...26 FIGURE 4 - MECHANICAL SWITCH...27 FIGURE 5 - BOUNCE EXAMPLE...28 FIGURE 6 MONOSTABLE MULTIVIBRATOR CONFIGURATION...30 FIGURE 7 - ASTABLE MULTIVIBRATOR CONFIGURATION...30 FIGURE 8 - MONOSTABLE MULTIVIBRATOR TIMING...31 FIGURE 9 - ASTABLE MULTIVIBRATOR TIMING...32 FIGURE 10 - MONOSTABLE MULTIVIBRATOR (1 SHOT) SYMBOL...33 FIGURE 11 1 SHOT - PULSE SHAPING...33 FIGURE 12 1 SHOT - PULSE STRETCHING...33 FIGURE 13 1 SHOT - PULSE SHORTENING...33 FIGURE 14 - COUPLED MONOSTABLES...33 FIGURE 15 - COUPLED 1 SHOTS - TIMING...33 FIGURE 16 - ANALOG MULTIPLEXER...34 FIGURE 17 - FREQUENCY/PERIOD MEASUREMENT...35 FIGURE 18 - FREQUENCY/PERIOD MEASUREMENT TIMING...35 FIGURE 19 - CRYSTAL STABILIZED TIME BASE...38 FIGURE 20 - GENERALIZED INTERFACE...39 FIGURE 21 - UNIPOLAR DAC...40 FIGURE 22 UNIPOLAR DAC EXAMPLE - TRANSFER FUNCTION...42 FIGURE 23 - DAC WITH ERROR - TRANSFER FUNCTION...43 FIGURE 24 - BIPOLAR DAC CONFIGURATION...44 FIGURE 25 - BIPOLAR DAC TRANSFER FUNCTION...45 FIGURE 26 SUCCESSIVE APPROXIMATION ADC...46 FIGURE 27-4-BIT ADC LINEAR SEARCH...47 FIGURE 28 - DUAL SLOPE ADC...50 FIGURE 29 - DUAL SLOPE ADC - OPERATION...51 FIGURE 30 - GENERALIZED EXPERIMENT...53 FIGURE 31 - ACQUISITION WINDOW...54 FIGURE 32 - RESOLUTION - 3 BITS...55 FIGURE 33 - RESOLUTION - 4 BITS...55 FIGURE 34 - RESOLUTION - 6 BITS...56 FIGURE 35 - EQUAL ACQUISITION INTERVALS...56 FIGURE 36 - VARIED ACQUISITION INTERVALS...56 FIGURE 37 EXPONENTIAL ACQUISITION INTERVALS...56 FIGURE 38 - MULTIPLE SIGNALS...57 FIGURE 39 - MULTIPLEXED ADC...57 FIGURE 40 - SIMPLE ADC...57 FIGURE 41 - SIMPLE ADC - TIMING ISSUES...58 FIGURE 42 - SOFTWARE TRIGGER TIMING...61 FIGURE 43 - SIMPLE ADC WITH HARDWARE TRIGGER...61 FIGURE 44 - PROGRAMMABLE CLOCK...62 FIGURE 45 ADC, REAL TIME CLOCK, AND HARDWARE TRIGGER...64 FIGURE 46 - ACQUISITION SYSTEM WITH DIRECT COUPLED CLOCK AND TRIGGER...66 FIGURE 47 - SAMPLE AND HOLD...67 FIGURE 48 - SAMPLE AND HOLD TIME COURSE...67 FIGURE 49 - SAMPLE AND HOLD AND ADC...68 FIGURE 50 - ADC, SAMPLE/HOLD, AND MULTIPLEXER...69 November 9, Version

5 Table of Figures FIGURE 51 - ACQUISITION SYSTEM WITH LOCAL BUFFER...71 FIGURE 52 - MULTIPLE ADC...73 FIGURE 53 - CIRCULAR BUFFER...73 FIGURE 54 - PRE, MID, POST TRIGGERS...73 FIGURE 55 - USING A LINEAR BUFFER AS A CIRCULAR BUFFER...75 FIGURE 56 - DIGITAL INPUT...75 FIGURE 57 - DIGITAL INPUT II...76 FIGURE 58 - SIMPLE DAC...76 FIGURE 59 - DIGITAL OUTPUT...77 FIGURE 60 - EXTERNAL FREQUENCY/PERIOD/TIME/COUNT METER...78 FIGURE 61 - INTERNAL FREQUENCY/PERIOD/TIME/COUNT METER...79 FIGURE 62 - SIMPLE COMPUTERIZED ACQUISITION SYSTEM...82 FIGURE 63 - INTELLIGENT INSTRUMENT SYSTEM...82 FIGURE 64 - DISTRIBUTED INSTRUMENT SYSTEM...83 FIGURE 65 - A VERY DISTRIBUTED INSTRUMENT SYSTEM...83 FIGURE 66 - ONE TO ONE COMMUNICATION...84 FIGURE 67 - PHYSICAL CONNECTIONS...84 FIGURE 68 ONE-TO-MANY COMMUNICATION...85 FIGURE 69 - MULTICAST...85 FIGURE 70 - BROADCAST...85 FIGURE 71 - COMMUNICATION TOPOLOGIES...86 FIGURE 72 - HIERARCHY OF STARS...87 FIGURE 73 - MIXED TOPOLOGIES...87 FIGURE 74 - HIGH DUTY CYCLE SIGNAL...88 FIGURE 75 - LOW DUTY CYCLE SIGNAL...88 FIGURE 76 - LOWER DUTY CYCLE SIGNAL...89 FIGURE 77 - LIMIT X-RANGE...89 FIGURE 78 - LIMIT X-RANGE...90 FIGURE 79 - LIMIT X AND Y RANGE...90 November 9, Version

6 Oscilloscope 1. Oscilloscope The figures in this section are from Section 3-4 and following in "Making the Right Connection" 1.1. CRT 1.2. Oscilloscope Schemat November 9, Version

7 Oscilloscope 1.3. Projection of two time varying signals November 9, Version

8 1.4. Time Sharing the Beam Oscilloscope November 9, Version

9 Oscilloscope 1.5. Lissajous Patterns - Varying Phase Angle November 9, Version

10 Oscilloscope 1.6. Lissajous Patterns - Phase Angle Measurement sin Θ = c/b November 9, Version

11 Oscilloscope 1.7. Lissajous Figures - Different Frequencies Horizontal to Vertical Frequencies a.) 1:1 b.) 2:1 c.) 1:5 d.) 10:1 e.) 5:3 November 9, Version

12 Oscilloscope (y versus Time Examples) 2. Oscilloscope (y versus Time Examples) 2.1. Asynchronous Sweep, With and Without Blanking November 9, Version

13 2.2. Synchronized Sweep Oscilloscope (y versus Time Examples) November 9, Version

14 2.3. Triggered Sweep, Simple Signal Oscilloscope (y versus Time Examples) November 9, Version

15 2.4. Triggered Sweep, Complex Signal Oscilloscope (y versus Time Examples) November 9, Version

16 2.5. Triggered Sweep, Complex Signal Raster Devices (TV, Monitor) on the CRT 3. Raster Devices (TV, Monitor) on the CRT 3.1. Timing Examples November 9, Version

17 Raster Devices (TV, Monitor) on the CRT Black and White 15 Vertical Horizontal Beam Time November 9, Version

18 Raster Devices (TV, Monitor) on the CRT Black and White (Multiple Frames Example) 15 Vertical Horizontal Beam Time November 9, Version

19 Raster Devices (TV, Monitor) on the CRT Gray Scale 15 Vertical Horizontal Beam Time November 9, Version

20 Raster Devices (TV, Monitor) on the CRT Gray Scale (Multiple Frames Example) 15 Vertical Horizontal Beam Time November 9, Version

21 Raster Devices (TV, Monitor) on the CRT Interlaced 15 Vertical Horizontal Beam Time November 9, Version

22 Raster Devices (TV, Monitor) on the CRT 3.2. Raster Images Black and White Raster8x8.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University Pixel Vertical flyback Horizontal Line Horizontal flyback Raster (8 x 8) Display Black and White November 9, Version

23 Raster Devices (TV, Monitor) on the CRT Gray Scale Raster8x8gray.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University Pixel Vertical flyback Horizontal Line Horizontal flyback Raster (8 x 8) Display Gray Scale November 9, Version

24 Raster Devices (TV, Monitor) on the CRT Interlaced Raster8x8grayinterlaced.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University Pixel Vertical flyback Horizontal Line Horizontal flyback Raster (8 x 8) Display Interlaced Gray Scale November 9, Version

25 4. CRT Modes Summary CRT Modes Summary Type Horizontal Drive Vertical Drive Beam Drive X-Y plot remote signal source remote signal source on Time base Oscope (Simplest) local sweep generator (free running) remote signal source on Time base Oscope (Simple) local sweep generator (free running) remote signal source Blanked on flyback Time base Oscope Typical) local sweep generator (Triggered) remote signal source Blanked on flyback, when armed Raster (TV, Monitor) local sweep generator local sweep generator remote source (Beam Intensity contains the visual information for a given point (pixel) in the image being displayed.) The longer the persistence, the lower the refresh rate needed to keep an image visible. The longer the persistence, the slow the motion (i.e. the changes from one frame to the next, can be. November 9, Version

26 Switches 5. Switches 5.1. Ideal and Real RealSwitch_01.cdr 11-Oct-2004 V S GenericSwitch_01.cdr 11-Oct-2004 V S Symbol R SClosed i S i S Open R SOpen Closed Figure 1 - Ideal Switch C S Figure 2 - Real Switch - 1st Order Model Table 1 shows nominal values for several of the figures of merit of switches. Any real switch also has a maximum value of V S. If a switch is subjected to voltages greater than the limit, the switch will arc and even catastrophically destruct. Another figure of merit is the maximum amount of current that can be put through the switch. Switches vary from a maximum current capacity of milliamps to many amps. Table 1 - Nominal Switch Characteristics Switch Type R SClosed R SOpen Time to Switch Ideal 0 0 Mechanical <0.1Ω >100MΩ milliseconds Solid State <200Ω >10 11 Ω microseconds Figure 3 shows two symbols for switches that can be switched between the open and closed states by electronic rather than manual means. Such devices are used often in modern instrumentation. GenericSwitch_02.cdr 11-Oct-2004 e in e out Switch Control e in Switch e out e SC e SC Figure 3 - Generic Switch with Electronic Control November 9, Version

27 5.2. Mechanical Switches Figure 4 - Mechanical Switch November 9, Version

28 Switches Bounce.cdr 30-SEP-2000 B B B T V Atkinson Department of Chemistry Michigan State University B C C C C A B t 1 t 2 t 3 t 4 A A B B B A C C C C A B t 5 t 6 t 7 t 8 A A B B B A C C C C A B t 9 t 10 t 11 t 12 A A B B B A C C C C A t 13 t 14 t 15 t 16 A A A t1 t2 Break t t Transition 3 8 t9 t16 Bounce Rigid Mechanical Single Pole Double Throw Switch Transition from one position to the other Figure 5 - Bounce Example November 9, Version

29 5.3. Solid State Switches SolidStateSwitch.cdr 30-SEP-2000 T V Atkinson Department of Chemistry Michigan State University DISC THRESH R = 1K 5V R = 1K V out Switch Switch Driver Switch open closed t 1 t 2 t 3 t 4 2.5V V out 0V t on t off Solid State Switch November 9, Version

30 5.4. Applications Multivibrators Switches Monostable.cdr 30-SEP-2000 OUT V R Close Switch Control DISC THRESH C e ref0 e C0 to Close Open Switch Driver e ref1 e C1 TRIG to Open Integrated Circuit Monostable Configuration Figure 6 Monostable Multivibrator Configuration Astablea.cdr 14-Oct-2004 OUT V R 1 Close DISC THRESH e C0 Switch Control Open Switch Driver R 2 C e ref0 e ref1 to Close e C1 TRIG to Open Integrated Circuit Figure 7 - Astable Multivibrator Configuration November 9, Version

31 Switches Monostabletime.cdr 30-SEP-2000 TRIG e ref1 Assume C is discharged at t=0 e C1 1 Limitations: a.) Long t = RC 1.) Leakage of C 2.) Noise on thresholds b.) Short t = RC 1.) Speed of comparators 2.) Speed of switch 3.) Speed of discharge 4.) Stray capacitance 2 Switch (OUT) Open Close 3 6 e ref0 5 V C 0 4 e C0 Figure 8 - Monostable Multivibrator Timing November 9, Version

32 Switches Switch (OUT) Open Close 7 Astabletime.cdr 30-SEP e ref0 V C e ref e C0 TRIG e ref1 5 e C1 Figure 9 - Astable Multivibrator Timing November 9, Version

33 Monostable Applications Switches Monostable_01.cdr 8-Oct S tr Q _ Q Monostable_02.cdr 8-Oct-2003 tr threshold R Figure 10 - Monostable Multivibrator (1 Shot) Symbol C Q Figure 11 1 Shot - Pulse Shaping tr Monostable_03.cdr 8-Oct-2003 tr Monostable_04.cdr 8-Oct-2003 Q Figure 12 1 Shot - Pulse Stretching Q Figure 13 1 Shot - Pulse Shortening Monostable_06.cdr 19-Oct S A Q Monostable_05.cdr 19-Oct-2004 B 1S Q IN Q A IN tr _ Q tr _ Q Q A R A C A R B C B t delay Figure 14 - Coupled Monostables Q B Figure 15 - Coupled 1 Shots - Timing Figure 14 illustrates one of many ways to couple more than one monostable together. Figure 15 shows the resultant timing for the configuration. Notice that every input pulse on In results in a pulse being generated on Q B that will have the leading edge delayed by t delay after the leading edge of the input pulse. Notice also that the signal on In are not periodic nor are the pulses of the November 9, Version

34 Measurement of Time and Frequency same width. The delay, t delay, and the width of the pulses on Q A and Q B are functions of R A and C A alone. The width of the pulse is a function of R B and C B alone. Collections of monostables may be constructed that produce complicated timing sequences Applications Analog Multiplexer s 3 R 3 e 3 e 2 s 2 R 2 Exam02_1.cdr e 1 s 1 R 1 s 0 R 0 R f e 0 Switch Control e out b 3 b 2 b 1 b 0 Let b i = 0 if switch S i is open. Let b i = 1 if switch S i is closed. If R f R 0 = R1 = R 2 = R 3 Figure 16 - Analog Multiplexer =, then out = { b0e0 + b1e1 + b2e2 + b3e3} = e b e. If only one switch, i.e. S k, is allowed to be closed at a time then the transfer function for Figure 16 becomes the following. e = where k can be 0, 1, 2, 3. out e k Thus, this circuit selects, based on a binary number, {b 3 b 2 b 1 b 0 }, one of a set of signals and presents the inverse of that signal at the output of the circuit. Notice that only one of the bits, b i, will be one at a time. 6. Measurement of Time and Frequency 6.1. Device The circuit shown in Figure 17 can be used to measure time and frequency. 3 i= 0 i i November 9, Version

35 Measurement of Time and Frequency FreqMeter_01.cdr 7-Oct-2003 e gi Gate e gc e go Counter Gate Control e start e stop Figure 17 - Frequency/Period Measurement The Gate Control in Figure 17 is a circuit whose output, e gc, will change state from Closed to Open upon detecting an edge (rising in the example) on e start. The output of the circuit will change from Open to Closed on the next edge of the appropriate type (rising in this example) on e stop. The output of the gate is presented to the counter. Thus, the counter will count edges (rising in this example) of the signal, e gi, coming from the gate when the gate is Open Signals An important case is that with the two inputs to the Gate Control tied together, i.e. driven by the same signal, e gcin. Figure 18 illustrates the behavior of the device when presented the two periodic signals e gi and e gcin. p gi FreqMeter_02.cdr 7-Oct-2003 e gi 1 0 e =e = gcin start e stop 1 0 p gi t Open e gc Closed t start t stop 1 e go 0 Figure 18 - Frequency/Period Measurement Timing 6.3. Derivation The following two relations are true in general. November 9, Version

36 frequency = 1 period Measurement of Time and Frequency NumberofPeriods frequency = unittime In the case of the Frequency/Period Measurement device as described here, the following will be true. In fact, the basis of all of the measurements accomplished with this device is the measurement of t. t = t t = p stop start gc If the frequencies of the two input signals are integer multiples of each other, the following is true. Such a relationship of the two signals will be assumed for the derivation. The error in the measurement of t due to this assumption is at most one period of e gi. n p = p Counts gi These can be arranged as follows. ncounts 1 = f f gi f = n gi p = n gc Counts gc Counts f gc gc p gi n = Counts f f gi gc n = Counts p p gc gi These results are the basis for the five measurement devices outlined in the table below. November 9, Version

37 Measurement of Time and Frequency gi Equation Device Conditions f = n f Frequency Meter f gc is known gc Counts Counts gc p = n p Period Meter f gc is known gi f f p p gi gc gc gi = n Frequency Ratio Meter Neither f gc nor f gi is known Counts = n Period Ratio Meter Neither f gc nor f gi is known Counts t t = n p Elapsed Time Meter f gc is known stop start Counts gi Of course, e gi and e gcin are not always integral multiples of each other. Analysis of the possibilities will show that the error in the measurement of t is one period of e gi. This translates into the error in the 5 relationships in the table being at most 1 count when the two signals are not integral multiples Requirements The following constrains are required when applying the above to measurements. 1. The Gate control signal is always the slower, i.e. f gi > f gc. Otherwise, the number of counts accumulated will only be 0 or If one of the two signals is known, you can measure the other. If neither is known, you can only determine the ratio of the two unknown frequencies or the two unknown periods. 3. There is always an error in the measurement of ±1 count. Therefore, the number of counts should be as large as possible, i.e. f gi >> f gc to minimize the error of the measurement. 4. Both e gi and e gcin are periodic, except in the case of elapsed time measurement when only e gi is periodic. 5. The accuracy and precision of the measurement is solely dependent on the accuracy and precision of the known frequency or period Time Base When measuring frequency or period, a stable, precise, accurate time base is needed as the standard or known signal. Figure 19 illustrates such a time base. The heart of the time base is an oscillator that is stabilized by a piezo electric crystal. Precisions and accuracies of parts per million and better can be achieved. In extreme cases, the temperature of the crystal will have to be stabilized. An appropriate output is chosen and connected to the Gate Input or the Gate Control. November 9, Version

38 Measurement of Time and Frequency Piezo Electric Crystal 10 MHz Osc. /10 /10 /10 /10 /10 /10 /10 /10 TimeBase.cdr 10-Oct MHz (100 nanosecond) 1 MHz (1 microsecond) 100 KHz (10 microsecond) 10 KHz (100 microsecond) 1 KHz (1 millisecond) 100 Hz (10 millisecond) 10 Hz (10 millisecond) 1 Hz (1 second) /6 / Hz (1 minute) /6 / Hz (1 hour) / Hz (1 day) / Hz (1 week) Figure 19 - Crystal Stabilized Time Base Digital clocks and watches are based on this technique with the states of the slower stages displayed on the face of the device. Typically, these digital time pieces will display months. This, of course, requires more logic to appropriately keep track of the 28, 29, 30, 31 day months and leap years. More flexible time bases will be discussed in the Programmable Clock Section. November 9, Version

39 Computer Interface Hardware 7. Computer Interface Hardware Interface0.cdr 19-Oct-2004 ADC e in D,...,D 0 n-1 Busy Convert DAC e out D,...,D 0 n-1 D In Latch Out Control Load Data D Out Latch In Control Data Ready World Computer Figure 20 - Generalized Interface The above is the generalized of interface between the computer and the outside world. All interfaces to the external world are variations of the four modes illustrated. November 9, Version

40 7.1. Unipolar DAC Computer Interface Hardware s 3 R 3 s 2 R 2 DAC.cdr e in s 1 R 1 s 0 R 0 R f Switch Control e out b 3 b 2 b 1 b 0 Figure 21 - Unipolar DAC Define the following binary variables. b i = 0 if switch S i is open b i = 1 if switch S i is closed Then the following is true e out = e R in n 1 f i= 0 bi R i If the following is true, R i = R i 2 then R eout = ein bi 2 R n 1 f i=0 i R n 1 f i Notice that e out is an analog quantity, ein is an analog quantity, and bi 2 is a binary R i=0 number. The DAC outputs a voltage that ranges from 0 to (2 n -1)* e max. The following defines e max. R f n emax = ein 2 R November 9, Version

41 or Computer Interface Hardware e in R R f = e 2 max n Thus, as the input of the DAC goes from 0 to 2 n -1, e out goes from 0 to Unipolar DAC Example (n = 4) 2 2 n n 1 e max in 2 n steps. Table 2 - DAC Circuit Parameters Table 3 - DAC Circuit Parameters (II) Parameter Value Parameter i 2 i R f /R e in -1 volt R R R R Table 4 - Unipolar DAC Example - Table of States Decimal b 0 b 1 b 2 b 3 Binary Multiplier Decimal Output November 9, Version

42 Computer Interface Hardware 4 Bit DAC Output Output Voltage (-RF*Ein*(Sum(1/Ri)) Binary Input Value Actual Output Ideal Output Figure 22 Unipolar DAC Example - Transfer Function DAC Example (n = 4 with Error in Bit 2) Table 5 - DAC with Error - Circuit Parameters Table 6 - DAC with Error - Circuit Parameters (II) Parameter Value Parameter i 2 i R f /R e in 1 volt R R R R November 9, Version

43 Computer Interface Hardware Table 7 - DAC with Error Table of States Decimal b 0 b 1 b 2 b 3 Binary Multiplier Decimal Output Bit DAC Output with Error in Bit 2 Output Voltage (-RF*Ein*(Sum(1/Ri)) Binary Input Value Actual Output Ideal Figure 23 - DAC with Error - Transfer Function November 9, Version

44 DAC (Bipolar) Computer Interface Hardware V offset R offset s 3 R 3 s 2 R 2 DAC1.cdr e in s 1 R 1 s 0 R 0 R f Switch Control e out b 3 b 2 b 1 b 0 Figure 24 - Bipolar DAC Configuration e out = ( e R in n 1 f i = 0 bi ) V R i offset R R f offset Again, assuming the following. then R i = 2 i R e out R n f = ein 1 ( R i= 0 i b 2 ) V i offset R R f offset Table 8 - Bipolar DAC Example - Circuit Parameters Table 9 - Bipolar DAC Example - Circuit Parameters (II) Parameter Value Parameter i 2 i V offset R f /R e in R R f offset -1 volt 0.5 volt R R R R November 9, Version

45 Computer Interface Hardware Table 10 - Bipolar DAC Example - Table of States Decimal b 0 b 1 b 2 b 3 Binary Multiplier Decimal Output Bit DAC Output Output Voltage (-RF*Ein*(Sum(1/Ri)) Binary Input Value Actual Output Ideal Output Figure 25 - Bipolar DAC Transfer Function November 9, Version

46 7.2. Successive Approximation ADC Computer Interface Hardware ADC0.cdr 25-Oct-2000 DAC e DAC Switch Controls Answer (n-bit) n-bit Register e In e a e< a e? b e b Number Generator/ Controller Busy Convert Figure 26 Successive Approximation ADC Successive Approximation ADC Example (4 Bit Linear Search) In this case a staircase is generated by incrementing a counter at a set rate until the generated voltage just exceeds the unknown voltage. Figure 27 is an example of how a 4 Bit ADC would operate. The bipolar 4-bit DAC from above is used to implement the 4-bit ADC. 1. Number Generator sets the counter to zero 2. Assert Convert to start process, raise Busy. 3. Number Generator adds 1 to the counter up at zero 4. If e a <e b, continue and go to Step 3, i. e. next count 5. If e a >e b, Done. Stop process, lower Busy. 6. Answer is the current contents of the n-bit Register. Table 11-4-Bit Successive Approximation ADC Signal Actual Voltage Steps required to get to answer Measured Voltage Unknown Unknown November 9, Version

47 Computer Interface Hardware 4 Bit DAC Output DAC Output (volts) DAC Input Value (Step) DAC Output Unknown 1 Unknown 2 Figure 27-4-Bit ADC Linear Search Successive Approximation ADC Example (8 Bit Binary Search) Start with MSB Turn on b n.. Is e DAC > e unk? Yes turn off b n No Leave b n turned on Turn on b n-1. Is e DAC > e unk? Yes turn off b n-1 No Leave b n-1 turned on Continue through n = 0 Parameter Value Increment Unknown 0.31 number of bits 8 November 9, Version

48 Computer Interface Hardware Step Bit Position Delta Step Trial Value Sum Bit Value trial value + Delta Step = SumStep 1 Step Binary Search ADC Voltage Step Trial Values Sum Unknown Voltage ADC Example 2 (8 Bit Binary Search) Parameter Value Increment Unknown 0.66 number of bits 8 November 9, Version

49 Computer Interface Hardware Step Bit Position Delta Step Trial Value Sum Bit Value Binary Search ADC Voltage Step Trial Values Sum Unknown Voltage November 9, Version

50 7.3. Dual Slope ADC Computer Interface Hardware s 1 R 1 s c e known e unknown s 0 R 0 C ADCDualSlope.cdr Control e integrator e comparator Figure 28 - Dual Slope ADC Table 12 - Dual Slope ADC - Switch Control Switch t 0 t integrate t discharge (t a, t b, t c ) sc closed open open s0 open closed open s1 open open closed e e e integrator integrator integrator eunknown ( tintegrate ) = tintegrate R 0 C eknown ( tintegrate ) = tdischarge R1C e = R C unknown eknown ( tintegrate ) tintegrate = tdischarge R 0 = R 1 eunknown t RC e t = unknown integrate integrate e = e unknown known 0 e = RC e t t t known discharge integrate known t discharge discharge R C 1 November 9, Version

51 Computer Interface Hardware ADCDualSlope2.cdr Equal Slopes e integrator t 0 0 t integrate t c Time 0 t b t a 1 e comparator t c 0 Time 1 t b e comparator 0 Time 1 e comparator t a 0 Time Figure 29 - Dual Slope ADC - Operation November 9, Version

52 7.4. Flash ADC (2 Bit) Computer Interface Hardware e unknown R ADCFlash.cdr OVERFLOW e 2 R e 1 b 1 R R e 0 b 0 UNDERFLOW Table 13 - Flash ADC - Table of States UNDERFLOW OVEROW e 0 e 1 e 2 b 0 b 1 e ref < e unknown ¾ e ref < e unknown < e ref ½ e ref < e unknown < ¾ e ref ¼ e ref < e unknown < ½ e ref < e unknown < ¼ e ref e unknown < November 9, Version

53 Measurement and Control Systems General 8. Measurement and Control Systems General MeasuremenControlt.cdr 1-Nov-2004 Scientist/Engineer Computer Data Store cf 2,2 c f 1,3 mf 3,3 m f 1,4 Output transducer cf 1,2 Control Measurement mf 3,2 mf 1,3 mf 1,2 Interface Input transducer c f 2,1 c f 1,1 mf 3,1 mf 2,1 mf 1,1 Physical System Figure 30 - Generalized Experiment An underlying goal of science and engineering is the understanding of physical systems. An important aspect of the search for this understanding is making observations of the physical system under study. Sometimes various aspects, e. g. temperature, pressure, of the system are controlled as the measurements are being made. Figure 30 is a generic picture of the modern experiment with both measurement and control. These observations are then used to discover the principles of behavior of the system. The measurement side of the experiment starts with a set of input transducers, m f j,1 that are placed in the system being studied. Each transducer converts a system parameter, p j, of interest, into a new quantity that is more amenable to measurement. Each transducer has a transfer function that gives the value of the output quantity as a function of the input quantity as seen below. The transducer transforms the information from one data domain to another. y (t ) f (p (t )) j i = m j,1 j i For some parameters additional transformations are made by other domain converters, m f j,k. Thus, complete data stream yields a value that is the set of nested transfer functions, which in general is the following. y (t ) = j i m f j,k ( m f j,k-1 ( m f j,1 (p (t )) ) j i November 9, Version

54 Measurement and Control Systems General where k = 1 to k, and n is the number of domain converters for this measurement stream. The following is an example for the first measurement stream of Figure 30, which has three conversions before reaching the interfaces. y (t ) 1 i = m f 1,3 ( m f 1,2 ( m f 1,1 (p (t )))) 1 i The interface performs the final domain conversion converts the quantity being measured into digital form, if this has not already happened, and gates the results into the computer to be stored or analyzed in real time. This section focuses on various hardware systems used as interfaces acquiring the quantities and recording the values for later analysis. Typically, sets of observations, i. e. measurements of the values of various parameters of the system, are made by the experimenter as the state of the system changes. Thus, the process results in a set of observations that can be represented as follows. y 1 (t 1 ), y 2 (t 1 ),, y q (t 1 ) y 1 (t 2 ), y 2 (t 2 ),, y q (t 2 ) y 1 (t n ), y 2 (t n ),, y q (t n ) In the above representation, measurements of the values, y i, of q parameters of the system are made at n different times. Time is always a dependent variable in experimentation since the measurements have to be made in real time. The times, t i, of the observations may often be correlated with some other parameter. As an example, if the observation is the intensity of the light coming out of a monochromator and the wavelength is being scanned over time, the time values can be related to the values of the wavelength. The result is a spectrum. StandardWindow.cdr 20-JUL-1997 y max y y min t min t max (x min ) ( x max ) t ( x) Figure 31 - Acquisition Window November 9, Version

55 Acquisition Systems (Input) - Analog An experiment can be thought of a series of measurements of one or more dependent variables with time as the independent variable. An acquisition window, i. e. Figure 31, describes how the data is acquired for a given dependent variable. In essence, the measurement process is the discovery of the set of grid points of the acquisition window that are the closest to the signal or parameter being measured. Of course, what actually happens is that the point nearest the physical parameter for at t min is determined and then that for the next time increment, etc. sequentially in time across the window. The goal is to optimize the window so that the signal being acquired fills the window giving the maximum resolution possible. The window is defined by the choices of the parameters t min, t max, t, y min, y max, and y. The choices are constrained by the needs of the experiment and the abilities of the acquisition system. Figure 31 shows a constant t, which is the most common strategy. Figure 35 contains an example of an acquisition using equal acquisition intervals. Figure 37 and Figure 36 suggest other, nonlinear strategies that may be desirable. The ultimate goal is to gather the most information possible about the signal of interest. More data points are desired for the portion of a signal that is changing more rapidly. The implied quantized nature of the measurements in this discussion is slanted toward the use of Analog to Digital Converters to make the measurements. However, the use of analog oscilloscope, analog recorders, and manual recording to acquire a set of data is analogous. In those cases the t and y are the horizontal and vertical resolutions of the analog device. The best results occur for these devices when the signal being measured fills the oscilloscope display, the width of the recorder, etc. That is, the best results are when the signal fills the acquisition window. Another important consideration is the specification of t min. Typically, the acquisition a signal is to begin at a particular time. Identifying that the time, i.e. the trigger event, has occurred must cause the acquisition to begin. 9. Acquisition Systems (Input) - Analog 9.1. Effect of Resolution Analog Analog Amplitude (Decimal) Digitized Amplitude (Binary) Amplitude (Analog) Digitized Amplitude (Binary) Time Time 0000 Figure 32 - Resolution - 3 Bits Figure 33 - Resolution - 4 Bits November 9, Version

56 Acquisition Systems (Input) - Analog Amplitude (Analog) Analog Digitized Amplitude (Binary) Time Figure 34 - Resolution - 6 Bits Acquisition Timing Schemes Signal Timebase Signal 8 8 Timebase Amplitude 6 4 Amplitude Time Time Figure 35 - Equal Acquisition Intervals Figure 36 - Varied Acquisition Intervals 10 8 Signal Timebase 6 Amplitude Time Figure 37 Exponential Acquisition Intervals Figure 38 illustrates a frequent need to acquire more than one signal at a time. A common approach is to use a multiplexed ADC which results the timing shown in Figure 39. November 9, Version

57 Acquisition Systems (Input) - Analog 10 MultiplexADC.cdr 20-JUL t k t k+1 t k+2 8 Signal Timebase Signal 2 y k z k+1 y(t) Amplitude z k yk+1 y k+2 z k+2 z(t) t acq -1 t Data Time Figure 38 - Multiple Signals Figure 39 - Multiplexed ADC 9.3. Simple ADC This and the following sections will examine a number of approaches to implementing a computer interfaced acquisition system that will allow the acquisition of a set of points which represent the amplitude of one or more analog signals as a function of time. ADC1.cdr 7-Oct-1995 e In In ADC d n-1,..., d0 Busy Convert Data CSR Interface to I/O Bus World Computer Figure 40 - Simple ADC This simple system requires a program executing on the computer to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system. 1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion. 2. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 3. Read the CSR and observe the value of the Busy bit. November 9, Version

58 Acquisition Systems (Input) - Analog 4. If the Busy bit is 1, go to Step 3. If the Busy bit is 0, the conversion is finished, proceed to the next step. 5. Read the Data Register to get the converted point. 6. Store the point 7. Do the bookkeeping to see if more data points are to be taken, and where the next data point is to be stored. 8. If more points are required, go to Step 1. If done, stop. Two problems exist with this approach. First, how does the system know when to start the acquisition process, i.e. what is the trigger event and how does the program know when it has occurred? Second, what is the time base for the set of data points, i.e. what are the values of x i associated with each data point, y i, acquired? Acquision_01.cdr 20-Oct-2004 t acq2 Busy t 1 t 1 Convert Program Step 1 Step 2 Step 3 Step 4 Step 3 Step 4 Step 3 Step 4 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 1 Step 2 Step 3 Step 4 t a t b t b t b t b t a t b t acq1 Busy t 1 t 1 Convert Program Step 1 Step 2 Step 3 Step 4 Step 3 Step 4 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 1 Step 2 Step 3 Step 4 t a t b t b t b t a t b Figure 41 - Simple ADC - Timing Issues Figure 41 shows two possible scenarios for the acquisition of two points with the system described here. The time base is controlled by the conversion time of the ADC and the time required by the program to execute the indicated steps. The times, t 1, represent the delay required for the ADC to respond to the command to convert and raise the Busy flag. The times labeled t a are the times during the execution of Step 1 at which the 1 is actually written out to the November 9, Version

59 Acquisition Systems (Input) - Analog ADC. The times labeled t b are the times during the execution of Step 3 at which the value of the Busy flag is actually latched into the interface. The time between any two data points, t acq, will be the sum of the following times. Time required to perform Steps 1. (Get the ADC to start the conversion.) The conversion time of the ADC Time required to perform Steps 3-4. (Sense the fact that the Busy flag has gone down.) Time required to perform Steps 5-8. (Deal with the current point and do the attendant bookkeeping.) First, these times will vary from computer system to computer system since the instruction timings differ from computer model to model. Second, the number of times Steps 3-4 will be executed may differ from data point to data point. Since the ADC is not synchronized with the computer, the Busy flag might go down before or after the time, t b, when the value is actually captured by the nearest Step 3 in time. If the falling edge of the Busy flag comes after the time t b, then the program makes an extra trip through the loop consisting of Step 3 and Step 4. This leads to the difference in acquisition times, t acq, seen in Figure 41. Another problematic issue is choosing a nominal acquisition interval, the time between data points. As written the time between points is what ever the instruction timing dictates plus the uncertainty due to varying number of execution of Steps 3 and 4. Other choices can be achieved by introducing time killing instructions between Step 7 and Step 8, but this is cumbersome and imprecise. Finally, at the end of Step 9, the program stops with the results of the acquisition stored in the memory of the computer. Either the memory would then have to be manually examined and the values manually recorded externally, or a program written that would read the acquired data and store it in a file on a disk, or print the values out on a printer or plot the values on a plotter. Fortunately, modern operating systems provide programming that would do much of this work for you. This problem of what to do with the data once acquired will not be addressed in this document Operator Trigger The simplest way to trigger an acquisition sequence is for the operator to wait to start the program until the desired point in time. This will work if the signal being acquired is very slow and the start time need not be very precise. The reaction time of the operator, the time needed for the program to start, plus any initialization steps in the program, (There are none in the above example.) will contribute to the uncertainty of the time of the first data point Software Trigger A second way to control the start of the acquisition is to have the software look for a trigger event on the signal being acquired. As an example, the following simple mechanism looks for a trigger event consisting of the first occurrence after launching the program of the signal making a transition through a threshold in the positive direction. Assume that a storage location called Threshold has been defined in the program and has been preloaded with the value of the threshold. [Wait until the signal goes below the threshold before arming the trigger mechanism.] November 9, Version

60 Acquisition Systems (Input) - Analog 1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion and raise the Busy flag. 2. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 3. Read the CSR and observe the value of the Busy bit. 4. If the Busy bit is 1, go to Step 3. If the Busy bit is 0, the conversion is finished, proceed to the next step. 5. Read the Data Register to get the converted point. 6. Compare the new value with Threshold? 7. If the new value is greater than the value in Threshold, go to Step 1. If the new value is less than the value in Threshold, the trigger mechanism is now armed, proceed to the next step. [Signal is now below the threshold. Get a new value and look for the next transition through the threshold.] 8. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion. 9. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 10. Read the CSR and observe the value of the Busy bit. 11. If the Busy bit is 1, go to Step 10. If the Busy bit is 0, the conversion is finished, proceed to the next step. 12. Read the Data Register to get the converted point. 13. Is the new value greater than or equal to the value stored in Threshold? 14. If no, go to Step 8. If yes, the trigger event has occurred, proceed with the acquisition of the dataset. This approach assumes, as with the triggering of an analog oscilloscope, that there is a slope and threshold that would define an unambiguous trigger event and that this trigger event would not occur until after the program has started. Figure 42 illustrates the timing of such an approach. The software is continually acquiring data points with an acquisition interval, t acq. The software trigger is armed after the transition through the value stored in Threshold, which is detected with the data point acquired at time t 1. The trigger event occurs at time t 2. However, the fact that the trigger event has occurred is not detected until the data point is acquired at time t 3. November 9, Version

61 Acquisition Systems (Input) - Analog t 1 t 2 t 3 Acquision_02.cdr 20-Oct-2004 Signal y Threshold Data Point t acq Time Figure 42 - Software Trigger Timing This approach could work for relatively slow signals Simple ADC with Hardware Trigger Another way to address the problem of when to begin the acquisition is to implement a hardware trigger mechanism as indicated in Figure 43. The trigger senses when the input signal, e trigger, crosses the threshold, e threshold in the direction specified by the Slope, e Slope. ADC1.cdr 14-Oct-2004 e In In ADC d n-1,..., d0 Busy Convert Data CSR Interface to I/O Bus World Computer e trigger e threshold e slope In Trigger Trigger Arm CSR Interface to I/O Bus Figure 43 - Simple ADC with Hardware Trigger Again, a program is required to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system. 1. Write a 1 into the Arm bit in the Trigger CSR. 2. Read the Trigger CSR and observe the value of the Trigger bit. 3. If the Trigger bit is 0, go to Step 2. If the Trigger bit is 1, a trigger event has occurred, proceed to the next step. November 9, Version

62 Acquisition Systems (Input) - Analog 4. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion and raise the Busy flag. 5. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 6. Read the ADC CSR and observe the value of the Busy bit. 7. If the Busy bit is 1, go to Step 6. If the Busy bit is 0, the conversion is finished, proceed to the next step. 8. Read the ADC Data Register to get the converted point. 9. Store the point 10. Do the bookkeeping to see if more data points are to be taken and where the next data point is to be stored. 11. If more points are required, go to Step 1. If done, stop. [As written this program would take one data point per trigger. If the trigger is to signal that a set of points are to be acquired, the branch at this point would be to Step 4 instead.] This system addresses the problem of when to begin the process, i.e. an external trigger event will start the process. However, there will be some uncertainty in the timing of when the process begins. As with the Busy flag problem of the previous example, the number of instructions in the program that are executed between the time of the trigger event and when the program has sensed that the trigger event has occurred can vary from one run to the next. This approach does not address the time base challenge described above Programmable Clock Not Shown: Control signals for strobing information into registers. ProgClk1.cdr 1-Nov MHz Osc. /10 /10 /10 /10 /10 /10 /10 10 MHz 1 MHz 100 KHz 1 KHz 1 KHz 100 Hz 10 Hz 1 Hz Multiplexer (Switch) Selected Frequency A 2 A 1 A 0 Gate Enable Count Counter (n-bits) Enable Oveflow Gate Set Q Flip Flop Clear Clear Latched Clock Out Latched Clock Out Clock Out Freq Reg CSR Preload Reg (n-bits) Counter Reg (n-bits) CSR I/O Bus Interface Figure 44 - Programmable Clock November 9, Version