A 2 Gbit/s 0.18 µm CMOS Front-End Amplifier. Integrated Differential Photodiodes

Transcription

1 Gbit/s 0.18 µm CMOS Front-End mplifier for Integrated Differential Photodiodes Markus Grözing, Michael Jutzi, Winfried Nanz, and Manfred Berroth 1 Prof. Dr.-Ing. Manfred Berroth

2 OULINE Motivation Differential CMOS Photodiode mplifier Chain Design opology & PD Bias Noise Optimization Experimental results Conclusion

3 MOIVION: Optical Interconnects Wide rea Network Fibre Cable (SM) Metropolitan rea Network Local rea Network Fibre Cable (MM) Rack-to-Rack Card-to-Card (Backplane) Waveguides on PCB Chip-to-Chip (PCB / MCM) CMOS ransmitter Chip ransmit Module / Laser Diode Waveguide Photodiode on CMOS Receiver Chip withinchip Waveguides on Chip? 3

4 Differential Photodiode: Principle & Layout light metal shading mask K illuminated K shaded K i K s SCR n+ p+ n+ n-well SCR n-well fast drift p-substrate 100 µm slow diffusion node 4

5 Differential Photodiode: ime Domain Response Voltage measured at 50 Ω [mv] Illuminated Signal Shaded Signal Differential Signal V PD V λ 850 nm R Bit 1.5 Gbit/s time [ns] 5

6 Differential Photodiode: Equivalent Circuit K i K s V PD V C Dis λ 850 nm C Di C Ds I illuminated node (0 V) I shaded Responsitivity Bandwidth Capacitances I PD,DM I illuminated I shaded 0 m/w B PD,DM > 1 GHz C Di C Ds 00 ff I PD,CM ½ (I illuminated + I shaded ) 40 m/w B PD,CM 30 MHz C Dis 50 ff 6

7 mplifier Chain Design Design goals: large sensitivity + C R Ω Gbit/s operation R 50 Ω C Fiber Diff. PD 1. reverse photodiode bias: > Vfor R bit Gbit/s operation. 3-dB bandwidth of amplifier chain: f 3dB 0.7 R bit 1.4 GHz 3. maximized electrical sensitivity of the amplifier chain: minimized input referred noise large gain of the amplifier chain. LI Driver 7

8 V RL V RL 0.8 V V R,max 0.3 V mplifier Stage opology V DD V DD 3.3 V R R.7 kω R R L 1 kω R L R L nd stage N-well isolation V ail I ref V PD,min V PD. V 1 st stage I stage 1.65 I stage m differential photodiode 0 V basic differential amplifier stage thick oxide current mirror V DSmax V GSmax x V RL + V DSon ( x ) V 1.8 V 8

9 Noise Equivalent Circuit R V in V o1 V o I photo C in g m1 V in I Dn1 R L1 V o1 Photo- Diode 1 st Stage nd Stage 1 st MOSFE differential pair thermal channel noise current main noise source: ~ 75 % of total integrated output noise ransimpedance resistor R : only ~ 10 % of total integrated output noise 9

10 Output Signal-to-Noise-Ratio Optimization Vo,photo( ω) Z( ω) SNRo( ω) V V o,noise I photo o,noise Z V o,photo I photo R jωc in R + 1 ω 3dB,Z C in + 1 R SNR V o,noise o g m1 4kγ R I photo ( ωc R ) in jωc jωc in in R R + 1 4kγ g m1 I Dn1 ω 3dB,SNR 4kγg C 1 R in m1 g µ m1 n C ox W ' L 1 I 0 ~ W 1 Enlarge W 1 10

11 mplifier Chain Design MOSFE Width [µm] Stage Current [m] I Noise 1 µ C 1.7 R Ω R 50 Ω C Fiber Diff. PD I PD,DM 0 µ/mw BW > 1.0 GHz LI Driver V 9 db R rans.9 kω BW 1.8 GHz V 43 db BW 1.7 GHz V Swing 15 mv (single ended) 11

12 Optical Receiver Layout ransimpedance mplifier Photo Diode 50 Ω- Driver Limiting mplifier 1

13 Measured Eye Diagrams (PRBS 31-1) R bit 500 Mbit/s R bit 1.5 Gbit/s BER 0 (10-11 ) BER 0 (10-11 ) R bit.0 Gbit/s R bit.5 Gbit/s BER 0 (10-11 ) BER

14 Bit Error Rate versus Incident Optical Power Mbit/s 1.5 Gbit/s Gbit/s PRBS 31-1 bit error rate spamod4_v optical λ850 nm [dbm] 14

15 Conclusion fast photodiode on unmodified CMOS receiver sensitivity enhanced by optimized amplifier chain design no equalization filter necessary easy speed / sensitivity trade-off 15