A 2Gbps Optical Receiver with Integrated Photodiode in 90nm CMOS. Alain Rousson

Transcription

1 A 2Gbps Optical Receiver with Integrated Photodiode in 90nm CMOS by Alain Rousson A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto c Copyright by Alain Rousson 2011

2 A 2Gbps Optical Receiver with Integrated Photodiode in 90nm CMOS Alain Rousson Master of Applied Science, 2011 Graduate Department of Electrical and Computer Engineering University of Toronto Abstract The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-sml photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13µm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm 2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW. ii

3 Acknowledgments I would like to sincerely thank my supervisor, Professor Tony Chan Carusone. His guidance, and in particular, his patience, made writing this thesis enjoyable. He also provided the resources to acquire the necessary equipement to perform optical testing here at the University of Toronto. Thank you to Professor Glenn Gulak, Professor Sorin Voinigescu, and Professor Olivier Trescases for serving on my thesis examination committee. Thanks to CMC for providing access to the TSMC 90nm CMOS technology node. Thanks to Jaro Pristupa for providing CAD support. Thanks to the guys at FIB-X for helping me get the chip up and running. I d also like to thank my colleagues: Kentaro for his help in the lab and all of the students in BA5000 for making BA5000 such a fun place to work. Finally, a great big high-five goes to Janessa. iii

4 Contents List of Figures List of Tables vi ix 1 Introduction Motivation State of the Art Objective Thesis Organization Background Photodiode Photodiode Physics Photodiode Model Photodiode Simulation State of the Art (extended) and Proposed Solution Analog Equalizer to Extend the System Bandwidth Decision Feedback Equalizer to Remove ISI Proposed Solution High-Pass Filter and Hysteresis Latch High-Pass Filter Equalizer Hysteresis Latch Model System Simulation Circuit/System Design and Simulation System Description Circuit Description Technology Simulation Corners Transimpedance Amplifier High-Pass Filter Linear Amplifier Hysteresis Latch Output Buffer Complete Receiver Simulation Results Layout and Measurements 35 iv

5 Contents 4.1 Circuit Layout Photodiode Layout Chip Layout Measurements Electrical Test Photodiode Responsivity Test Optical Test Conclusion Summary Future Work Layout Considerations 58 References 61 v

6 List of Figures 1.1 Optical receiver for long distance communications [1] Cross section of a photodiode in a modified SiGe process [2] Cross section of an unmodified photodiode that uses avalanche operation [3] Cross section of SML photodiode [4] Optical receiver using equalization to extend the system bandwidth [5] Cross section of CMOS photodiode Photodiode current response (a) Photodiode response to -5dBm 5Gbps PRBS13 (b) Input signal Block diagram of receiver using an analog equalizer [6] Block diagram of receiver using a IIR DFE [7] Frequency response of proposed solution High pass filter equalizer model (a) High-pass filter response (b) Step response High-pass filter equalizer with hysteresis latch The input to the photodiode model is a 5Gbps PRBS13 signal (a) Output of the hysteresis latch (b) Hysteresis latch eye diagram (c) Equalizer output (d) Equalizer output eye diagram (e) Photodiode output (f) Photodiode output eye diagram Receiver block diagram TIA block diagram TIA core amplifier schematic TIA bandwidth High-pass filter schematic Eye diagram after the high-pass filter; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into the photodiode. The simulation covers 10000UIs Block diagram of offset compensation Linear amplifier schematic for one stage Linear amplifier input schematic for offset compensation Linear amplifier frequency response Eye diagram after the linear amplifiers; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into the photodiode. The simulation covers 10000UIs Block diagram of the hysteresis latch [8] vi

7 List of Figures 3.13 Hysteresis latch schematic Threshold adjustments by changing I tail Eye diagram after the hysteresis latch; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into photodiode. The simulation covers 10000UIs Output buffer schematic Output buffer frequency response Eye diagram after the output buffer; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into photodiode. The simulation covers 10000UIs Annotated photo of the photodiode n-well/p-substrate photodiode. It is 72µm 78µm. The n-well is connected to metal 2, while the p- substrate is connected to metal Photo of bare die Photo of the die after the ablation of the aluminium over the photodiodes Close-up photos of the photodiode (a) The photodiode after original manufacturing is covered by aluminium. (b) The photodiode after the ablation of the aluminium Photo of the PCB used to test the chip Test setup for electrical testing Eye diagrams with an electrical PRBS7 input to the board of 200mV pp (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps Eye diagrams with an electrical PRBS31 input to the board of 300mV pp (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps Test setup for photodiode responsivity testing Photodiode responsivity test structure Test setup for the optical testing Photo of the test setup Photo of the optical probe coupling to the integrated photodiode Eye diagrams with an average input power of -3.0dBm at 2.5Gbps (a) Archcom Technology AC6538 (b) NewFocus 1554-A Eye diagrams with an average input power of -1.9dBm and extinction ratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip Eye diagrams with an optical PRBS7 input with an average input power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps Eye diagrams with an optical PRBS31 input with an average input power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps BER vs. average optical input for a constant 9dBm extinction ratio and a 1.2V supply (a) PRBS7 input (b) PRBS31 input vii

8 List of Figures 4.19 Eye diagrams with an optical PRBS7 input with an average input power of -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps Eye diagrams with an optical PRBS31 input with an average input power of -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps BER vs. average optical input for a constant 9dBm extinction ratio and a 1.3V supply (a) PRBS7 input (b) Pseudo-Random Bit Sequence (PRBS)31 input Spice simulation output of the linear amplifier, with the plot on the left having a PRBS7 input, and the plot on the right having PRBS31 input. The blue lines represent a possible threshold value Eye diagram after the output buffer with revised photodiode model, 4.25Gbps PRBS7-4dBm average power and 8.5dB extinction ratio input into photodiode. The supply voltage is 1.2V and the simulation temperature is 27 o C (a) TT simulation corner (b) SS simulation corner. 54 viii

9 List of Tables 3.1 Simulation corner parameters Comparison of TIA design parameters with [4] and [7] TIA simulation summary TIA monte-carlo simulation summary Linear amplifier simulation summary Power consumption breakdown by voltage rail, which are both set to 1.2V Measurement results for optical testing. The chip is built in a standard 90nm CMOS. The wavelength used is 850nm. The simulation results are for a 1.2V supply voltage with a temperature of 27 o C. The extracted simulation are for 1000UIs. It is not possible to infer the optical sensitivity from that length of simulation Comparison of non-sml optical receivers Comparison of most recently published optical receivers ix

10 List of Acronyms BER Bit Error Rate BERT Bit Error Rate Tester BiCMOS Bipolar Complementary Metal-Oxide-Semiconductor CMOS Complementary Metal-Oxide-Semiconductor DFE Decision Feedback Equalizer ESD Electrostatic Discharge FIB Focused Ion Beam FPGA Field-Programmable Gate Array IC Integrated Circuit IIR Infinite Impulse Response ILO Injection Locking Oscillator ISI Inter-Symbol Interference LAN Local-Area Network LED Light Emitting Diode MOSFET Metal-Oxide-Semiconductor Field Effect Transistor OEIC Optoelectronic Integrated Circuit NRZ Non-Return-to-Zero PCB Printed Circuit Board PRBS Pseudo-Random Bit Sequence QFN Quad Flat No leads RGC Regulated-Cascode SML Spatially Modulated Light x

11 List of Acronyms SOI Silicon-on-Insulator TIA Transimpedance Amplifier TSMC Taiwan Semiconductor Manufacturing Company UI Unit Interval VCSEL Vertical-Cavity Surface-Emitting Laser VGA Variable Gain Amplifier xi

12 1 Introduction 1.1 Motivation Fiber-optic interconnects have replaced electrical interconnects in long-distance data communication. The receivers for these optical links are implemented on multiple die as shown in Figure 1.1 [1], and on expensive technologies, such as GaAs [9], or InP-InGaAs [10]. These solutions are relatively cost-insensitive due to the large number of users per channel. For short-reach optical connections such as Local-Area Network (LAN), board-to-board or chip-to-chip interconnects, there is only one user per channel, meaning the system cost must be low. Short-reach optical links offer advantages over electrical interconnects, since they are immune to crosstalk or other electrical conductor affects that negatively impact performance [1]. The need for a low cost system puts certain limits on the system design, as low-cost fibers and lasers are needed. Single-mode fibers are relatively inexpensive, however, multi-mode fibers have relaxed alignment tolerances and a smaller bend radius, reducing the complexity of connectors and installation costs. The diameter of a multi-mode fiber is approximately 50µm, therefore the photodiode area must be at least 50µm in diameter [5]. Vertical-Cavity Surface-Emitting Lasers (VCSELs) that operate at wavelengths of 850nm are the lowest cost lasers available, and are easy to test and Figure 1.1: Optical receiver for long distance communications [1]. 1

13 1 Introduction mass-produce. Furthermore, silicon can absorb 850nm light. A receiver implemented entirely in a standard Complementary Metal-Oxide-Semiconductor (CMOS) process offers a very low manufacturing cost. Moreover, it is a single-chip solution, which presents further advantages, such as eliminating ground-bounce issues, Electrostatic Discharge (ESD) problems, and bond-wires [5]. The problem with optical receivers in CMOS technology is the low speed of silicon photodiodes. The photodiode is built as a reverse bias PN junction, which creates a depletion region that is used to collect the electron-hole pairs created when incident photons are absorbed. However, the penetration depth of 850nm light is far greater than the width of the depletion region, resulting in carriers generated deep in the silicon that must diffuse to the depletion layer. This limits the bit-rate to tens of Mbps [11]. Furthermore, smaller technology nodes operate at lower voltages with higher doping levels, resulting in a smaller depletion region, which leads to smaller photodiode intrinsic bandwidth, and photodiode responsivity [1][4]. However, it is desirable to implement the optical receivers in nanoscale technologies where they can be integrated alongside large amounts of digital logic. 1.2 State of the Art Several methods were investigated to remove slow diffusing current in order to increase the speed of the photodiode in CMOS Optoelectronic Integrated Circuits (OEICs). Photodiodes built in modified Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) [2][12] technology have better performance than their unmodified CMOS counterparts. Figure 1.2 shows the cross section of a modified photodiode. The buried N + layer is 10µm deep, creating a deep depletion region, resulting in a high quantum efficiency. Furthermore, the N + /p-substrate junction shields the photodiode from any slow diffusion currents generated in the p-substrate. The bandwidth of the photodiode reported in [2] was 2.2GHz. The problem with this solution is that it is expensive. Another method is to increase the width of the depletion layer by using high reverse bias voltages permitting avalanche operation [13][3]. Figure 1.3 shows the cross section of an PIN photodiode fabricated in an unmodified CMOS process. The slow diffusion currents generated in the p-substrate are still shielded by the deep n-well/p-substrate junction, however, to completely deplete the p- layer, a voltage that is significantly 2

14 1 Introduction Figure 1.2: Cross section of a photodiode in a modified SiGe process [2]. Figure 1.3: Cross section of an unmodified photodiode that uses avalanche operation [3]. higher than the nominal supply voltage is required. This voltage can lead to reliability issues, and can cause the system to be more complicated and expensive. In [3], a 6V reverse bias voltage is required to to operate the receiver at 2.5Gbps. A 2V reverse bias voltage limits the operation to 622Mbps. Receivers also use a Spatially Modulated Light (SML) photodiode to increase the photodiode intrinsic bandwidth [4][14][15]. Figure 1.4 shows a cross section of an SML photodiode. An SML photodiode consists of uncovered photodiodes interleaved with covered photodiodes. The covered photodiodes do not generate any drift current in their depletion region. Diffusion currents generated deep in the substrate are collected by both covered and uncovered diode connections. When the current collected by both diodes are subtracted from each other, the diffusion currents are eliminated, leaving only the drift current. This increases the bandwidth. Unfortunately, SML photodetectors have a lower responsivity than a standard photodiode [1], since some of the current is subtracted, and since the photodiode is more than 50% covered by metal. Finally, equalization is frequently used to extend the data rate. The concept is illustrated in Figure 1.5. In [4][5][16][17][18], a high-pass analog equalizer is used to 3

15 1 Introduction Figure 1.4: Cross section of SML photodiode [4]. Figure 1.5: Optical receiver using equalization to extend the system bandwidth [5]. extend the system bandwidth, while in [7], an Infinite Impulse Response (IIR) Decision Feedback Equalizer (DFE) is used to remove Inter-Symbol Interference (ISI). A popular and promising approach is to combine an SML photodetector with equalization, as seen in [4][16][17][18]. Since an SML photodiode has a larger bandwidth, only modest equalization is required. The highest data rate reported in a monolithically integrated CMOS optical receiver is 8.5Gbps at a sensitivity of -3.2dBm with a Bit Error Rate (BER) of and 47mW power consumption [18]. The receiver uses a Regulated-Cascode (RGC) Transimpedance Amplifier (TIA) to extend the TIA bandwidth, however, this architecture also increases the total input-referred noise, thus decreasing the receiver sensitivity. In [19], a receiver with a 5.5Gbps data rate at a sensitivity of -3.4dBm with a BER of and 58.5mW power consumption is reported, using a standard shunt-feedback TIA. 4

16 1 Introduction 1.3 Objective The objective of this work is to enable parallel optical receivers integrated with digital logic in standard nanoscale CMOS. To accomplish this goal, the photodiode is integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage is not exceeded. This is the first receiver built in a CMOS technology that is smaller than 0.13µm, other than the work published in [1]. The receiver in [1] is built in 65nm CMOS, and integrates photodiodes connected to TIA and a 50Ω output buffer to drive test equipment, but doesn t consist of a complete optical receiver. The work characterizes the intrinsic bandwidth and responsivity of different photodiode structures. In smaller feature-size CMOS processes, the lower supply voltage and smaller device dimensions lead to a smaller depletion region. For the same incident wavelength, the proportion of light captured in the depletion region compared to deep in the substrate decreases, which decreases the intrinsic bandwidth of the photodiode [1][5]. This explains why there are no other receivers in technologies smaller than 0.13µm. The most exciting applications for this type of receiver are when it is integrated alongside CMOS logic, which today are all in nanoscale technologies. In fact, Altera has announced that they will integrate optical transceivers onto their Field- Programmable Gate Arrays (FPGAs) to increase their bandwidth, and reduce the system cost and power [20]. To allow parallel optical receivers on the same chip, there are two lanes integrated with a pitch compatible with existing industry photodiode arrays. The photodiode integrated with the receiver is a non-sml photodiode, since SML photodiodes block over 50% of the light. Since a non-sml photodiode has severe bandwidth limitations, linear equalization will be difficult. To perform the equalization, the receiver will use pulse-signalling and a hysteresis latch. 1.4 Thesis Organization Chapter 2 provides background information on CMOS photodiodes and simulation results for the proposed system. In Chapter 3, the transistor-level design and simulation results for each individual block in the system are shown. Chapter 4 discusses the layout and the measurement results. Chapter 5 concludes the thesis and suggests future research. 5

17 2 Background This chapter provides background information on CMOS photodiodes in Section 2.1. Section 2.2 revisits the receivers found in literature, and introduces the proposed receiver architecture. Section 2.3 covers the proposed receiver in more detail, while Section 2.4 provides system-level simulation results. 2.1 Photodiode Photodiodes convert optical energy into electrical energy using the optical absorption process, which is covered in more detail in [21]. This chapter will summarize the information needed to understand photodiode operation. The model and simulation results are for a silicon CMOS photodiode, as this is the most inexpensive semiconductor used in electronics. The photodiode model parameters of other popular semiconductors can be found in [21] Photodiode Physics Light sources (Light Emitting Diodes (LEDs), lasers) are described by the vacuum wavelength λ 0 since it is independent of the medium. Photons have a fixed energy E E = hυ = hc λ = hc 0 λ 0. (2.1) where υ is photon frequency, c is the photon velocity and λ is the photon wavelength. The bandgap energy of the semiconductor material is denoted as E g. When a photon collides with an electron in the semiconductor valence band, it transfers its energy if that energy is greater than the bandgap energy of the semiconductor (E > E g ). The photon is absorbed, generating an electron-hole pair. The semiconductor is transparent to light with wavelengths longer than λ c = hc 0 /E g. For silicon E g = 1.1eV, and the longest wavelength that can be absorbed is λ c = 1110nm. 6

18 2 Background Cathode Light n+ p+ Anode n-well p-substrate Figure 2.1: Cross section of CMOS photodiode. The optical absorption coefficient α of a semiconductor determines the penetration depth 1/α, according to Lambert-Beer s Law Φ( x) = Φ 0 e α x. (2.2) Φ( x) is the light flux at depth x into the semiconductor. The absorption coefficients of silicon for a 850nm wavelength is 0.06µm 1. Photons absorbed in the semiconductor depletion region will cause carrier drift, since there is an electric field present. Photons absorbed below and above the depletion region will create minority carrier diffusion, which is much slower than carrier drift. For light with a wavelength of 850nm, the average penetration depth is 18µm [7], meaning that the ratio of light collected in the depletion region versus light collected in the substrate below the depletion region is small Photodiode Model The photodiode model is based on the frequency response of the carrier drift current, J drift, and the minority carrier diffusion currents, J diff,e and J diff,h. A CMOS photodiode cross section is shown in Figure 2.1. The photodiode PN junction is formed by the p-substrate and the n-well. When a reverse bias voltage is applied, a depletion region is formed at the PN junction. Photons absorbed in the depletion region form the J drift current. The photons absorbed above and below the depletion region cause minority carrier diffusion in 7

19 2 Background both the n-well (J diff,h ) and the p-substrate (J diff,e ). The total current is J total = J drift + J diff,h + J diff,e. (2.3) The equations modelling the behaviour of the three currents are shown below. Readers interested in the derivation of these equations are invited to consult [22]. The drift current is swept out of the depletion region by the electric field present. According to [22], the drift current is much faster than the minority carrier diffusion currents and the speed of the TIA. Consequently, the response is considered frequency independent and proportional to the absorption coefficient and the width of the depletion region [22] J drift = qαw DR. (2.4) α is the absorption coefficient, W DR is the width of the depletion region. The J diff,e current equation is determined by the behaviour of minority carriers (electrons) in the p-substrate within the first few diffusion lengths L n below the depletion region [22] J diff,e = qαl n e αlx n=l 4 1 π 2 (2n 1) 2 ((2n 1)2πLn ). (2.5) jωτn + αl n l where l x is the depth of the n-well, τ n is the electron lifetime, and l is the periodicity of the structure. This parameter is used to model SML photodiodes. See [22] and [6] for further reading on SML photodiodes. For regular photodiodes, l = 1. The current response proves that for smaller α, the photodiode has a lower bandwidth, which is caused by the photons penetrating deeper into the the p-substrate, causing greater electron diffusion lengths. The J diff,h current equation is determined by the behaviour of minority carriers (holes) in the n-well above the depletion region. Holes have lower mobility than electrons. However, since the depth of the n-well is very shallow in modern processes, the diffusion lengths are much smaller than for J diff,e. The equation is [22] J diff,h = q L2 p l 32 π 2 (1 e αlx ) l x ( (2n 1)πLp n=1 m=1 2l x ( 2l x 1 l y 2n 1 ) 2 + l y 2l x ( 1 2m 1 ) 2 ) 2 + ( (2m 1)πLp l y ) jωτp. (2.6) 8

20 2 Background 5 10 Total Current Electron Diffusion Current Hole Diffusion Current Drift Current Current [db(a/w)] Frequency [Hz] Figure 2.2: Photodiode current response. where l x is the depth of the n-well, l y is the length of the n-well, L p is the diffusion length of holes, and τ p is the hole lifetime. The responsivity is small in this region due to the shallow depth of the n-well in modern processes. In smaller feature-size CMOS processes, the lower supply voltage and smaller device dimensions lead to a smaller depletion region, meaning the proportion of light captured in the depletion region compared to deep in the substrate decreases. This leads to a decreases of the intrinsic bandwidth of the photodiode [1][5] Photodiode Simulation The total current response of the photodiode along with the current response of the three regions of interest are shown in Figure 2.2. The 3dB bandwidth is 33MHz and the responsivity is 0.4A/W. Figure 2.3 shows the photodiode output for a 20ns segment of a 5Gbps PRBS13 sequence. The DC value of the signal shifts from bit to bit, which makes equalization more complicated. 9

21 2 Background 6 x Current [A] Power Normalized [W] Time [sec] x 10 8 (a) Time [sec] x 10 8 (b) Figure 2.3: (a) Photodiode response to -5dBm 5Gbps PRBS13 (b) Input signal. 2.2 State of the Art (extended) and Proposed Solution This section discusses solutions previously investigated to extend the bandwidth of the photodiode model developed in Section 2.1. As mentioned in Section 1.2, a SML photodiode can be used to eliminate slow diffusing current [6][14][15]. The two equalizer structures previously published are the use of an analog equalizer [6][5][16][17][18] to extend the system bandwidth, and the use of an IIR DFE [7] to remove ISI. Finally, the proposed architecture of this thesis is discussed Analog Equalizer to Extend the System Bandwidth The block diagram of the receiver proposed in [6] is shown in Figure 2.4. The square around the photodiode indicates it is covered, and does not convert light. This structure is similar to the structure proposed in [5][16][17][18], especially regarding the use of the equalizer. The AC coupling serves two purposes. Since the input to the TIA is single-ended, the AC coupling removes any DC offset in the differential output signal. The value of the DC offset is dependent on the average input power. Furthermore, it allows the TIA to be connected to the remaining circuit blocks, which operate at a different supply voltage and DC offset voltage. The subtracter is used to improve the commonmode rejection. The analog equalizer extends the bandwidth of the system, removing 10

22 2 Background Figure 2.4: Block diagram of receiver using an analog equalizer [6]. ISI, however, this structure amplifies high frequency noise. The post-amplifier and output buffer are needed to drive 50Ω per side external loads Decision Feedback Equalizer to Remove ISI Using a DFE to remove the long tail of post-cursor ISI created by the slow diffusion carriers requires too many taps, and therefore makes the power consumption excessive. In [7], a DFE that uses a IIR filter to mimic the exponential tail of the photodiode response is proposed. The DFE required the sum of 3 exponential responses to properly model the photodiode response. The advantage of this structure is that only one flip-flop is required, and once the coefficients of the IIR filters are set, they do not need to be re-adjusted for different data rates. The proposed block diagram is illustrated in Figure 2.5. The AC coupling block is still needed to remove any DC offset in the differential output due to the single-ended input, and allows the TIA to be connected to the remaining circuit blocks, which operate at a different DC offset voltage. The Variable Gain Amplifier (VGA) guarantees signal power to the DFE is constant regardless of the input optical signal power. The half-rate IIR DFE follows the VGA, with its clock provided by an Injection Locking Oscillator (ILO). The output buffer is used to drive 50Ω per side external loads. This receiver requires many coefficients to be set for proper equalization. Furthermore, it is not very forgiving of inaccuracies in the photodiode model without some kind of adaptation, which hasn t been investigated as of yet Proposed Solution The solutions presented in Section and attempt to remove the long tail of the post-cursor ISI through two different mechanisms. However, both solutions use 11

23 2 Background Figure 2.5: Block diagram of receiver using a IIR DFE [7]. AC coupling to connect the output of the TIA to the input of the equalization block, and to remove the common-mode offset in the differential output signal caused by the single-ended input. The corner frequency in both solutions is quite low, around 100kHz. Pushing the corner frequency out to a multi-ghz value removes the common-mode offset cause by the single-ended input, but it also removes all low-frequency content. However, this property can be used to remove the slow-moving diffusion current from the photodiode response. This mechanism is shown in Figure 2.6. Recent work on replacing DC interconnects between a transmitter and receiver with an AC interconnect is shown in [23]. The AC interconnect removes all lowfrequency content from the signal resulting in pulse-signaling. Since the problem with the photodiode response is the shifting of the DC value, an AC interconnect can be used as an equalizer within a receiver. The problem is returning the signal pulses to Non-Return-to-Zero (NRZ) format, as this requires a non-conventional receiver. This is achieved through a hysteresis latch, which is a non-linear circuit. This type of equalization has been used in electrical links in the past [24]. 2.3 High-Pass Filter and Hysteresis Latch This section describes the combination of two components, the high-pass filter and the hysteresis latch, used to perform the equalization of the receiver. 12

24 2 Background Gain [db(a/w)] Photodiode Response 35 High Pass Filter Response Total Response Frequency [Hz] Figure 2.6: Frequency response of proposed solution. C AC R Figure 2.7: High pass filter equalizer model High-Pass Filter Equalizer The AC coupling is done through a standard RC high pass filter. The model is shown in Figure 2.7. If the resistor R is set to a constant 200Ω differential, the capacitance C AC can be modified to change the high-pass filter corner frequency. A higher corner frequency reduces the pulse width, and consequently the total ISI. This effect is shown in Figure 2.8. For proper equalization, the pulse width must be less than 1Unit Interval (UI), and so a smaller capacitance value results in equalization of data at higher bit rates. However, the smaller capacitance values will decrease the pulse amplitude. The pulse amplitude must be greater than the minimum hysteresis threshold and provide sufficient noise margin. 13

25 2 Background Gain [db] Amplitude [V] fF 35 5pF 200pF Frequency [Hz] (a) fF 5pF 200pF Time [s] x (b) Figure 2.8: (a) High-pass filter response (b) Step response. Figure 2.9: High-pass filter equalizer with hysteresis latch Hysteresis Latch Model The hysteresis latch is the receiver for the high-pass filter equalizer. It converts the pulse signals to NRZ signalling. Figure 2.9 shows the receiver block diagram. In the hysteresis latch, the received signal is compared to two threshold voltages, V th and V th. If the signal is above V th, the output of the hysteresis latch is driven to a logic 1. If the signal is below V th, the output of the hysteresis latch is driven to a logic 0. If the received signal is between V th and V th, the hysteresis latch holds its value. 14

26 2 Background 2.4 System Simulation Figure 2.10 shows the results of a MatLab model of the proposed receiver system simulation. The input to the photodiode model is a 5Gbps PRBS13 signal. The photodiode model output is shown in Figure 2.10(e). The time display is of a 20ns segment of the input. For this simulation, the output buffer after the hysteresis latch has a bandwidth of 6.5GHz. The pulse-signalling seen at the output of the high-pass filter equalizer is shown in Figure 2.10(c). The corresponding eye diagrams are for a 5000UI segment of the 5Gbps PRBS13 input sequence. 15

27 2 Background Hysteresis Latch Output Eye Diagram [V] Hysteresis Latch Output [V] Eye Diagram Time [sec] (a) Eye Diagram Equalizer Output Eye Diagram [V] Equalizer Output [V] 0 2UI (b) x Time [sec] UI 8 x 10 (c) (d) 5 6 x Eye Diagram x Photodiode Output Eye Diagram [A] Photodiode Output [A] Time [sec] UI 8 x 10 (e) (f) Figure 2.10: The input to the photodiode model is a 5Gbps PRBS13 signal (a) Output of the hysteresis latch (b) Hysteresis latch eye diagram (c) Equalizer output (d) Equalizer output eye diagram (e) Photodiode output (f) Photodiode output eye diagram. 16

28 Photodiode TIA High-pass filter Hysteretic Comparator Output Buf. 10pF 300fF 6MΩ 50Ω A f 50Ω V out Dummy 1.36kΩ 200Ω 50Ω Figure 3.1: Receiver block diagram. 3 Circuit/System Design and Simulation This chapter presents the block and system level design of the optical receiver. The system architecture is described in Section 3.1. Block level schematic design and simulations are provided in Section 3.2 to Section 3.6. Section 3.7 details the full system simulation results. 3.1 System Description Circuit Description The receiver is designed to handle signal data rates up to approximately 5Gbps, with a change of input current signal of approximately 20µA. The receiver block diagram is shown in Figure 3.1. The receiver begins with the two photodiodes. The photodiode surrounded by the box is covered by metal, therefore it will not convert any optical power to electrical power. The purpose of this photodiode is to balance the capacitance at both input nodes of the differential TIA. The remaining photodiode will convert the optical signal to an electrical signal. 17

29 3 Circuit/System Design and Simulation Table 3.1: Simulation corner parameters. Corner Transistor Corner Temperature Supply Voltage Typical TT 27 o C 1.2V Slow SS 85 o C 1.2V Fast FF 0 o C 1.2V The electrical signal is fed to the differential TIA, which converts the signal current to a signal voltage. The TIA drives the high-pass filter described in Section 2.3, which is used to remove ISI. The high-pass filter also acts as AC coupling between the TIA and the linear amplifier stage, since they operate at different common-mode voltages. The linear amplifier increases the signal swing. Any offset in the differential voltage at the input will by amplified by the gain of this stage to overwhelm the signal at the output. To solve this problem, offset compensation is included in this stage. The hysteresis latch returns the signal to NRZ signalling levels, as described in Section 2.3. The output buffer is included for testing. It needs to drive a 50Ω load per side Technology The design was implemented in the Taiwan Semiconductor Manufacturing Company (TSMC) 90nm CMOS technology. It has 1 polysilicon layer, and 9 metal layers. The supply voltage for this design is 1.2V Simulation Corners The design was tested with three simulation corners, listed in Table 3.1, to ensure that the circuit would operate properly despite process variations. The current densities are controllable through external pins, and were kept constant across the three simulation corners. 3.2 Transimpedance Amplifier The TIA is the most critical block of the receiver design. The TIA is the first block, meaning that its noise contributions dominate the total receiver noise. The other 18

30 3 Circuit/System Design and Simulation R f 1.36kΩ 0.64V A f V out R f 1.36kΩ Figure 3.2: TIA block diagram. V DD R D1 150Ω R D2 150Ω C m 135fF V out V in M1 M2 M3 M4 60 2µm/0.12µm 60 2µm/0.12µm V b M µm/0.12µm M µm/0.12µm 7.4mA 7.4mA Figure 3.3: TIA core amplifier schematic. important specifications are the bandwidth, transimpedance and stability. The TIA architecture is taken from [4]. The TIA block diagram is shown in Figure 3.2, and the core amplifier schematic is shown in Figure 3.3. The transistor sizes have the format of N f W f /L f where N f is the number of fingers, W f is the width of the fingers, and L f is the length of the fingers. This convention is used for all schematics. 19

31 3 Circuit/System Design and Simulation In [4], the supply voltage for the TIA is 3.3V. In [7], the TIA uses the same architecture as [4], but with a 1.2V supply voltage. Thus, the transistor sizing is taken from [7], which is why the transistors do not have minimum lengths. For this architecture, the bandwidth is BW TIA = 1 2πR in,tia C PD. (3.1) where R in,tia is the input impedance of the TIA, and C PD is the parasitic capacitance of the photodiode. The targeted bandwidth in [4] is 2.8GHz, while it is 3GHz in [7]. The input impedance of the TIA is R in,tia = R f A f. (3.2) where R f is the feedback resistor, and A f is the gain of the core amplifier, both shown in Figure 3.2. The core amplifier in [7] draws 9.3mW, and the core amplifier in [4] draws 31.7mW. While the core amplifier gain is not specified in either work, the power drawn suggests that the core amplifier in [4] has a higher gain, since the core gain is given by A f = (g m R D ) 2. (3.3) where g m is the transconductance of the transistors forming the differential pair, and R D is the load resistances of the differential pair. Furthermore, the photodiode capacitance in [4] is reported as 500fF, while the photodiode capacitance reported in [7] is 2pF. To achieve the desired bandwidths, the feedback resistance, R f, is 5.6kΩ in [4], while it is only 300Ω in [7]. The transimpedance of the TIA is R T = R fa f A f + 1. (3.4) and is approximately equal to R f if the core amplifier gain is significantly higher than 1. The transimpedance in [4] is 75dBΩ while it is only 49.5dBΩ in [7]. This implies higher input-referred noise in [7], which is determined by integrating the TIA output noise spectral density v n,out (f) from a low non-zero frequency (to ensure a finite result in the presence of 1/f-noise) to twice the TIA bandwidth, and dividing it 20

32 3 Circuit/System Design and Simulation Table 3.2: Comparison of TIA design parameters with [4] and [7]. Parameter [4] [7] This Work Power Supply (V) Core Amplifier Power (mw) Photodiode Capacitance (pf) Feedback Resistor (kω) Midband Transimpedance (dbω) Bandwidth (GHz) Input-referred noise current (µa RMS ) by the midband transimpedance. i rms n,tia = 1 R T 2BWTIA 0 + v n,out (f)df. (3.5) The input-referred noise reported in [4] is 0.19µA rms, while it is 2.9µA rms in [7]. Increasing the transimpedance from the 300Ω reported in [7] is a priority, since it will relax gain requirements for subsequent stages, and reduce the input-referred noise. To do so, the current through each stage of TIA is approximately doubled from [7]. The widths of the transistors are increased to maintain a similar over-drive voltage. This doubles the g m of the transistors. To keep the transistors in saturation, but still keep the core amplifier gain high, the load resistors are only reduced from 200Ω to 150Ω. This reduces the TIA input DC bias voltage from 0.8V to 0.64V. With these changes in place, a photodiode capacitance of 1.35pF, and a target bandwidth of 3.5GHz, the value of the feedback resistor can be increased to 1.36kΩ. Compared to [7], this increases the transimpedance to 62.7dBΩ and decreases the input-referred noise to 1.1µA. The TIA input impedance is 32.7Ω. The parameters of the three designs are tabulated in Table 3.2. The frequency response of the TIA under the different corner conditions is shown in Figure 3.4. The value of C m was chosen to eliminate peaking in the frequency response. A summary of the TIA performance is shown in Table 3.3. Monte-carlo simulation results for the TIA, which include mismatch and process variations in R f, are shown in Table 3.4. A minimum open-loop phase margin of 60 o would be a good target to robustly 21

33 3 Circuit/System Design and Simulation Transimpedance [dbω] Typical Corner Slow Corner Fast Corner Frequency [Hz] Figure 3.4: TIA bandwidth. Table 3.3: TIA simulation summary. Corner Typical Slow Fast Midband transimpedance (dbω) Bandwidth (GHz) Peaking (dbω) Phase margin (degree) Input-referred noise current (µa RMS ) Table 3.4: TIA monte-carlo simulation summary. Mean Standard deviation Number of oints Midband transimpedance (dbω) Bandwidth (GHz) Peaking (dbω) 4.05m 1.84m 1000 Phase margin (degree)

34 3 Circuit/System Design and Simulation minimize overshoot and guarantee stability. From these simulation results, the phase margin is 85 o, significantly higher than the required 60 o. A re-designed TIA could feature less phase margin for better bandwidth and input-referred noise. The bandwidth could be increased by reducing R f, although this would decrease the transimpedance and increase the input-referred noise. In [17][19], the core amplifier of the TIA has four stages. Additional stages could be added to the core amplifier of the TIA in this work to increase the core amplifier gain, which would increase the bandwidth. A combination of additional stages in the core amplifier, and an increase in R f would result in a similar bandwidth, but higher transimpedance and lower input-referred noise, with lower phase margin. A further area of improvement would be using minimum-length transistors in the TIA. In fact, if the length was decreased by a factor of λ = 120nm/100nm = 1.2 to a minimum size of 100nm, either the bandwidth, or the transimpedance/input-referred noise could be improved. If the transistor is kept at a minimum length, and the overdrive voltage stays constant, the total current per stage, I, will increase by λ. If R D1 and R D2 are kept constant, the input and output common mode will decrease by 0.5 IR D2 (λ 1), which should still leave enough headroom to keep all six transistors in the saturation region. Furthermore, the poles at the inner node and at the output will increase by λ. The core amplifier gain, A f, will increase by λ 2. If the feedback resistor, R f, is kept constant, the bandwidth will increase by a factor of λ 2. The inpact on input-referred noise is hard to quantify analytically. Since the closed-loop bandwidth increases, the phase margin might decrease. However, if the feedback resistor is also increased by λ 2, then the bandwidth will stay constant, but the transimpedance will increase by λ 2. The input-referred noise is still hard to quantify analytically, but since the transimpedance increases, the input-referred noise should decrease. 3.3 High-Pass Filter The high-pass filter converts the output of the TIA to pulse-signalling. It also doubles as an AC interconnect between the TIA and the linear amplifiers, so they can operate at different DC offsets. Furthermore, it removes the common-mode offset in the differential output of the TIA caused by the single-ended input. 23

35 3 Circuit/System Design and Simulation C AC 300fF R 100Ω V IN V CM V OUT R 100Ω C AC 300fF Figure 3.5: High-pass filter schematic. The high-pass filter is taken from the work presented in [8]. The schematic is shown in Figure 3.5. The input common-mode voltage of the linear amplifiers is set to 900mV using the V CM pin. The corner frequency is f 3dB = 1 1 2π C AC R = 5.3GHz. (3.6) The eye diagram shown in Figure 3.6 is generated using a spice simulation. The input is a 5Gbps PRBS31 signal with 5ps rise and fall time. It has a 400µV DC offset, and a 600µV pp swing, to emulate an optical signal with -4dBm average power, and 8.5dB extinction ratio. This signal is passed through the photodiode model developed in Section 2.1. The output of the photodiode model modulates a current source at the input of the TIA. The eye diagram covers 10000UIs, and is of the output of the high-pass filter. There are three distinct levels, a high-pulse, a low-pulse and no pulse. The high-pulse indicates a low-to-high data transition. A low-pulse indicates a high-to-low data transition. A zero means there was no transition in the data signal. 3.4 Linear Amplifier The output of the high-pass filter is only 5mV pk, and needs to be amplified to be able to reliably trigger the hysteresis latch. This is accomplished by a multi-stage linear amplifier. In order to amplify the 5mV signal outputted by the filter to at least 120mV for the hysteresis latch, the gain must be at least 28dB. If the gain is increased significantly more than 28dB, there is greater power consumption without increasing 24

36 3 Circuit/System Design and Simulation Figure 3.6: Eye diagram after the high-pass filter; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into the photodiode. The simulation covers 10000UIs. the effectiveness of the receiver. Furthermore, the linear amplifiers contribute to the total input-referred noise of the receiver, but this contribution is reduced with a higher gain per stage [25]. The architecture is shown in Figure 3.7. The schematic for each gain stage is shown in Figure 3.8. The transistors are sized to have a bandwidth greater than the bandwidth of the TIA, and cumulative gain of 28dB. The resistors are sized to maintain the 900mV output common-mode voltage. The input of the linear amplifier is shown in Figure 3.9, and is also taken from [4]. Since any offset voltage in the linear amplifier would be amplified and saturate other stages, offset cancellation is required, as seen in Figure 3.7. The low-pass filter is made using a 6MΩ resistor and two 5pF capacitors connected differentially, which are smaller than the values reported in [4]. In [4], the resistor is 11MΩ and the singleended capacitor is 70pF. The capacitor can be halved with a differential structure. The components are smaller in order to meet the 250µm pitch requirement for multiple optical lanes [26][27][28]. Spice simulations confirm that the corner frequency is low enough to properly compensate an offset caused by a difference of 20% in the width of the first gain stage input pair. The frequency response of the linear amplifier is shown in Figure The midband 25

37 3 Circuit/System Design and Simulation Figure 3.7: Block diagram of offset compensation. V DD R D 150Ω V OUT M1 M2 20 2µm/0.12µm V IN M3 50 2µm/0.12µm V B 2.7mA Figure 3.8: Linear amplifier schematic for one stage. 26

38 3 Circuit/System Design and Simulation V DD R D 150Ω V OUT M1 M2 M3 M4 20 2µm/0.12µm 20 2µm/0.12µm V IN,OC V IN V B1 M5 M6 50 2µm/0.12µm 50 2µm/0.12µm V B2 3.3mA 2.7mA Figure 3.9: Linear amplifier input schematic for offset compensation. 27

39 3 Circuit/System Design and Simulation Gain [db] Typical Corner 5 Slow Corner Fast Corner Frequency [Hz] Figure 3.10: Linear amplifier frequency response. Table 3.5: Linear amplifier simulation summary. Corner Typical Slow Fast Midband gain (dbω) Bandwidth (GHz) Offset compensation cut-off (khz) gain is 30.0dB. The total bandwidth is 4.50GHz, which is greater than the TIA bandwidth. A summary of the linear amplifier performance is shown in Table 3.5. The simulated differential output of the linear amplifier is shown in Figure The test input is the same as the input described in Section 3.3. The signal has an opening of approximately 150mV, which is large enough to trigger the hysteresis latch. An area of improvement would be using minimum-length transistors. The linear amplifier power could be reduced while maintaining the same gain. 3.5 Hysteresis Latch The hysteresis latch re-generates the low-frequency content of pulse-signalling, outputting NRZ signalling. The pulse signal is compared to a threshold value, which is 28

40 3 Circuit/System Design and Simulation Figure 3.11: Eye diagram after the linear amplifiers; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into the photodiode. The simulation covers 10000UIs. R D1 R D2 g m in g m 1 V out V in R D3 g m 2 I tail Figure 3.12: Block diagram of the hysteresis latch [8]. set by a feedback path. The polarity is determined by the value of the most recent pulse bit. The block diagram of the hysteresis latch, which is taken from [8][23], is shown in Figure The hysteresis condition is [23] g m 1 R 2 g m 2 R 1 > 1. (3.7) 29

41 3 Circuit/System Design and Simulation V DD R D1 170Ω R D2 200Ω R D3 100Ω M5 M6 10 2µm/0.12µm V OUT M1 M2 M3 M4 10 2µm/0.12µm 10 2µm/0.12µm V IN M7 M8 M9 40 2µm/0.12µm 40 2µm/0.12µm 40 2µm/0.12µm V B1 V B2 2mA Adjustable Adjustable Figure 3.13: Hysteresis latch schematic. There is flexibility to minimize the settling time, since there are two gain stages, and R D1 and R D2 can be manipulated. Furthermore, g m 2 works as a buffer between the critical node and the next stage. This design also uses a split-load [29], taking the feedback from the low-impedance fast-settling node, and taking the output from the high-swing node. The feedbackloop settling time is given by the time-constant R D1 C 1, where C 1 is the capacitance at the output of the feedback loop, and the output settling time is given by (R D2 + R D3 )C L, where C L is the output capacitance. See [23] for more details. The schematic for the hysteresis latch is shown in Figure 3.13, which is the schematic used in [8] to implement the hysteresis latch seen in Figure The threshold voltage is set by changing the bias voltage V B2. A smaller current through M8 and M9 results in a smaller threshold voltage. With the current through M8 and M9 set to approximately 1.5mA, the value of g m 1 is 8.85mA/V and the value of g m 2 is 9.26mA/V. The hysteresis condition is 30

42 3 Circuit/System Design and Simulation Figure 3.14: Threshold adjustments by changing I tail. g m 1 R 2 g m 2 R 1 = 8.85mA/V 200Ω 9.26mA/V 170Ω = 2.8. (3.8) which is greater than 1, and leaves a large safety margin for process, voltage and temperature variations. A plot of the differential output versus the differential input voltage is shown in Figure 3.14, which shows the receiver hysteresis. The threshold voltage increases with the current through M8 and M9. The simulated differential output of the hysteresis latch is shown in Figure The test input is the same as the input described in Section 3.3. The output has been re-generated to NRZ signalling levels. An area of improvement would be using minimum-length transistors. There would be more flexibility in choosing the values of g m, R D1, R D2 and R D3 to minimize the settling time, while keeping the power consumption constant. 3.6 Output Buffer The receiver performance will be measured by an oscilloscope and Bit Error Rate Tester (BERT) which have a 50Ω input resistance. In order to provide proper match- 31

43 3 Circuit/System Design and Simulation Figure 3.15: Eye diagram after the hysteresis latch; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into photodiode. The simulation covers 10000UIs. ing and signal swing, an output buffer whose output resistance is matched to 50Ω is included after the hysteresis latch. The output buffer s bandwidth must be greater than the TIA. Despite the fact that the small-signal approximation isn t very accurate because of the relatively large input signal, it can still be used as an approximation [6]. The BERT requires a minimum swing of 100mV pp per side. The load output impedance is 25Ω per side, as the 50Ω output impedance of the buffer is in parallel with the 50Ω input impedance of the oscilloscope/bert. The output buffer is driving a bondwire inductance of 2nH and a package pin capacitance of approximately 1pF. The swing requirement means the output buffer must drive a large current, 100mV/25Ω = 4mA. Consequently, the transistors need to be large, which loads the output of the hysteresis latch. To reduce the load, multiple differential stages are used. The hysteresis latch can drive the first stage. The second stage draws more current, to be able to drive the larger final stage, which must drive the 25Ω load per side. The schematic is shown in Figure The small-signal bandwidth is 4.2GHz, as seen in the frequency response shown in Figure The simulated single-ended output of the output buffer is shown in 32

44 3 Circuit/System Design and Simulation V DD R D1 170Ω R D2 85Ω R D3 50Ω V OUT V IN M1 M2 M3 M4 M5 M6 20 2µm/0.12µm 20 2µm/0.12µm 30 2µm/0.12µm M7 M8 M9 50 2µm/0.12µm 80 2µm/0.12µm 80 2µm/0.12µm V B1 V B2 V B3 2.7mA 5.2mA 5.2mA Figure 3.16: Output buffer schematic Gain [db] Frequency [Hz] Figure 3.17: Output buffer frequency response. Figure The test input is the same as the input described in Section 3.3. The swing is approximately 150mV pp per side, which is greater than the 100mV pp per side needed by the BERT. 33

45 3 Circuit/System Design and Simulation Figure 3.18: Eye diagram after the output buffer; 5Gbps PRBS31-4dBm average power and 8.5dB extinction ratio input into photodiode. The simulation covers 10000UIs. Table 3.6: Power consumption breakdown by voltage rail, which are both set to 1.2V. Block V DD Power (mw) ov DD Power (mw) TIA Linear Amplifiers Hysteresis Latch Biasing Circuitry Output Buffer Total Complete Receiver Simulation Results The simulation results of the complete receiver are presented in this chapter. The differential signal at different stages of the receiver (Figure 3.1) are shown in Figure 3.6, Figure 3.9, Figure 3.15, and Figure The power consumption breakdown is shown in Table 3.6. The measurement results are reported in Chapter 4. 34

46 4 Layout and Measurements This chapter presents the layout, test setup, and the measurement results for the optical receiver chip. The chip was built in TSMC s 90nm CMOS process, as detailed in Section 3.1. Section 4.1 details the chip layout and Section 4.2 presents the measurement results. 4.1 Circuit Layout Photodiode Layout The photodiode is built using an n-well/p-substrate structure, as detailed in Section 2.1. An annotated photo of the photodiode is shown in Figure 4.1. It uses two columns of seven fingers in order to reduce the transit time of the diffusion and drift current components from the doped region to the metal contacts. The photodiode is approximately 72µm by 78µm to facilitate the alignment of the 50µm fibre. The n-well is connected to metal 2, which appears dark purple in the photo. The metal 2 strip is 0.5µm wide, and uses two rows of contacts to the n-well. The p- substrate is connected to metal 1, which appears blue in the photo. The metal 1 strip is 1µm wide, and uses four rows of contacts to the n-well Chip Layout A photo of the bare die is shown in Figure 4.2. The chip s dimensions are 1.5mm by 1.0mm, resulting in an area of 1.5mm 2. In addition to the DC optical test structure, the chip has two optical receiver lanes, and an electrical breakout lane. Existing high-speed photodiode arrays which operate at 850nm wavelength have a 250µm pitch [26][27][28]. In order to meet this pitch requirement, each optical lane has a dimension of approximately 895µm by 220µm for an area of 0.197mm 2. There are three visible photodiodes on the chip, with two more photodiodes that are not visible. The photodiodes that are not visible are used to balance the input 35

47 4 Layout and Measurements Figure 4.1: Annotated photo of the photodiode n-well/p-substrate photodiode. It is 72µm 78µm. The n-well is connected to metal 2, while the p-substrate is connected to metal 1. capacitive load to the TIA. The top two visible photodiodes create the two optical receiver lanes, while the bottom photodiode is used in a DC test structure. Figure 4.2 shows that the three photodiodes detailed above were covered in aluminium after the initial fabrication. The aluminium was placed over all passivation layer openings, regardless of the actual aluminium layer definition. The aluminium definition was only located under passivation openings used by the bond pads. This aluminium blocked all light from entering the photodiodes, and had to be removed using a Focused Ion Beam (FIB) which can do site-specific ablation of metal. The die photo after the FIB process is shown in Figure 4.3. This figure also shows the bondwires that connect the die to a 44 pin Quad Flat No leads (QFN) package. The eighteen leftmost pads don t have any electrical connections, and consequently are not wirebonded. Close-up photographs of the photodiode before and after the FIB process are shown in Figure

48 4 Layout and Measurements 4.2 Measurements Figure 4.2: Photo of bare die. The QFN package was mounted on a custom Printed Circuit Board (PCB), which can be seen in Figure 4.5, for electrical and optical testing. The supply and commonmode voltages were generated using voltage regulators. The bias currents were set by varying potentiometers. This section details an electrical breakout test, a photodiode responsivity test, and an optical speed test Electrical Test The block diagram of the electrical test setup is shown in Figure 4.6. For all test setup diagrams, solid lines represent high-speed electrical connection, dashed lines represent optical connections, and dotted lines represent multimeter leads. The electrical test was performed at a room temperature of 24 o C. The PRBS generator has an output impedance of 50Ω, but the input impedance of the TIA is significantly smaller, which leads to a lot of reflections at the input. For this reason, it is hard to determine the actual eye magnitude seen at the input of the TIA. The output of the electrical breakout has a high BER if the input is smaller than 200mV pp for a PRBS7 input. 37

49 4 Layout and Measurements Figure 4.3: Photo of the die after the ablation of the aluminium over the photodiodes. (a) (b) Figure 4.4: Close-up photos of the photodiode (a) The photodiode after original manufacturing is covered by aluminium. (b) The photodiode after the ablation of the aluminium. 38

50 4 Layout and Measurements Figure 4.5: Photo of the PCB used to test the chip. Figure 4.6: Test setup for electrical testing. The eye diagrams of the electrical breakout are shown in Figure 4.7. However, with a PRBS31 input, the input must be increased to 300mV pp, and there are still obvious bit errors in the eye diagrams at 2.5Gbps and 3.125Gbps data rates. The eye diagrams are shown in Figure Photodiode Responsivity Test The block diagram for the photodiode responsivity test is shown in Figure 4.9. The schematic of the test structure is shown in Figure A 50µm/125µm optical fibre couples the power emitted from a 850-nm VCSEL (Finisar HFE ) to the photodiode. The voltage drop across the resistor shown in Figure 4.10 is measured 39

51 4 Layout and Measurements (a) (b) (c) (d) Figure 4.7: Eye diagrams with an electrical PRBS7 input to the board of 200mV pp (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. using a multimeter (Agilent 34401A), and the input optical power is measured using a power meter (Noyes OPM4). The photodiode responsivity test was performed at a room temperature of 24 o C. With an input signal of -0.16dBm (0.964mW), the voltage drop across the resistor was 0.326V, for a total current of 135.6µA. The responsivity is 0.141A/W Optical Test The block diagram of the optical test setup is shown in Figure The transmit and receive clock of the BERT (Centellax TG1B1-4) are generated by two synchronized generators (Agilent 83712B and E8257D). The BERT can only adjust the phase of 40

52 4 Layout and Measurements (a) (b) (c) (d) Figure 4.8: Eye diagrams with an electrical PRBS31 input to the board of 300mV pp (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. Figure 4.9: Test setup for photodiode responsivity testing. the receive clock in 90 o increments, so the two function generator setup allows for more precision to set the receive clock phase. The BERT generates the PRBS7 or PRBS31 signal which drives the VCSEL 41

53 4 Layout and Measurements 2.4kΩ Pad Photodiode Figure 4.10: Photodiode responsivity test structure. Figure 4.11: Test setup for the optical testing. 42

54 4 Layout and Measurements Figure 4.12: Photo of the test setup. driver (Mindspeed M02171-EVM) which in turn modulates the VCSEL (Finisar HFE ). The power emitted from the VCSEL is coupled to the chip through a 50µm/125µm optical fiber. The electrical output is differential; one of the outputs is captured by an oscilloscope (Agilent DCA-J 86100C) to measure the eye diagram while the second output is used by the BERT to compute the BER and determine the optical sensitivity. A photo of the setup is shown in Figure A photo of the optical probe coupling to the integrated photodiode is shown in Figure The optical test was performed at a room temperature of 24 o C. To determine the extinction ratio, the optical signal is applied to a discrete photodiode/tia package. Two packaged photodiode/tias were used: the NewFocus 1554-A (with a conversion gain of -200V/W), and the Archcom Technology AC6538 (with a conversion gain of -450V/W). The outputs for both photodiode/tia packages are captured on an oscilloscope and shown in Figure The average input power is -3.0dBm (0.5mW). The eye is approximately 180mV pp per side for the AC6538, and 150mV pp for the 1554-A. The extinction ratio for the AC6538 is shown in Equations The extinction ratio for the 1554-A is shown in Equations They are quite close, and so the extinction ratio is assumed to be approximately 9dB. P pp = 360mV 450V/W = 0.8mW (4.1) 43

55 4 Layout and Measurements Figure 4.13: Photo of the optical probe coupling to the integrated photodiode. (a) (b) Figure 4.14: Eye diagrams with an average input power of -3.0dBm at 2.5Gbps (a) Archcom Technology AC6538 (b) NewFocus 1554-A. P high = 0.5mW + 0.4mW = 0.9mW = 0.46dBm (4.2) P low = 0.5mW 0.4mW = 0.1mW = 10dBm (4.3) ER = 9.5dB (4.4) 44

56 4 Layout and Measurements P pp = 150mV 200V/W = 0.75mW (4.5) P high = 0.5mW mW = 0.875mW = 0.58dBm (4.6) P low = 0.5mW 0.375mW = 0.125mW = 9dBm (4.7) ER = 8.5dB (4.8) The overshoot shown in Figure 4.14(b) is due to the VCSEL turning on with such a large extinction ratio, which causes relaxation oscillation [25]. The large extinction ratio also causes the turn-on delay to experience random variations, meaning the optical data has more jitter [25]. The extinction ratio and, hence, overshoot and jitter, can be reduced by increasing the DC signal power while keeping the signal swing constant. However, this increases the offset seen in the outputs of the TIA. Furthermore, the power supply has to provide enough headroom for the TIA to perform as expected despite this DC offset. For example, a 2.5Gbps optical signal with -1.9dBm output and an extinction ratio of 4.8dB output has the same optical swing as the previous setup, and the output of the NewFocus 1554-A photodiode/tia shown in Figure 4.15(a) shows the eye has significantly less ringing. Furthermore, the rms-jitter decreases from 5.3ps rms to 4.4ps rms. However, Figure 4.15(b) is the output of the chip, and the eye diagram is closed, since there is too much DC offset at the output of the TIA. This suggests that offset compensation should act right on the input of the TIA to remove the signal-dependent DC offset as in [28][30][31]. On the other hand, offset cancellation right at the input would add input-referred noise. The measured output eye diagrams with an average input power of -3.7dBm and an extinction ratio of 9dB with a 1.2V supply is shown for various data rates with a length-(2 7 1) pseudo-random pattern PRBS7 in Figure 4.16 and with a length- (2 31 1) pseudo-random pattern PRBS31 in Figure Figure 4.18 shows a plot of BER against average input power for both the PRBS7 and PRBS31 input. These plots indicate the input optical sensitivity is -3.7dBm for a 2Gbps PRBS31 input and -4.9dBm for a 2.5Gbps PRBS7 input. Hence, the optical sensitivity can be greatly improved through the use of data encoding schemes, such as 8b/10b. Furthermore, the BER at 4.25Gbps for the PRBS7 input, and the BER at 3.125Gbps for the PRBS31 input, improve very little with an increase of input optical power. This suggests that the receiver is limited by bandwidth, not noise. The eye diagram measurements were repeated with the supply voltage increased to 45

57 4 Layout and Measurements (a) (b) Figure 4.15: Eye diagrams with an average input power of -1.9dBm and extinction ratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip. 1.3V and all other measurement conditions that same as in Figure 4.16 and The results are shown in Figure 4.19 for a PRBS7 input and Figure 4.20 for a PRBS31 input. Figure 4.21 shows a plot of BER against average input power for both the PRBS7 and PRBS31 inputs with the supply voltage increase to 1.3V. The BER gets better for the PRBS31 inputs, but worse for the PRBS7 inputs. This suggests that the increased supply voltage improves bandwidth (the main limitation in PRBS31 patterns) but that the increased noise bandwidth hurts the PRBS7 patterns. Hysteresis Threshold Dependence on Data Rate The hysteresis threshold level was optimized to minimize BER for each data rate, with an average input power level of -3.7dBm. This resulted in a higher hysteresis threshold for lower bit rates. Figure 4.22 shows the spice simulation output of the linear amplifiers with a PRBS7 input on the left, and a PRBS31 input on the right. There is no noise in this simulation. The blue line shows one possible threshold value, with the distance A showing the distance between the threshold value and the lowest possible logic-1 pulse value. The distance B shows the distance between the threshold value, and the highest possible no-transition value. A higher hysteresis threshold, which increases the distance B, makes the receiver less sensitive to noise. The pulses created by the PRBS31 input have a wider range 46

58 4 Layout and Measurements (a) (b) (c) (d) Figure 4.16: Eye diagrams with an optical PRBS7 input with an average input power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. of amplitudes compared to the pulses created by PRBS7. This is because the pulses created by the PRBS31 input suffers from more baseline wander before the high-pass filter. This decreases the distance A in the case of the PRBS31 input. Furthermore, the pulse amplitudes decrease when the data rate is increased. The threshold value is decreased to keep a similar value A. This hysteresis threshold configuration leads to the BER of the receiver with a small average input power being occasionally lower for higher input data rates, as seen in Figure For instance, in Figure 4.21(a), the BER of the 3.125Gbps signal is lower than the 2.5Gbps signal at input average powers below -6dBm. The reason this happens is that while a higher hysteresis threshold is less sensitive 47

59 4 Layout and Measurements (a) (b) (c) (d) Figure 4.17: Eye diagrams with an optical PRBS31 input with an average input power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. to noise, it won t trigger properly with a very small input signal. However, a lower hysteresis threshold is more sensitive to noise, but it will trigger properly for very small input signals. Analysis of Simulation Results Increasing the supply voltage from 1.2V to 1.3V, and optimizing the TIA bias current to minimize BER doesn t change the TIA DC input bias from 0.63V. The photodiode capacitance, responsivity, and intrinsic bandwidth are unchanged. The power drawn by the core amplifier increases from 18.2mW to 23.2mW, using the calculation below and the schematic shown in Figure

60 4 Layout and Measurements Gbps 2.5 Gbps Gbps 4.25 Gbps Gbps 2 Gbps 2.5 Gbps Gbps Bit Error Rate Bit Error Rate Average Optical Input Power [dbm] (a) Average Optical Input Power [dbm] (b) Figure 4.18: BER vs. average optical input for a constant 9dBm extinction ratio and a 1.2V supply (a) PRBS7 input (b) PRBS31 input. I M5 = I M6 = 2 1.2V 0.63V 150Ω = 7.6mA (4.9) P TIA = 1.2V (2 7.6mA) = 18.2mW (4.10) The increase in power leads to an increase in the core amplifier gain, which will decrease the input impedance. Since the photodiode capacitance is unchanged, the TIA bandwidth increases. The transimpedance is unchanged. Since the output noise spectral density is now integrated over a wider bandwidth, the total input-referred noise increases. Spice simulations suggests the input-referred noise increases from 1.1µA rms to 1.13µA rms, and the bandwidth increases from 3.6GHz to 3.9GHz. The change in supply voltage also increases the gain per stage of the linear amplifiers. Spice simulations also suggest that the linear amplifiers bandwidth remains approximately constant, which is still significantly higher than the TIA bandwidth. From these results, it is probable that the signal-to-noise ratio at the input of the TIA degrades slightly with the change in power supply voltages. The receiver had sufficient bandwidth with a 1.2V supply to equalize a PRBS7 input pattern. Hence, the increase in bandwidth with a 1.3V supply doesn t improve the performance. The higher input-referred noise degrades the BER. However, the increase in bandwidth does improve the performance of the receiver with a PRBS31 input pattern, since this kind of pattern is more bandwidth dependent than a PRBS7 49

61 4 Layout and Measurements (a) (b) (c) (d) Figure 4.19: Eye diagrams with an optical PRBS7 input with an average input power of -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. input pattern. The bandwidth dependence of a PRBS31 input is due to the additional baseline wander before the high-pass filter. This causes the pulses after the filter to have a wider range of amplitudes, as shown in Figure Increasing the bandwidth of the TIA decreases the total amount of baseline wander, since the output signal settles to its final value faster. This in turn decreases the vertical spread of the pulse signal after the high-pass filter, resulting in a greater distance A, as seen in Figure The measurement results are presented in Table 4.1. The simulation and measurement results agree with respect to power consumption. DC optical measurement results show that the DC responsivity is 0.141A/W instead 50

62 4 Layout and Measurements (a) (b) (c) (d) Figure 4.20: Eye diagrams with an optical PRBS31 input with an average input power of -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. of the 0.4A/W of the photodiode model. While the effect of the FIB process on the optical responsivity is hard to measure, the difference is likely due to the inaccuracies of the analytical model of the photodiode presented in Section 2.1. The analytical model depends on dopant concentrations and diffusion lengths that are not published, so they can only be estimated. A device simulator or actual photodiode measurement results would provide a significantly more accurate model. The intrinsic bandwidth of the photodiode can t be measured using this prototype. Furthermore, the bias currents are lower than the bias currents seen in TT simulations, suggesting that the die is slower than the TT corner. Figure 4.23 shows a new circuit simulation, where the response of the photodiode 51

63 4 Layout and Measurements Gbps 2.5 Gbps Gbps 4.25 Gbps Gbps 2 Gbps 2.5 Gbps Gbps Bit Error Rate Bit Error Rate Average Optical Input Power [dbm] (a) Average Optical Input Power [dbm] (b) Figure 4.21: BER vs. average optical input for a constant 9dBm extinction ratio and a 1.3V supply (a) PRBS7 input (b) PRBS31 input. (a) Figure 4.22: Spice simulation output of the linear amplifier, with the plot on the left having a PRBS7 input, and the plot on the right having PRBS31 input. The blue lines represent a possible threshold value. 52

64 4 Layout and Measurements Table 4.1: Measurement results for optical testing. The chip is built in a standard 90nm CMOS. The wavelength used is 850nm. The simulation results are for a 1.2V supply voltage with a temperature of 27 o C. The extracted simulation are for 1000UIs. It is not possible to infer the optical sensitivity from that length of simulation. Simulation 1.2V Supply 1.3V Supply Total chip area 1.5mm 2 Receiver area 0.197mm 2 Receiver power (minus output buffers) 50.0mW 46.3mW 55.2mW Output buffer power 17.4mW 19.6mW 22.4mW Optical Sensitivity dBm 2Gbps is shifted down to the measured value, with the bandwidth left unchanged. This is a complete noise transient simulation done using a full RC-extraction. The simulation shows 1000UIs with a PRBS7 input. It is impossible to simulate the UIs necessary to measure a BER. However, the eye opening is smaller with the full RC-extraction and updated photodiode model than the eye shown in Figure Measurement results show that the BER should be approximately 10 4 with this setup, according to Figure

65 4 Layout and Measurements (a) (b) Figure 4.23: Eye diagram after the output buffer with revised photodiode model, 4.25Gbps PRBS7-4dBm average power and 8.5dB extinction ratio input into photodiode. The supply voltage is 1.2V and the simulation temperature is 27 o C (a) TT simulation corner (b) SS simulation corner. 54