Transimpedance Amplifier Design using 0.18 µm CMOS Technology

Transcription

1 Transimpedance Amplifier Design using 0.18 µm CMOS Technology by Ryan Douglas Bespalko A thesis submitted to the Department of Electrical and Computer Engineering in conformity with the requirements for the degree of Master of Science (Engineering) Queen s University Kingston, Ontario, Canada July 2007 Copyright c Ryan Douglas Bespalko, 2007

2 Abstract This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking, series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the i

3 transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. ii

4 Acknowledgments This section is to acknowledge the people and organizations that have generously assisted in the completion of this thesis. First, I d like to thank my thesis supervisor Dr. Brian Frank for his interest and enthusiasm over the past years. His guidance and support, as well as his extensive knowledge of CMOS circuit design have been instrumental in making this thesis a success. I d also like to thank my other thesis supervisor Dr. John Cartledge for his support, particularly in the area of photonics. His clear teaching style has made optical communications understandable, even for a circuit designer. Second, I d like to thank the students in the Very High Speed Circuits lab at Queen s University. Thank you for the many useful discussions which have been a great help, as well as the occasional much needed distraction during the many long hours in the lab. Financial support for this work has been provided by the Natural Sciences and Engineering Research Council (NSERC), the Canadian Institute for Photonic Innovations (CIPI), as well as Queen s University. Finally I d like to thank my family for their continued support. You ve always been there to help me follow my dreams. iii

5 Table of Contents Abstract Acknowledgments Table of Contents List of Tables List of Figures Nomenclature i iii iv vii viii xii Chapter 1 Introduction Fiber to the Home Common Access Network Architectures Multiple Access Techniques for PONs Integrated Optical Transceiver Challenges of CMOS Thesis Overview and Major Contributions Chapter 2 Background Theory Optical Receiver - Basic Theory Receiver Sensitivity Integrated Transceiver Transimpedance Amplifiers Common TIA topologies Open Loop TIAs Feedback TIAs Bandwidth Considerations Chapter 3 Literature Review Transimpedance Amplifier Topologies Regulated Cascode TIA DC Coupled Common Gate TIA Feedback TIAs Bandwidth Extension Shunt Peaking iv

6 3.2.2 Series Inductive Peaking Shunt and Series Peaking Chapter Gbps Transimpedance Amplifier Design Introduction The Cascode Structure Miller Effect Cascode vs. Common Source Gbps TIA Design Variable Gain Final Schematic Simulation Results Measured Results Measurement Setup Transistor Model Verification Transimpedance Measurements Group Delay Measurements Noise Measurements Common Mode Rejection Ratio Measurement Conclusion Chapter 5 10 Gbps Transimpedance Amplifier Introduction Inductive Peaking Shunt and Series Inductive Peaking Shunt-Series Inductive Peaking Gbps TIA Design Noise Analysis Optimum Device Size Final Schematic On-Chip Inductors Resistors Simulation Results Front-End Tuning Measured Results Inductor Measurements Differential Measurements Single-Ended Measurements Conclusions Chapter 6 Conclusions and Future Work Conclusions Future Work References 118 v

7 Appendices Appendix A Noise Model Calculations 122 A.1 High Frequency Noise Model A.2 Common Source Transistor Model with Resistive Feedback A.3 Calculating Noise Parameters from ABCD Representation Appendix B Noise Measurements 130 B.1 Determining Device Noise Parameters B.1.1 R. Q. Lane Method B.2 Noise Parameter Measurement Procedure B.2.1 Measurement Setup B.2.2 Source Impedance Measurement B.2.3 Noise Figure Measurement B.2.4 Loss Compensation vi

8 List of Tables 1.1 PON Data Transmission Rates and Wavelengths GPON Standard Gbps TIA Component Values Gbps TIA Performance Comparison Values of m for Shunt and Series Inductive Peaking Gbps TIA Component Values Gbps TIA Performance Comparison vii

9 List of Figures 1.1 Common Access Network Architectures Passive Optical Network Architecture Basic Optical Receiver Block Diagram Probability Density Function Basic Optical Receiver Block Diagram MIC Block Diagram for an Integrated Transceiver Transimpedance Amplifier Input Referred Noise Current Photodiode and Simple Transimpedance Amplifier Basic Optical Receiver Block Diagram Common Gate TIA Feedback TIA Response of a Second Order Filter to Random Data Response of a Filter with a Low Frequency Cut-off of 20 MHz to Random Data Regulated Cascode TIA DC Coupled Common Gate TIA Feedback TIA Topologies Shunt Inductive Peaking TIA Using Series Inductive Peaking viii

10 3.6 Shunt and Series Inductive Peaking Common Source and Cascode Amplifiers Common Source Equivalent Circuit Miller Theorem Differential Cascode TIA Cascode TIA with AGC Gbps TIA Final Schematic Current Mirror Gbps TIA Chip Photo Gbps TIA Chip Plot Simulation Setup Simulated Transimpedance Gain and Input Referred Noise Current Estimated BER for the 2.5 Gbps TIA Simulation Setup S-Parameters for a 30 Finger Common Source Transistor S-Parameters for a 30 Finger Common Source Transistor Simulated vs. Measured Transimpedance Simulated and Measured Transimpedance Gain with Various AGC Voltages - C P D = 0 ff Simulated and Measured Transimpedance Gain with Various AGC Voltages - C P D = 250 ff Simulated vs. Measured Phase and Group Delay - AGC = 0.0 V Simulated vs. Measured Phase and Group Delay - AGC = 3.0 V Noisy Two-port Network Representation Simplified Noisy Two-port Network Representation TIA Noise measurements AGC = 0.0 V TIA Noise measurements AGC = 3.5 V ix

11 4.25 Port Numbering Convention Measured Common Mode Rejection Ratio Various Methods of Inductive Peaking Bandwidth Improvement Using Shunt and Series Inductive Peaking Modified Shunt and Series Peaking for Interstage Bandwidth Extension Resonance Frequencies Using Series Inductive Peaking Frequency Response and Group Delay as the Series Inductance is Reduced Bandwidth Improvement Using Shunt, Series, and Shunt-Series Inductive Peaking Transient Response with a Bandwidth of Approximately 11 GHz Transient Response with a Bandwidth of Approximately 9 GHz Transient Response with a Bandwidth of Approximately 7 GHz Transient Response with a Bandwidth of Approximately 5 GHz Differential TIA Input Stage Using Shunt-Series Inductive Peaking TIA Input Stage Half Circuit Cascaded Networks Cascaded Networks with Noise Sources Transimpedance Gain and Group Delay as the Transistor Size is Increased Feedback Resistance versus Device Size Optimum Device Size for Various Values of the Drain Bias Current I den Optimum Current Density Series Inductance versus Device Size Transimpedance, Group Delay and Input Referred Noise Current using the Optimum Device Size Gbps TIA Schematic Monolithic Inductors x

12 Gpbs TIA Die Photo Gbps TIA Chip Plot Full Circuit Simulation Gbps TIA with Front-End Tuning Full Circuit Simulation with Front-End Tuning Inductor Test Structure Measurements Gbps TIA Measured Output Spectrum Gbps TIA Load and Source Stability Factor Gbps TIA Load and Source Stability Factor with Source Connections Gbps TIA Single-ended Measurements A.1 High Frequency Noise Model A.2 Noise Measurement Setup A.3 Common Source Transistor with Feedback A.4 ABCD Representation with Noise B.1 Noisy Two Port Network B.2 Noise Measurement Setup B.3 Source Impedance Measurement Setup B.4 Loss Compensation xi

13 Nomenclature Latin Symbols B B opt B cor C BP C DS C GD C GS C P D D F F min f 3dB G a G cor g m g mb G opt G u I 1 Noise Bandwidth [Hz] Optimum Source Susceptance [S] Noise Correlation Susceptance [S] Bond Pad Capacitance [F] Drain to Source Capacitance [F] Gate to Drain Capacitance [F] Gate to Source Capacitance [F] Photodiode Capacitance [F] Decision Threshold [V] Noise Factor Minimum Noise Factor 3dB Bandwidth [Hz] Available Gain [db] Noise Correlation Conductance [S] Transconductance [V/V] Back Gate Transconductance [V/V] Optimum Source Conductance [S] Equivalent Noise Conductance [S] Pulse Shape Dependent Factor xii

14 I den I N Drain Current Density [A/m] Input Referred Noise Current Source [A] i n,in 2 Mean Squared Input Referred Noise Current [A 2 ] i n,in 2 Input Referred Noise Current [A rms] d i n,in 2 df k Input Referred Noise Current Spectral Density [A/ Hz] Boltzmann Constant [J/K] L BW P avg Q q R R b r ds r e R F B R n Bond Wire Inductance [H] Average Optical Input Power [dbm] Quality Factor Charge of an Electron [C] Responsivity [A/W] Bit Rate [bps] Drain to Source Resistance [Ω] Extinction Ration [db] Feedback Resistance [Ω] Equivalent Noise Resistance [Ω] S d1 Signal level for a 1 S d0 Signal level for a 0 σ 1 Noise power for a 1 σ 0 Noise power for a 0 T V d V g V N Temperature [K] Drain Voltage [V] Gate Voltage [V] Input Referred Noise Voltage Source [V] v n,out 2 Mean Squared Output Noise Voltage [V 2 ] Y cor Y opt Noise Correlation Impedance [Ω] Optimum Source Impedance [Ω] xiii

15 Z T Transimpedance [dbω] Greek Symbols ɛ Γ opt Γ out Least Squares Error Optimum Reflection Coefficient Output Reflection Coefficient µ Stability Factor for the Load µ Stability Factor for the Source φ τ g ω phase [rad] Group Delay [s] Angular Frequency [rad/s] Acronyms AC ADS AGC APD APON ATM BER CMOS CMRR DC DSL DUT EM EPON Alternating Current Advanced Design System Automatic Gain Control Avalanche Photodiode ATM Passive Optical Network Asynchronous Transfer Mode Bit Error Rate Complimentary Metal Oxide Semiconductor Common Mode Rejection Ratio Direct Current Digital Subscriber Line Device Under Test Electro-Magnetic Ethernet Passive Optical Network xiv

16 erfc GaAs Gbps GPON HDTV IEEE InP ISI LA LD Mbps MIC nmos NRZ OLT ONU P2P P2MP PIC pmos PON RGC SCMA TDMA TSMC TIA VNA Complimentary Error Function Galium Arsenide Giga bits per second Gigabit-capable Passive Optical Network High Definition Television Institute of Electrical and Electronics Engineers Indium Phosphide Inter Symbol Interference Limiting Amplifier Laser Driver Mega bits per second Microelectronic Integrated Circuit n-type Metal Oxide Semiconductor Non Return to Zero Optical Line Termination Optical Network Unit Point-to-Point Point-to-Multi-Point Photonic Integrated Circuit p-type Metal Oxide Semiconductor Passive Optical Network Regulated Cascode Subcarrier Multiple Access Time Division Multiple Access Taiwan Semiconductor Manufacturing Company Transimpedance Amplifier Vector Network Analyzer xv

17 VoD VoIP WDMA Video on Demand Voice over Internet Protocol Wavelength Division Multiple Access xvi

18 Chapter 1 Introduction 1.1 Fiber to the Home Fiber optic networks are playing an increasingly important role in today s communication networks, primarily in long haul and metropolitan systems. These networks have created a large amount of low cost bandwidth that is the core of today s networks. However, there still exists a large bottleneck in the last mile, or the local access level of service between the metropolitan system and the home or business. Due to the high cost of fiber-based implementations, hybrid fiber coax and digital subscriber line (DSL) solutions currently dominate at the access level. However, due to the ever expanding set of services being offered to residential homes, these technologies are having difficultly keeping up with the increased bandwidth requirements. These services include high speed Internet, video on demand (VoD), voice over Internet protocol (VoIP), and high definition television (HDTV). Other potential services may include remote patient observation for medical purposes using video surveillance. This would be aimed at cutting health care costs by allowing people to stay at home during care. Another potential service would be teleworking, where people work from home to reduce rush hour traffic [1]. DSL and cable modem technologies are constantly evolving and reaching higher 1

19 CHAPTER 1. INTRODUCTION 2 speeds to meet these demands. These speed increases generally come at the cost of shorter link lengths, and result in further penetration of fiber into the access network. Eventually, as customers continue to demand higher speed services, fiber will make up the entire access network. The low loss and extremely wide bandwidth of optical fiber make it capable of handling not only the current capacity, but also handling any capacity challenges in the foreseeable future [1] Common Access Network Architectures There are three general network architectures that are considered in the access network. The first is a Point-to-Point (P2P) architecture, shown in Figure 1.1 a), where a dedicated fiber is run from the local exchange (optical line termination (OLT)) to each customer (optical network unit (ONU)). This type of architecture involves a large initial cost since there is a lot of equipment required at the local exchange and none of it is shared among customers. This system however, provides the largest capacity since each link is independent and the bandwidth is not split among multiple customers. This system also has the highest level of flexibility. Each connection can be customized, and the services can be upgraded on a customer to customer basis. ONU ONU ONU ONU OLT Customer Terminations OLT Active Node Customer Terminations Local Exchange ONU Local Exchange ONU ONU ONU (a) (b) Figure 1.1: Common Access Network Architectures a) Point-to-Point b) Active Star

20 CHAPTER 1. INTRODUCTION 3 The other two general architectures are both Point-to-Multi-Point (P2MP) networks. The first P2MP architecture is the active star shown in Figure 1.1 b). In this system, a single fiber is run from the local exchange to an active node in the field that is close to the end users. Individual fibers are then run from this node to each of the customer terminations. The advantage of this system is that there is only one fiber from the local exchange, which reduces the amount of equipment needed. The actual terminal at the local exchange is more complex, but there is only one terminal instead of one terminal for every customer. The disadvantage of this system is that the active node requires power and maintenance. The second P2MP architecture is the passive optical network (PON) shown in Figure 1.2. In a PON, the active node in an active star architecture is replaced with a passive optical splitter/combiner. This type of architecture benefits from the reduced installation costs of a P2MP network and avoids the extra operational and maintenance costs associated with an active star configuration. The only downside is that the loss in the power splitter/combiner will result in slightly shorter link lengths when compared to the active star configuration. For these reasons, PONs show the most promise for implementing a fiber based solution in the access network. The following sections will examine different PON configurations and discuss some performance specifications for several standards that have been developed for PONs Multiple Access Techniques for PONs Since the fiber that feeds the passive splitter/combiner in a PON is shared by every customer, multiple access techniques need to be used to avoid data collisions. In the downstream direction, all of the data is simply transmitted to every ONU, and each ONU is responsible for selecting the appropriate data. In the upstream direction, multiple access techniques are needed to avoid collisions and multiplex the data coming from each ONU.

21 CHAPTER 1. INTRODUCTION 4 ONU ONU OLT Customer Terminations Local Exchange Passive Optical Power Splitter/Combiner ONU ONU Figure 1.2: Passive Optical Network Architecture There are several different proposed multiple access techniques that can be used. The first is time division multiplexing (TDMA), where each ONU is given a time slot where it is allowed to transmit data. The OLT controls the data transfer using message passing to each ONU to allocate it time to transmit. Ranging functions are needed to determine the distance from each ONU to the OLT to ensure proper timing. A second proposed method is sub-carrier multiple access (SCMA). SCMA has each ONU modulate their packet streams on unique electrical carrier frequencies. Another option is wavelength division multiple access (WDMA), where each ONU transmits data at a different optical wavelength. TDMA methods show the most promise because they are able to achieve high data rates with moderate complexity. Standards have been developed for several different TDMA methods. The first is the ATM PON (APON) standard that divides the data into native ATM cells. This is outlined in the G.983 standard of the ITU-T SG15. Another standard has been developed for an Ethernet PON (EPON), which carries gigabit Ethernet packets. The EPON is covered in the IEEE standard. Finally, a third standard called the Gigabit PON (GPON) has been developed that is able to send both ATM cells and Ethernet packets. These standards specify a number of different bit rates for the downstream and upstream data. These values are listed in

22 CHAPTER 1. INTRODUCTION 5 Table 1.1 along with the upstream and downstream wavelengths. Table 1.1: PON Data Transmission Rates and Wavelengths APON EPON GPON Downstream Wavelength 1500 nm 1490 nm or 1510 nm nm Upstream Wavelength 1300 nm 1310 nm nm Downstream Bit Rate 155 Mbps, 1.25 Gbps 1.25 Gbps, 622 Mbps 2.5 Gbps Upstream Bit Rate 155 Mbps 1.25 Gbps 155 Mbps, 622 Mbps 1.25 Gbps 2.5 Gbps Table 1.2 shows some important specifications from the GPON standard. The values listed in the table concern the specifications for transmitting and receiving data in the downstream direction at a bit rate of 2.5 Gbps. There are three separate classes listed. Each class has different specifications for the power launched at the transmitter, and the required sensitivity of the receiver. Class C is intended to use an avalanche photodiode (APD), which allows for a better sensitivity. Table 1.2: GPON Standard Transmitter Specifications Nominal Bit rate Mbps Operating Wavelength nm Line Code Scrambled NRZ Class A B C Mean Launched Power MIN 0 dbm 5 dbm 3 dbm Mean Launched Power MAX 4 dbm 9 dbm 7 dbm Extinction Ratio more than 10 db Receiver Specifications Bit Error Rate (BER) less than Class A B C Minimum Sensitivity -21 dbm -21 dbm -28 dbm Minimum Overload -1 dbm -1 dbm -8 dbm Consecutive Identical Digit Immunity more than 72 The transimpedance amplifier designed in chapter 4 is designed to meet this

23 CHAPTER 1. INTRODUCTION 6 GPON specification for 2.5 Gbps transmission. The transimpedance amplifier designed in chapter 5 has been designed for a bit rate of 10 Gbps and is intended for future higher speed applications Integrated Optical Transceiver While the majority of the cost of installing fiber in the access level is the digging and ducting required to run the fiber (roughly 85% [1]), there is still a lot of room to reduce the link cost. Since the transceivers at each termination represent 70-80% of the total link cost (not including the digging and ducting), the total system cost can be reduced significantly by lowering the transceiver cost. Transceivers that are currently available use a number of discrete components that add to the component cost, as well as the manufacturing cost of each transceiver. An integrated solution can significantly reduce the cost, and provide better performance because components can be optimized to work together. A two chip solution has been proposed by researchers at Queen s University and McMaster University consisting of one photonic integrated circuit (PIC) and one microelectronic integrated circuit (MIC). The PIC will integrate a wavelength multiplexer with a photodiode and laser, while the MIC will integrate the receiver and transmitter electronics onto a single complimentary metal oxide semiconductor (CMOS) integrated circuit. The receiver electronics will consist of a transimpedance amplifier (TIA), and a limiting amplifier. The transmitter electronics will consist of a pre-amplifier, and a laser driver (LD). The focus of this thesis is work on the MIC, particularly the transimpedance amplifier at the input of the receiver portion of the circuit.

24 CHAPTER 1. INTRODUCTION Challenges of CMOS Traditionally, analog circuits used in optical communication systems are implemented using Gallium Arsenide (GaAs) or Indium Phosphide (InP) technologies. These processes are designed for high speed circuits, and have been traditionally the only technologies able to produce the high bandwidth circuits required in optical communication systems. However, due to the aggressive scaling of the CMOS process, it is now becoming possible to design high performance analog circuits in CMOS. The primary advantage of moving to a CMOS process is a dramatic reduction in cost due to its widespread use in high volume digital circuits. Another advantage of using CMOS is its ability to integrate digital and analog circuits onto the same substrate. 1.3 Thesis Overview and Major Contributions This thesis focuses on the design of high speed transimpedance amplifiers in CMOS technology. The chapters of the thesis are organized as follows. Chapter two reviews the important background theory relevant to the thesis. First, some basic theory on optical receivers is presented and the role of the TIA in an optical receiver is discussed. Next, a method for estimating the sensitivity of an optical receiver is covered. Finally, the important performance specifications for a TIA are given, and some general topologies are discussed. In chapter three a literature review is presented of the current work that has been done in the area of high speed transimpedance amplifier design using CMOS technology. A number of different open loop and feedback topologies are examined and their performance is compared. A review is also done on common bandwidth extension techniques used to improve the performance of CMOS TIAs. Shunt inductive peaking, series inductive peaking, and shunt-series inductive peaking are discussed. Chapter four presents a 2.5 Gbps transimpedance amplifier fabricated using 0.18 µm

25 CHAPTER 1. INTRODUCTION 8 CMOS technology. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. The cascode topology is used to reduce the input capacitance of the amplifier and increase the bandwidth. The amplifier has been designed to be pseudo differential in order to improve the common mode rejection. This is important because the intended application of the TIA is an integrated transceiver. The differential structure will help reduce the impact of noise coupled into the TIA from other system components. The TIA also has a variable gain to increase the range of acceptable input powers such that the amplifier isn t saturated. Simulation results show a maximum transimpedance gain of 64 dbω and a bandwidth of 1.8 GHz with a photodiode capacitance of 250 ff. The average input referred noise current spectral density over the TIA bandwidth is 9.0 pa/ Hz. Using the variable gain control the TIA bandwidth can be reduced to 46 dbω. Measured results are presented for the TIA and show a good match to simulated results. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. Chapter five presents the design of a 10 Gbps transimpedance amplifier using 0.18 µm CMOS technology. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. This technique uses both a shunt and series connected inductor to create multiple resonant structures that increase the amount of current available to charge the output capacitance. Like the TIA in chapter four, this TIA has been designed to be pseudo differential in order to increase the common mode rejection ratio. The chapter begins with a discussion of the different methods of bandwidth extension using inductive peaking. The optimal configurations for maximally flat responses are shown for shunt inductive peaking, series inductive peaking, and shunt-series inductive peaking. Next, the TIA circuit

26 CHAPTER 1. INTRODUCTION 9 topology is optimized using a novel noise analysis using a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Simulation results are presented for the amplifier, and show that with inductive front-end tuning, the TIA can achieve a transimpedance gain of 45 dbω with a bandwidth of 12 GHz. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. Finally, chapter six concludes the work contained in the thesis and summarizes the results. Areas of further work are also explored.

27 Chapter 2 Background Theory 2.1 Optical Receiver - Basic Theory The most basic optical receiver consists of a photodiode and a transimpedance amplifier. The photodiode is a square law device, which means the detected electrical current depends on the power of the incident optical signal. The TIA amplifies this electrical current with sufficient bandwidth, converting it to a voltage, while adding as little noise as possible. Generally, the TIA output signal is still not large enough to reach detectable logic levels (approximately 500 mvp-p) so additional amplification is added in the form of a limiting amplifier (LA). A limiting amplifier has a high gain and a large output voltage swing. The input signal is amplified until it is saturated at the amplifier voltage rails. This has the effect of producing a reasonably constant output voltage swing for a wide range of input voltage levels. If the LA is DC coupled to the TIA, DC offset compensation is required to prevent the LA from saturating at one rail. The TIA and limiting amplifier make up what is generally called the analog front-end of the optical receiver. After the received signal has been boosted to detectable logic levels, a decision circuit is used to remove the noise from the received signal. The decision circuit is timed by a clock recovery circuit which extracts a clock signal from the received data. 10

28 CHAPTER 2. BACKGROUND THEORY 11 It is important that the clock driving the decision flip flop have a well-defined phase relationship with the received data such that the signal is sampled at the optimum point during the bit period [2]. Finally, the signal can be multiplexed down to multiple lower bit rate signals using a de-multiplexer. A block diagram of this typical optical receiver is shown in Figure 2.1. Photodiode v(t) v(t) t t Flip Flop DMUX TIA LA D Q i(t) t Offset Compensation Clock Recovery /N Figure 2.1: Basic Optical Receiver Block Diagram Receiver Sensitivity The two most important performance measures of an optical receiver are the achievable bit rate and the receiver sensitivity. The sensitivity of the receiver is measured as the minimum received optical power required to achieve a specific bit error rate (BER) (usually 10 9 or ). The BER is defined as the ratio of incorrectly detected bits to the total number of bits sent. The sensitivity of the receiver is important because it determines the maximum tolerable loss in the system which translates into a maximum link length. In long haul applications, the longest link length is important because it can reduce the number of optical amplifiers or signal regeneration units. In the context of PONs, a longer available link length can increase the number of times the optical signal is split, which can increase the number of subscribers or increase the range of individual ONUs.

29 CHAPTER 2. BACKGROUND THEORY 12 The sensitivity of a receiver can be estimated from the input signal levels and noise sources. Since the sensitivity is defined as a received optical power needed to achieve a specified BER, we will start by estimating the BER of the system for a given power level. The BER can be calculated using the following equation if we assume there is no pattern dependence and that a 1 and a 0 are equally likely [3]. BER = 1 {Prob(x = 1 0) + Prob(x = 0 1)} (2.1) 2 where x is the detected bit. The BER is equal to the probability of detecting a 1 when a 0 is sent plus the probability of detecting a 0 when a 1 is sent. The factor of one half is due to the fact that the probability of a 1 or a 0 being sent are the same. These probabilities can be calculated if we know the probability density functions for the received signal for both a 1 and a 0 being sent. If we assume a Gaussian distribution for the received signal levels for a 1 and a 0, we get the following plot shown in Figure Decision Level Probability Density Function σ 0 f 0 (x) σ 1 f 1 (x) S0 d S d Signal Level Figure 2.2: Probability Density Function

30 CHAPTER 2. BACKGROUND THEORY 13 where S d1 and S d0 are the average received signal levels for a 1 and a 0,and σ 1 and σ 0 are the variance in the received signal for a 1 and a 0. The Gaussian distribution is given below in equation 2.2. f 1 (x) = 1 2πσ1 exp [ (x S ] d1) 2 2σ 2 1 (2.2) The first term in equation 2.1 is the area under the curve corresponding to a 0 being sent that is above the decision threshold. The second term is the area under the curve corresponding to a 1 being sent that is below the decision threshold. This is shown below in equation 2.3. BER = 1 2 { 1 2πσ1 D exp [ (x S d1) 2 2σ 2 1 ] dx + 1 2πσ0 D exp [ (x S d0) 2 2σ 2 0 ] } dx (2.3) This equation can be simplified by replacing the integrals with the complementary error function which is given below. erfc(x) = 2 e u2 du (2.4) π x This substitution gives the following expression for the BER of the system shown in equation 2.5. BER = 1 { erfc 4 D S d0 2σ0 } + erfc S d1 D 2σ1 (2.5)

31 CHAPTER 2. BACKGROUND THEORY 14 We can simplify the analysis further by setting the detection level such that the probability of incorrectly detecting a 1 and a 0 are equal as shown below. D S d0 2σ0 = S d1 D 2σ1 (2.6) This results in the detection threshold shown in equation 2.7. D = σ 0S d1 + σ 1 S d0 σ 0 + σ 1 (2.7) The BER expression in equation 2.5 can now be simplified to the following expression shown below. BER = 1 2 erfc S d1 S d0 (2.8) 2(σ1 + σ 0 ) The BER is calculated for the signal at the input of the decision circuit in Figure 2.1. At this point the input signal has been amplified and noise has been added to the signal by the amplifiers. If the receiver noise is referred to the input, the BER can be calculated at the input of the receiver. This is generally what is done in practice because the gain of the amplifiers does not need to be considered. We can now define values for the signal levels and noise powers to estimate the BER for the system. We will assume that a certain optical power level P 1 is received for a 1 and an optical power P 0 is received for a 0. Ideally, there would be zero optical power received for a 0, but practically this is not the case. The GPON standard summarized in Table 1.2 specifies a minimum extinction ratio of 10 db. The extinction ratio r e is defined as the ratio of the optical power received for a 1 to the

32 CHAPTER 2. BACKGROUND THEORY 15 optical power received for a 0 as shown in equation 2.9. r e = P 1 P 0 (2.9) We will also assume that the probability of receiving a 1 and a 0 are equally likely, therefore the average received optical power P avg is the average of the optical powers P 1 and P 0. P avg = P 1 + P 0 2 (2.10) The optical powers P 1 and P 0 can be written in terms of the average optical power as shown below. P 1 = P avgr e 1 + r e (2.11) P 0 = P avg 1 + r e (2.12) The input current into the TIA for a 1 or a 0 is the received optical power multiplied by the responsivity R of the photodiode as shown in equation S d1 = 2RP avgr e 1 + r e (2.13) S d0 = 2RP avg 1 + r e (2.14) The responsivity of the photodiode is a measure of the current produced per unit optical power incident on the photodiode [3].

33 CHAPTER 2. BACKGROUND THEORY 16 The noise power during the transmission of a 1 or a 0 is a combination of the signal dependent shot noise from the photodiode, dark current, and the input referred noise current from the receiver. The signal dependent noise in the photodiode results from the randomness associated with the rate of arrival of the photons at the detector. The dark current is the portion of the current from the photodiode that is not directly related to the incident signal and is present with no light incident on the photodiode [3]. In this analysis the dark current will be neglected because it is generally small compared to the circuit noise. Expressions for the noise power of the received signal for a 1 and a 0 are shown below. σ 2 1 = 4qRP avgr e 1 + r e BI 1 + i n,in 2 (2.15) σ 2 0 = 4qRP avg 1 + r e BI 1 + i n,in 2 (2.16) The first term in equations 2.15 and 2.16 is the signal dependent shot noise. This value is derived in more detail in [3] where B is the noise bandwidth of the receiver, q is the charge of an electron, and I 1 is a term that is dependent on the received pulse shape. The value of I 1 is derived for several common pulse shapes in [3] and is generally in the range of 0.5 I 1 2. For this analysis we will choose a value of I 1 = 1. The second term in equations 2.15 and 2.16 is the mean squared input referred noise current of the receiver. The input referred noise current is the noise current that when put through the receiver, generates the appropriate noise voltage at the input of the decision circuit. Figure 2.3 shows plots of the BER vs. the average received input power for various values of the circuit noise. Typical values are chosen for the properties of the

34 CHAPTER 2. BACKGROUND THEORY 17 photodiode and receiver and are listed below. R = 0.9 A/W B = 2 GHz I 1 = 1 r e = 10 db log10(ber) i n,in 2 = 0.5 µa rms i n,in 2 = 0.7 µa rms i n,in 2 = 0.9 µa rms i n,in 2 = 1.1 µa rms i n,in 2 = 1.3 µa rms i n,in 2 = 1.5 µa rms P avg (dbm) Figure 2.3: Basic Optical Receiver Block Diagram We can see from Figure 2.3 that in order to meet the GPON specification listed in Table 1.2, the input referred noise current of the receiver needs to be less than 0.9 µa rms. The receiver noise is largely determined by the noise properties of the TIA, since the noise contribution of subsequent stages to the input referred noise current are divided by the transimpedance gain of the TIA. For a high sensitivity receiver it is important to have a low noise transimpedance amplifier with a large transimpedance gain.

35 CHAPTER 2. BACKGROUND THEORY Integrated Transceiver In the proposed integrated transceiver, crosstalk from other system components will act as an additional source of noise and will degrade the receiver sensitivity. One particular concern is the effect of the transmitter, especially the high power laser driver on the same substrate as the sensitive TIA. This is shown below in Figure 2.4 MMIC Transmitter TIA LD Re-timer Bias and Modulation Current Control Cross Talk TIA LA Clock and Data Recovery Receiver AGC Offset Compensation Figure 2.4: MIC Block Diagram for an Integrated Transceiver The large signals from the laser driver may couple into the TIA and greatly degrade the receiver sensitivity. This adds another requirement to the receiver circuitry. The receiver should add as little noise to the signal and should also have strong noise immunity. Two general methods can be used to achieve noise immunity. The electrical isolation can be increased by using isolation trenches and placing different components into separate well structures to reduce the amount of conducted noise that is coupled into the TIA. Also, circuit topologies such as a differential structure can be used to reject the noise that does reach the TIA and prevent it from being added to the signal.

36 CHAPTER 2. BACKGROUND THEORY Transimpedance Amplifiers The primary function of a TIA is to convert the small current produced by the photodiode into a voltage while adding as little noise to the output signal as possible. The circuit is therefore characterized by several properties, including transimpedance gain, group delay, and input referred noise current as shown in Figure 2.5. Z T (f) Z T (f) f f Photodiode I in TIA V out d in,in 2 df τ g (f) f f Figure 2.5: Transimpedance Amplifier The transimpedance gain of the TIA is the ratio of the output voltage to the input current. Z T (f) = V out I in (2.17) The group delay is defined as the negative of the derivative of the phase of the transimpedance with respect to frequency. τ g (f) = 1 2π [ ] d( ZT (f)) df (2.18) A flat group delay means the amplifier has a linear phase response. A flat group delay is important because variations in the group delay with frequency can cause distortions in the output signal. The distortion is significant if the variation in the group delay across the bandwidth of the amplifier is significant when compared to

37 CHAPTER 2. BACKGROUND THEORY 20 the signal bit period. Finally, the noise contribution of the TIA is characterized by the input referred noise current. The input referred noise current is the noise current that could be applied to the equivalent noiseless TIA that would produce an output noise voltage equal to that of the original noisy circuit [2]. This is shown below in Figure 2.6. v n,out 2 TIA I V out in I in in,in 2 (Noiseless) TIA (Noiseless) V out Figure 2.6: Input Referred Noise Current The input referred noise current is related to the output noise voltage by the following equation. i n,in 2 = v n,out 2 Z T 2 (2.19) The input referred noise current is used to provide a fair comparison between devices since it does not depend on the transimpedance gain of the device. The most basic TIA is shown in Figure 2.7 a) where the TIA is simply a resistor R L. The photodiode is replaced with an equivalent model in Figure 2.7 b). The photodiode model consists of an ideal current source and a photodiode capacitance. The photodiode current I in passes through the resistor and is converted to a voltage V out. The transimpedance gain is equal to the value of the load resistance R L since all of the photodiode current passes through R L [2]. One problem with this simple circuit is that it has a very fixed trade-off between gain, bandwidth and noise. The transimpedance gain as mentioned is equal to the value of R L. However, the bandwidth is determined by the RC time constant formed between R L and the photodiode capacitance C P D. The 3 db bandwidth of the circuit

38 CHAPTER 2. BACKGROUND THEORY 21 V out I in C P D R L V out R L Photodiode (a) (b) Figure 2.7: a) Photodiode and Simple Transimpedance Amplifier b) Simple Transimpedance Amplifier with Photodiode Model is given as follows [2]. f 3dB = 1 2πR L C P D (2.20) This shows that for a given photodiode capacitance the resistor R L determines the bandwidth. To achieve higher bit rates, the resistor R L needs to be reduced to increase the bandwidth, which in turn reduces the transimpedance gain. Unfortunately it can be shown that the input referred noise current is also dependent on the value of R L. Figure 2.8 shows the noise contribution from the resistor R L. The noise from the resistor is directly referred to the input such that the mean squared input referred noise current spectral density is constant and given in equation 2.21 V out I in C P D R L irl Figure 2.8: Basic Optical Receiver Block Diagram d i n,in 2 df = d i R L 2 df = 4kT R L (2.21)

39 CHAPTER 2. BACKGROUND THEORY 22 where k is the Boltzmann constant and T is the temperature in Kelvin. In order to determine the total mean squared input referred noise current, the mean squared noise current spectral density needs to be multiplied by the magnitude squared of the normalized transimpedance gain and integrated from 0 to infinity. This is shown below in equation 2.22 [3]. i n,in 2 = 1 Z T pk 2 0 d i n,in 2 Z T (f) 2 df (2.22) df In this case, the mean squared input referred noise current spectral density is constant and can be removed from the integral. i n,in 2 = d i n,in 2 1 df Z T pk 2 0 Z T (f) 2 df (2.23) The remaining portion of the equation is called the noise bandwidth of the system and is shown in equation B = 1 Z T pk 2 0 Z T (f) 2 df (2.24) The transimpedance gain Z T (f) for this system is given below in equation Z T (f) = V out I in = R L 1 + j2πfc P D R L (2.25) In this case, the maximum transimpedance, Z T pk, occurs at DC and is equal to R L. The integration results in the following noise bandwidth.

40 CHAPTER 2. BACKGROUND THEORY 23 B = 1 4R L C P D (2.26) We can now determine the total mean squared input referred noise current. i n,in 2 = kt R 2 L C P D (2.27) We can see from this equation that the input referred noise current is increased as the value of R L is decreased. Therefore, as the bit rate is increased, the value of R L is reduced in order to increase the bandwidth of the circuit. As R L is reduced, the input referred noise current is increased, and the transimpedance gain is reduced. The noise, gain, and bandwidth equations for this TIA are directly coupled. More complex structures need to be examined that reduce this trade-off. 2.3 Common TIA topologies Generally there are two types of TIA topologies, open loop TIAs and feedback TIAs [2]. The goal when designing a TIA, is to provide a low input impedance in order to meet the bandwidth requirements, while also providing low noise and high gain. The characteristics and performance of these two topologies will be discussed below Open Loop TIAs Open loop TIAs generally use common gate or common base topologies since these devices are capable of providing a low input impedance. A typical common gate

41 CHAPTER 2. BACKGROUND THEORY 24 TIA is shown in Figure 2.9. The transistor M 1 is the common gate transistor with a resistive load R D, while transistor M 2 provides a bias current. R D V out V bias M 1 I in C P D M 2 V bias Figure 2.9: Common Gate TIA Since all of the photodiode current passes through the load resistance R D, the transimpedance gain is equal to R D. The input resistance of this amplifier is given to a good approximation by [2] R in r ds 1 + R D 1 + (g m 1 + g mb 1 )r ds 1 (2.28) where r ds 1 is the drain to source resistance, g m 1 is the device transconductance, and g mb 1 is the back-gate transconductance due to the body effect. This equation assumes that drain to source resistance r ds 2 of transistor M 2 is large. For long channel devices operating in the saturation region, the value of r ds is large and this equation reduces to the following relationship, where the input resistance is only dependent on the properties of the device, and is independent of the load resistance R D. R in 1 g m + g mb (2.29)

42 CHAPTER 2. BACKGROUND THEORY 25 This is an important result because the bandwidth is independent of the transimpedance gain set by R D. In reality, if R D is increased too much, the output pole formed with the parasitic output capacitance of the common gate transistor will determine the bandwidth. The unfortunate downside of this TIA is that the noise current produced by the load resistance R D and the bias transistor M 2 are directly referred to the input with a unity factor. The noise contributions from these two sources also trade-off with each other. The load resistor can be increased in order to reduce its noise contribution. In order to maintain the proper biasing conditions, the bias current would need to be reduced which would increase the noise contribution of M 2. If the bias current is maintained, the supply voltage would need to be increased. In order to reduce the noise contribution from the bias transistor, the bias current can be increased. Again, to maintain the bias conditions, the load resistor would need to be decreased, which would increase the noise contribution from the load resistor. If the load resistor is kept the same, the supply voltage would again need to be increased to maintain the transistor in saturation. Improving the noise performance of this device comes at the cost of increased power consumption. As the supply voltage is increased, the power consumption increases quickly for a small improvement in the noise performance Feedback TIAs A more popular TIA topology is the shunt-shunt feedback structure shown in Figure An ideal inverting voltage amplifier is shown with a feedback resistance R F B. The transimpedance gain of this circuit given in the following equation [2] Z T = A A + 1 R F B 1 + jω R F BC P D A+1 (2.30)

43 CHAPTER 2. BACKGROUND THEORY 26 where A is the open loop voltage gain of the amplifier. R F B -A V out I in C P D Figure 2.10: Feedback TIA We can see that if the voltage gain, A, of the amplifier is sufficiently high, the transimpedance is approximately equal to R F B in the amplifier s passband. Assuming that the dominant pole is at the input, the bandwidth of this circuit will be given by the following expression. f 3dB A + 1 2πR F B C P D (2.31) The bandwidth of the TIA is greater than that of a simple resistive network by a factor of A+1. The noise of the feedback resistor R F B is directly referred to the input with a unity factor, while the noise from the voltage amplifier is divided by a factor of R F B. This is similar to the load resistor in the common gate amplifier, but in this case R F B doesn t carry bias current and therefore can be increased without increasing the supply voltage Bandwidth Considerations The previous section has covered two typical TIA topologies and discussed their major performance parameters. We have stated that it is important to minimize the input referred noise current and maximize the transimpedance gain to improve the sensitivity of the device. We haven t, however, discussed in detail the bandwidth

44 CHAPTER 2. BACKGROUND THEORY 27 requirements of the TIA. For this section we will assume that the signal is sent in a binary non-return to zero format (NRZ) format, which is the most common. In this format the data signal is either high or low for the entire bit period. If consecutive bits are the same, the data signal remains at the high or low state for multiple bit periods. At the point of detection, superimposed on the NRZ data signal will be broadband noise that will be a combination of noise added during transmission, signal dependent shot noise generated by the PIN photodiode, and thermal noise added by the receiver electronics. It is clear that by reducing the bandwidth of the TIA, this broadband noise can be filtered and reduced. However, limiting the amplifier bandwidth will produce inter-symbol-interference (ISI), which can also generate errors in the receiver. There is therefore a trade-off between the amount of ISI produced and the amount of noise passed by the TIA. It is not easy to determine this optimum bandwidth analytically since the TIA generally has a complex transfer function with multiple poles. Figure 2.11 shows eye diagrams of the response of a second order maximally flat butterworth filter to random data with varying bandwidth relative to the bit rate R b. It can be seen that as the bandwidth is reduced from a value equal to the bit rate down to a value equal to 0.3 times the bit rate, a significant amount of ISI is introduced. From this Figure, we can see that the bandwidth can be reduced to approximately 0.7 times the bit rate with minimal added ISI. There may be tighter restrictions on the optimal sampling time when compared to the higher bandwidth signal, but there is minimal vertical and horizontal eye closure. Another consideration is the low frequency cut-off frequency. Often, AC coupling is desired in circuit design in order to bias the transistors at their optimal bias point for either optimal gain or optimal noise performance. The biasing network will introduce a low frequency cut-off frequency. Figure 2.10 shows the effects of the low frequency

45 Output Voltage (mv) Output Voltage (mv) CHAPTER 2. BACKGROUND THEORY Time Normalized to Bit Period (b) 6 Output Voltage (mv) Output Voltage (mv) (a) Time Normalized to Bit Period Time Normalized to Bit Period (c) Time Normalized to Bit Period (d) Figure 2.11: Response of a Second Order Filter to Random Data with a Bandwidth Equal to a) Rb b) 0.7 Rb c) 0.5 Rb d) 0.3 Rb 3

46 CHAPTER 2. BACKGROUND THEORY 29 cut-off on a 2.5 Gbps random data signal. The data signal was produced by passing NRZ data through a first order high pass filter with a low frequency 3 db cut-off of 20 MHz. This cut-off frequency is not practical but is used to illustrate the effects of the low frequency cut-off frequency. The data signal has a sequence of consecutive high bits in the middle of the sequence. It can be seen that the DC level during the series of consecutive bits begins to droop. A long series of consecutive bits can significantly alter the DC level of the data, which alters the optimum threshold voltage. The GPON standard calls for the receiver to be able to tolerate 72 consecutive identical bits. A poor low frequency cut-off has the effect of vertically closing the eye, and can reduce the sensitivity of the system Output Voltage (mv) Time (ns) Figure 2.12: Response of a Filter with a Low Frequency Cut-off of 20 MHz to Random Data In order to achieve a lower low frequency cut-off, the size of the bias network components need to be increased. If these components are implemented on-chip, they can be very large and take up a considerable amount of valuable chip space. For this reason, these components are generally added externally. In this project, the goal is to produce a fully integrated transceiver on a single MIC. Since this is the case, adding external components is not desired. Instead, the TIA design will be DC coupled to avoid external biasing components. There will be a slight performance

47 CHAPTER 2. BACKGROUND THEORY 30 trade-off as the active components will not be biased at their optimum bias points.

48 Chapter 3 Literature Review 3.1 Transimpedance Amplifier Topologies Regulated Cascode TIA The basic principle of open loop TIAs was described in section A common gate structure is normally used because it has a low input impedance. By presenting the photodiode with a low input impedance, the amplifier is able to isolate the photodiode capacitance from determining the bandwidth of the system. The ability of the common gate structure to isolate the large photodiode capacitance is limited by the g m of the input transistor. In order to lower the input impedance, the size of the transistor can be increased, which raises the bias current and adds to the parasitic input capacitance. A regulated cascode (RGC) structure has been used in [4, 5, 6] to solve this problem. The regulated cascode structure is shown below in Figure 3.1. The RGC structure consists of a common gate transistor M 1 with a resistive load R 1. The resistor R S sets the bias current through the common gate transistor. The transistor M B and resistor R B create a local feedback loop that reduces input impedance of the amplifier by approximately the value of its voltage gain. The regulated cascode structure is 31

49 CHAPTER 3. LITERATURE REVIEW 32 generally used as a current buffer and is followed by a feedback transimpedance amplifier structure. By lowering the input impedance of the amplifier, the RGC structure decouples the photodiode capacitance from determining the bandwidth of the amplifier. R F B R 1 R B A V out M 1 M B R S Figure 3.1: Regulated Cascode TIA The input impedance of the RGC structure is given as follows. This approximate result neglects the body effect. R in 1 g m1 (1 + g mb R B ) (3.1) We found in section that the input resistance of a common gate amplifier was approximately equal to 1/g m (again neglecting the body effect). We can see from the result in equation 3.1 that the RGC structure has an input resistance that is a factor of 1/(1+g mb R B ) lower than the common gate structure. This RGC topology was used in [4] to create a 1.25 Gbps TIA. The RGC structure was used as a current buffer and was followed by a voltage gain stage. The TIA achieved a transimpedance of 58 dbω, with a bandwidth of 950 MHz with a photodiode capacitance of 500 ff. The TIA had an average noise current spectral density of 6.3 pa/ Hz. This same topology was used in [6] to create a 2.5 Gbps TIA. The TIA was able

50 CHAPTER 3. LITERATURE REVIEW 33 to achieve a bandwidth of 2.2 GHz, and a transimpedance gain of 55.3 dbω, with a photodiode capacitance of 500 ff. The RGC topology was also used in [5] to create a 1 Gbps differential TIA. This TIA has a 80 dbω differential transimpedance gain with a bandwidth of 670 MHz. The RGC structure was also used in the TIAs used in the optical receiver analog front-ends in [7] and [8]. In [8], the RGC structure was used in a single ended TIA with a transimpedance gain of 54 dbω, and a bandwidth of 2.5 GHz, to create a 2.5 Gbps optical receiver analog front-end. In [7], a differential structure was used to create a 10 Gbps analog front-end with a sensitivity of -12 dbm at a BER of Finally, the RGC structure was used in a tunable transimpedance amplifier in [9]. The RGC structure is used as a current buffer before a voltage gain stage that has an adjustable gain and bandwidth DC Coupled Common Gate TIA Figure 3.2 shows another type of TIA that uses a modified common gate topology. This topology was first used in [10]. I DC R T V out M 2 M 1 R B Figure 3.2: DC Coupled Common Gate TIA The importance of DC coupling in avoiding baseline wander has been discussed

51 CHAPTER 3. LITERATURE REVIEW 34 in section In a DC coupled common gate TIA, a significant change in the DC input current can alter the bias point of the common gate transistor and affect the performance of the amplifier. Variations in the DC input current will also lead to changes in the DC output voltage which may also affect the next stage of the system. The topology in [10] avoids this problem by using a current mirror to ensure the bias current in the common gate structure is constant. The resistor R B sinks any additional input current. This topology is not used as a current buffer and the resistor R T sets the transimpedance gain as long as R B is sufficiently large. The size of the transistor M 2 is minimized such that the majority of the signal current flows through the common gate transistor M 1. Since the transistor is minimally sized, it adds minimal capacitance to the input and also contributes very little noise. A number of TIAs have been demonstrated using this topology. A TIA was designed in [10] using a 0.25 µm CMOS process that achieved a transimpedance bandwidth of 42.9 dbω, and a bandwidth of 8.4 GHz. The measured input referred noise current is equal to 14.6 pa/ Hz. A second TIA was designed using a 47 GHz SiGe HBT process that achieved a transimpedance gain of 47.3 dbω, and a bandwidth of 9.8 GHz. The measured input referred noise current for this TIA is equal to 12.0 pa/ Hz. Two TIAs with similar performance are also reported in [11]. A 25 Gbps TIA has also been designed using this topology in [12]. This TIA was designed in a 0.13 µm CMOS process and achieves a transimpedance gain of 42 dbω and a 15 GHz bandwidth. This topology has also been used in several high speed optical receiver analog front-ends. A 10 Gbps optical receiver analog front end has been reported in [13]. This modified common gate structure was used in a differential configuration with a shunt peaking inductor to further improve the bandwidth. The receiver was able to achieve a sensitivity of dbm with a BER of at a bit rate of 10 Gbps.

52 CHAPTER 3. LITERATURE REVIEW 35 A 17 Gbps optical receiver analog front-end has been reported in [13]. A receiver sensitivity of dbm achieved with a BER of at a bit rate of 12.5 Gbps. The bit rate of 12.5 Gbps was the limit of the BER test equipment used, but an open eye was shown for a 17 Gbps signal Feedback TIAs A number of different feedback topologies have been reported in the literature. Figure 3.3 shows the most common feedback structures. Figure 3.3 a) shows a shuntshunt feedback topology with a common source gain stage. The transistor is loaded with a resistor for broadband amplification. A source follower is used to isolate the load resistor from the feedback resistance. Figure 3.3 b) shows a similar topology, but with a cascode gain stage instead of a common source gain stage. By placing a common gate transistor between the common source transistor and the load, the Miller effect is reduced and the input capacitance of the TIA is reduced. Finally Figure 3.3 c) shows a feedback TIA that uses a CMOS inverter as the gain stage. By using the pmos transistor, this topology is capable of a high gain but suffers from the large parasitics of the larger pmos transistor as well as the Miller effect [14]. R D R D M 2 M 2 M 2 M 1 Vout M 2 V out R F B Vout R F B M 1 M 1 R F B (a) (b) (c) Figure 3.3: Feedback TIA Topologies a) Common Source b) Cascode c) CMOS Inverter A 2.5 Gbps optical receiver has been designed in [15]. The optical receiver uses

53 CHAPTER 3. LITERATURE REVIEW 36 a TIA with a shunt-shunt feedback topology that uses a resistive loaded common source gain stage. The feedback resistance is created using transistors operating in the linear mode. This allows for the gain to be adjusted. This TIA is able to achieve a bandwidth of 5.9 GHz and a transimpedance gain of 59 dbω. The optical receiver is able to operate with a minimum input current amplitude of 30 µap-p. A 5 Gbps TIA has been reported in [16]. This TIA uses a shunt-shunt feedback topology and uses a cascode gain stage to reduce the Miller effect. A source follower buffer is used on the output to isolate the resistor in the gain stage from the feedback resistance. This TIA was able to achieve a bandwidth of 2.6 GHz with a photodiode capacitance of 200 ff. The transimpedance gain was 58.7 dbω and the average input referred noise current density was 13 pa/ Hz A 10 Gbps TIA was designed using the CMOS inverter topology in [17]. Multiple CMOS inverter stages were cascaded using series inductive peaking. This design will be discussed in greater detail in section Bandwidth Extension Shunt Peaking Shunt inductive peaking has long been used as a technique for extending the bandwidth of a circuit. Figure 3.4 a) shows a common source amplifier with shunt inductive peaking. If the dominant pole of the amplifier is at the output, the inductor adds a pole and a zero to the frequency response, as shown in equation 3.2. V out V in = g m R D 1 + jωr D C L ω 2 LC L (3.2) This technique was first used to extend the bandwidth of a CMOS TIA using

54 CHAPTER 3. LITERATURE REVIEW 37 L L C ind R D R S R D M 1 C L M 1 C L (a) (b) Figure 3.4: Shunt Inductive Peaking a) Ideal b) Inductor Model on-chip inductors in [18]. It was shown in this paper that the bandwidth of this type of circuit could be extended as much as 85%. This maximum bandwidth comes at the cost of peaking in the frequency response and the group delay. For a maximally flat frequecy response it was shown that a 72% increase in bandwidth could be achieved. If a maximally flat group delay is required, a bandwidth extension of 60% can be achieved. The theory of shunt inductive peaking will be discussed further in chapter 5. These bandwidth improvements are for the ideal case shown in figure 3.4 a), a more realistic model is shown in figure 3.4 b), which includes the parasitic components of an on-chip inductor. The advantage of shunt inductive peaking is that the Q value of the on-chip inductor is not important since the series resistance of the inductor can be incorporated by adjusting the value of the resistor R D. It is important to minimize the size of the inductor to reduce the parasitic capacitance. Therefore, the minimum trace width should be used that meets the current density rules for the metal [18]. A number of TIAs have been designed using shunt inductive peaking [7, 9, 19, 20]. Shunt inductive peaking is also frequently used in output buffers to drive a large offchip load capacitance [5, 12].

55 CHAPTER 3. LITERATURE REVIEW Series Inductive Peaking Another bandwidth extension technique is series inductive peaking. By placing an inductor in series with a capacitive load, a resonant circuit is created which will pull more current into the load capacitance, improving the speed. As with shunt inductive peaking, the increase in bandwidth results in a peak in the frequency response. Again, the inductor can be selected to produce a maximally flat frequency response or group delay with a slightly reduced bandwidth. A more detailed analysis of series inductive peaking will be done in chapter 5. Series inductive peaking has been used to design a 10 Gbps TIA in 0.18 µm CMOS technology in [17]. The TIA uses a multi-stage amplifier with series inductive peaking between stages as shown in Figure 3.5. The series inductors increase the bandwidth of each individual stage. An added benefit is that the bandwidth is not degraded when stages are cascaded as would be the case if series inductive peaking was not used V out Figure 3.5: TIA Using Series Inductive Peaking Each gain stage consists of a CMOS inverter with resistive feedback. Normally this topology is not capable of high bandwidths due to the large parasitic capacitance added by the pmos transistor. However, the series inductors absorb the parasitic capacitance between the stages and increase the bandwidth. The series inductors combine with the parasitic capacitances to create a 3rd order LC ladder filter structure. It was found that a poor match at the input and the output could produce

56 CHAPTER 3. LITERATURE REVIEW 39 poor performance. M-derived half circuits were used as matching networks at the input and output. A simulation was done to show that the five stage amplifier was able to produce a bandwidth three times higher than the amplifier with no inductive peaking. The TIA reported in [17] achieved a transimpedance gain of 61 dbω with a bandwidth of 7.2 GHz and an average input referred noise current density of 8.2 pa/ Hz Shunt and Series Peaking A combination of shunt and series peaking can be used to further extend the bandwidth of a circuit. This principle has been demonstrated in [21]. Figure 3.6 shows a common source amplifier with shunt and series inductive peaking. The inductors create multiple resonant structures that improve the bandwidth of the circuit. Unlike shunt or series peaking alone, there is still a certain amount of peaking in the frequency response and group delay using the optimal component values. The peaking, however, is reduced by the finite Q of on-chip spiral inductors. Shunt and series peaking is analyzed in more detail in chapter 5. L 1 R D L 2 M 1 C L Figure 3.6: Shunt and Series Inductive Peaking This article demonstrates the advantage of shunt and series peaking in broadband

57 CHAPTER 3. LITERATURE REVIEW 40 circuits. Often, the gain of a broadband circuit is compromised to obtain a large bandwidth. This has led to the use of distributed amplifiers (DAs) and cascaded amplifiers to get past this trade-off between gain and bandwidth. Distributed amplifiers absorb the parasitic capacitances of the gain stages in either artificial or high impedance transmission lines at the input and output of the amplifier. The total amplifier gain is roughly the sum of the gains from each stage. There are several drawbacks to distributed amplifiers. Since all of the bias current for the gain stages flows through the same loads, there is a severe trade-off between gain and voltage headroom. Also, the finite output resistance of short channel devices can add significant loss to the output transmission line. The loss in the transmission lines limits the length of the line, the number of stages, and ultimately the maximum gain that can be achieved [21]. In a cascaded amplifier, the gain of each stage is multiplied. However, the total bandwidth is reduced as the stages are cascaded, and the bandwidth of each stage needs to be significantly higher than the system bandwidth. Shunt and series inductive peaking can be used to extend the bandwidth of each stage and make broadband cascaded amplifiers possible. An amplifier was designed in [21] that cascaded 5 differential pair gain stages using shunt and series inductive peaking. The bandwidth of the amplifier with shunt and series inductive peaking was approximately 3.5 times larger than the bandwidth of the amplifier without inductive peaking. The final amplifier was able to achieve a differential gain of 15 db and a bandwidth of 22 GHz using 0.18 µm CMOS technology.

58 Chapter Gbps Transimpedance Amplifier Design 4.1 Introduction This chapter presents the design of a 2.5 Gbps transimpedance amplifier designed to meet the GPON specifications given in Table 1.2. Based on the analysis shown in section 2.3 and chapter 3, a shunt-shunt feedback topology was chosen for this TIA design. This is because the TIA is being designed for an integrated system with a specific photodiode. This means the TIA doesn t need to be able to function with a range of photodiode capacitances and an open loop TIA is not required. By using a feedback topology, a higher sensitivity will be achieved. 4.2 The Cascode Structure The first step in the design was to choose an appropriate gain stage to replace the ideal voltage gain stage shown in Figure The important performance specifications for the amplifier are a high gain, large bandwidth, low noise, and low input capacitance. Two topologies were considered for this design, a common source configuration 41

59 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 42 and a cascode configuration. These two configurations are shown in Figure 4.1. The common source transistor has a resistive load for broadband amplification. The cascode configuration also has a common source transistor at the input. The common source transistor is cascaded with a common gate transistor and a resistive load. R D R D V out V out M 2 V in M 1 V in M 1 (a) (b) Figure 4.1: a) Common Source Amplifier b) Cascode Amplifier Miller Effect One of the issues to consider when comparing the two topologies is the effect of the Miller capacitance. Figure 4.2 shows a small signal equivalent model of the common source configuration. The gate to drain capacitance C GD, known as the Miller capacitance, is connected between the input and output. The gate to drain capacitance is formed as a result of the overlap between the gate and the drain caused by lateral diffusion of the drain under the gate. For short gate length devices, this overlap capacitance is significant compared to other parasitic capacitances and is important to consider. Miller s theorem allows this capacitance to be replaced with shunt capacitances at the input and output [22]. Miller s theorem can be derived by looking at the general example in Figure 4.3. A series admittance is connected between two points with a known voltage gain of K. In order to replace this series admittance with shunt

60 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 43 G R G C GD D V gs C GS g m V gs C DS r ds RL S Figure 4.2: Common Source Equivalent Circuit admittances at the input and the output, the currents I 1 and I 2 must remain constant during the transformation. I 1 I 2 Y I 1 I 2 V 1 V 2 = KV 1 V 1 Y 1 Y 2 V 2 = KV 1 Figure 4.3: Miller Theorem In the first diagram with the series admittance, we can write the following for the currents I 1 and I 2. I 1 = (V 1 V 1 K)Y = V 1 (1 K)Y (4.1) I 2 = (V 1 K V 1 )Y = V 1 (K 1)Y (4.2) We can now equate these currents to the currents in the second diagram. I 1 = V 1 Y 1 = V 1 (1 K)Y (4.3) I 2 = KV 1 Y 2 = V 1 (K 1)Y (4.4)

61 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 44 The values of the shunt admittances can now be determined and are shown below. Y 1 = Y (1 K) (4.5) Y 2 = Y (1 1/K) (4.6) This is an interesting result because as the gain is increased, the input capacitance of the amplifier is increased. This reduces the magnitude of the input pole and reduces the bandwidth of the TIA. In the next section we will look at how this effect can be reduced Cascode vs. Common Source The low frequency voltage gain of the common source transistor can be calculated using the small signal model in Figure 4.2. The voltage gain is given in the following formula V out V in = g m (r ds //R L ) (4.7) where g m is the transconductance of the transistor, r ds is the drain to source resistance of the transistor in saturation, and R L is the load resistance. If we assume that r ds R L we can approximate the voltage gain as follows. V out V in = g m R L (4.8) The voltage gain across the common source transistor is directly proportional to the load resistance R L. In the case of the common source gain stage, R L is equal

62 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 45 to the load resistance R D. In the cascode configuration, the load R L is equal to the input resistance of the common gate transistor. The input resistance of a common gate transistor was shown in section to be as follows. R in 1 g m + g mb (4.9) In a resistively loaded common source configuration, the load resistor R D sets the voltage gain across the common source transistor. The cascode configuration minimizes the Miller effect by placing a common gate transistor in series with the common source transistor. The common gate transistor presents the common source transistor with a low input impedance which reduces the voltage gain across the common source transistor and reduces the Miller capacitance. The common gate transistor however, acts as a current buffer and passes the current from the common source transistor through to the load resistor resulting in the same gain as the resistive loaded common source amplifier. This is an ideal result as the gain will be lowered slightly if the value of the drain to source resistance r ds is low. The cascode and common source amplifiers have same gain, but the cascode will have a lower input capacitance. The downside of the cascode configuration is that it requires a higher supply voltage to maintain the same gain as the common source topology, and there will be a small noise contribution from the common gate transistor Gbps TIA Design For the reasons described above, a cascode gain stage was chosen for the TIA. The schematic for the input transimpedance stage of the amplifier is shown in Figure 4.4. A source follower was added to isolate the load resistance R D from the feedback

63 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 46 resistor R F B as well as the capacitance of the next stage. R D R D M 3 M 3 V bias M 2 M 2 V bias OUT+ R F B M 1 M 1 R F B OUT- IN+ IN- I 2 I 1 I 2 Figure 4.4: Differential Cascode TIA The TIA has been designed to be pseudo differential. The TIA is not truly differential because the photodiode is single ended and is only connected to one side of the differential structure. The purpose of using a pseudo differential structure is to improve the common mode rejection of the device. The intended application of this TIA is to be integrated on the same substrate as other transceiver components. By making the structure differential the input referred noise current is increased by a factor of 2. However, since there is significant cross-talk expected, the increase in common mode rejection will outweigh this penalty Variable Gain In order to avoid saturating the amplifier when a high powered signal is applied, the TIA was designed to have a variable gain. The gain can be varied by adjusting the value of the feedback resistance by placing a transistor operating in the linear mode in parallel with the feedback resistor R F B as shown in Figure 4.5. As the gate voltage of

64 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 47 the transistor is increased, the transistor is turned on and begins to conduct, reducing the value of the total feedback resistance. The tuning range is determined by the on resistance of the transistor. The larger the transistor is, the smaller the on resistance will be. This is a problem for this circuit because the parasitic diffusion capacitance of the transistor will increase the input capacitance of the TIA. In order to avoid this problem, the transistor is isolated from the input with a resistor. R D R D M 3 M 3 V bias M 2 M 2 V bias OUT+ R F B 2 R F B 1 M 1 M 1 R F B 1 R F B 2 OUT- AGC IN+ IN- AGC I 2 I 1 I 2 Figure 4.5: Cascode TIA with AGC The feedback network consists of two series resistors, with one connected in parallel with a transistor. When the transistor is turned on, the value of R F B 2 is shorted by the transistor, reducing the feedback network to approximately R F B 1. The range of the variable gain is set by the relative values of R F B 1 and R F B1 2, as well as the size of the transistor Final Schematic The final schematic for the 2.5 Gbps TIA is shown in Figure 4.6. A voltage gain stage was added after the transimpedance stage. This stage uses a simple resistive loaded differential pair. Also, for measurement purposes, an output buffer has been added to the TIA. The output buffer is also a resistive loaded differential pair with an output impedance that is matched to 50 Ω.

65 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 48 RD 1 RD 1 M3 M3 RD 2 RD 2 RD 3 RD 3 OUT+ M2 M2 IN- OUT- M5 M5 RF B 1 RF B 2 M1 M1 M4 M4 MAGC MAGC RF B 1 RF B 2 I1 I2 I2 I3 I4 IN+ AGC Figure 4.6: 2.5 Gbps TIA Final Schematic Table 4.1: 2.5 Gbps TIA Component Values Transistor Sizes Component M 1 M 2 M 3 M 4 M 5 M AGC Value (2.5 µm Fingers) Resistor Values Component R D 1 R D 2 R D 3 R F B 1 R F B 2 Value 256 Ω 228 Ω 50 Ω 100 Ω 700 Ω Current Source Values Component I 1 I 2 I 3 I 4 Value 6.3 ma 3 ma 7.3 ma 11 ma

66 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 49 Table 4.1 documents the component values used including the transistor sizes, the resistor values, and the bias currents for each stage. The current sources were implemented using current mirrors. These devices were not shown in Figure 4.6 for simplicity, but a sample circuit is shown in Figure 4.7. I out R bias M 1 M 2 Figure 4.7: Current Mirror A photo of the final chip is shown in Figure 4.8 and the final layout is shown in Figure 4.9. The total chip has an area of 730 µm by 610 µm, including the input and output pads. It can be seen that even though the amplifier is only pseudo differential, a set of dummy pads and a transmission line have been used for the unconnected input to ensure the amplifier is symmetrical and to allow for differential S-parameter characterization. It is important that the amplifier layout is symmetrical in order to achieve a high common mode rejection ratio (CMRR). A dummy capacitance will need to be added on the input to simulate the photodiode capacitance. 4.4 Simulation Results The final 2.5 Gbps TIA was simulated with Agilent s Advanced Design System (ADS) using transistor models provided by the Taiwan Semiconductor Manufacturing Company (TSMC). In order to account for the effects of the transmission lines and pads, Agilent s Momentum simulator was used to do an electromagnetic (EM) simulation

67 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN µm 730 µm Figure 4.8: 2.5 Gbps TIA Chip Photo of the top metal layer. Ports were added at the pads and at the ends of the coplaner waveguides. The active components were then connected to the ports and a co-simulation was done. Simulating the transimpedance amplifier without the effect of the photodiode is not very useful. It is important to estimate the transimpedance gain with the effects of the photodiode capacitance. Photodiode capacitances are generally between 100 ff and 500 ff [2]. An ideal capacitance of 250 ff was added to the input of the TIA as shown in Figure A dummy capacitance was also added to the other TIA input to maintain the symmetry of the differential circuit. The results of this simulation are shown in Figure Figure 4.11 a) shows the transimpedance gain with different values of the AGC voltage. The TIA has a maximum transimpedance gain of 64 dbω and a corresponding transimpedance bandwidth of 1.8 GHz. This works out to approximately 0.72 times the bit rate of

68 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 51 Figure 4.9: 2.5 Gbps TIA Chip Plot

69 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 52 I in V out I P D C P D TIA 50Ω C dummy 50Ω Figure 4.10: Simulation Setup 2.5 Gbps which is near the optimum value discussed in section The average input referred noise current spectral density corresponding to the maximum gain is approximately 9.0 pa/ Hz. Transimpedance (dbω) AGC=0.0 V AGC=2.4 V AGC=2.5 V AGC=2.6 V AGC=3.0 V Frequency (Hz) (a) Input Referred Noise Current Density (pa Hz) AGC=0.0 V AGC=2.4 V AGC=2.5 V AGC=2.6 V AGC=3.0 V Frequency (Hz) (b) Figure 4.11: Simulated Transimpedance Gain and Input Referred Noise Current - C P D = 250 ff a) Transimpedance Gain b) Input Referred Noise Current The results show that the transimpedance gain can be lowered to 46 dbω when an AGC voltage of 3.0 V is applied. Results are also shown for a number of intermediate AGC voltages. It can be seen that as the gain is reduced, the bandwidth of the amplifier is increased. This is because, as the AGC voltage is increased, the total resistance of the feedback network is reduced. This raises the value of the input pole created by the feedback resistance and the photodiode capacitance. We can see in

70 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 53 Figure 4.11 b) that as the AGC voltage is increased, the input referred noise current is increased. This is because the transistor M AGC is now conducting and contributing noise current that is directly referred to the input, and the bandwidth of the amplifier is increased which allows more noise into the system. Ideally, the input referred noise current would be held constant, but this is not a major problem for the system, as in practice the gain is only lowered in the presence of a high powered input signal. In this situation the signal power is high enough to achieve a low BER. We can estimate the sensitivity of the receiver based on these results using the same procedure shown in section In order to determine the input referred noise current we can integrate the output noise voltage spectral density with respect to frequency, and divide by the peak transimpedance gain as shown below. i n,in 2 = 1 Z T pk 2 0 d v n,out 2 df (4.10) df The result of this integral is estimated using a numerical integration from 0 to 50 GHz. Simulation data for the output noise voltage spectral density was created up to 50 GHz with data points spaced every 10 MHz. The root mean squared input referred noise current was found to be µa rms when the AGC voltage was set to 0.0 V. When the AGC voltage was set to 3.0 V, the root mean squared input referred noise current was increased to 2.55 µa rms. Figure 4.12 shows the BER plots with these values for the input referred noise current. For these calculations, a photodiode responsivity of 0.9 A/W was used, the pulse shape dependent term I 1 was set to 1, and the extinction ratio r e was set to 10 db. We can see that the sensitivity is approximately 7 db lower with an AGC of 3.0 V. However, since the difference in the transimpedance gain is 18 db, if we assume the

71 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 54 0 AGC = 0.0 V AGC = 3.0 V 5 log(ber) P avg (dbm) Figure 4.12: Estimated BER for the 2.5 Gbps TIA TIA output voltage is held constant, we would expect the photodiode current to be at least 18 db higher when the AGC is equal to 3.0 V. V out I in V out I in I in I in = 64 dbω (4.11) = 46 dbω (4.12) = 18 db (4.13) The photodiode current is related to the input optical power by the responsivity of the photodiode. An 18 db increase in the photodiode current corresponds to an 18 db increase in the average input optical power. I in = RP avg (4.14) I in = RP avg (4.15) I in P = avg = 18 db (4.16) I in P avg

72 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 55 This shows that the performance will meet the specified GPON sensitivity requirement of -21 dbm shown in Table Measured Results Measurement Setup The complete four port S-parameters for the 2.5 Gbps TIA were measured using onwafer probing with an HP8510 two port vector network analyzer (VNA). In order to obtain the four port S-parameters, six separate measurements needed to be made. The two port S-parameters were measured between each of the ports on the TIA while terminating the unconnected ports with 50 Ω terminations. The full set of four port S-parameters was later combined from these six measurements. Each of the measurements were taken over a frequency span of 45 MHz to 40 GHz with a total of 801 points. In order to characterize the TIA s transimpedance gain and group delay under practical situations, some post processing of the measured S-parameters was required. The four port S-parameters were loaded into Agilent s ADS as a dataset. Once the S- parameters were loaded, ideal capacitances representing the photodiode capacitance and the corresponding dummy capacitance were added in simulation. Figure 4.13 shows this post processing setup. The TIA was terminated at the outputs using ideal terminations. An AC simulation was then run to calculate the TIA s transimpedance gain and group delay using different photodiode capacitances Transistor Model Verification In order to verify the transistor model used in the simulation results against fabricated data, a 30 finger transistor was fabricated and measured in the common source configuration for a number of different bias conditions. Due to a lack of available

73 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 56 Ideal Ideal V out I in C P D 4 Port Measured 50Ω S Parameters C dummy 50Ω Figure 4.13: Simulation Setup chip space, de-embedding structures were not fabricated and the effects of the pads and short transmission lines were de-embedded using EM simulations performed with Agilent s Momentum EM software. Figures 4.14 and 4.15 show the de-embedded measured results of the 30 finger common source transistor with a gate bias of V g = 0.8 V and V g = 1.2 V respectively. The measured results are compared to the models obtained from TSMC. Results for the three RF corner cases are shown, Slow/Slow, Typical/Typical, and Fast/Fast. The RF corner cases are statistically determined to cover the effects of process variations. The Slow/Slow model represents the worst case performance based on the process variations and the Fast/Fast model represents the best case performance. The Slow/Slow model refers to the slow nmos model and the slow pmos model. Since this design only uses nmos transistors we will now refer to the three corner cases as simply slow, typical, and fast. These results show that for frequencies below 5 GHz, the slow model is the most consistent with the measured results. At higher frequencies, the typical model seems more accurate when compared to the measured results. From these results we can expect better agreement between the measured TIA results and the simulated results if the slow model is used.

74 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 57 Simulated FF Model Simulated TT Model Simulated SS Model Measured S11 S12 (db) Simulated FF Model Simulated TT Model Simulated SS Model Measured Frequency (GHz) (a) Simulated FF Model Simulated TT Model Simulated SS Model Measured (b) Simulated FF Model Simulated TT Model Simulated SS Model Measured S21 (db) 6 4 S Frequency (GHz) (c) (d) Figure 4.14: S-Parameters for a 30 Finger Common Source Transistor V d = 1.8 V, V g = 0.8 V

75 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 58 Simulated FF Model Simulated TT Model Simulated SS Model Measured S11 S12 (db) Simulated FF Model Simulated TT Model Simulated SS Model Measured Frequency (GHz) (a) Simulated FF Model Simulated TT Model Simulated SS Model Measured (b) Simulated FF Model Simulated TT Model Simulated SS Model Measured S21 (db) 6 4 S Frequency (GHz) (c) (d) Figure 4.15: S-Parameters for a 30 Finger Common Source Transistor V d = 1.8 V, V g = 1.2 V

76 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN Transimpedance Measurements Figures 4.16 a) and b) show the measured transimpedance gain of the 2.5 Gbps TIA with an ACG voltage of 0.0 V (Maximum Gain). Figure 4.16 a) shows the raw measured data without an external input capacitance and Figure 4.16 b) shows the transimpedance gain with a 250 ff input capacitance connected to the input to simulate the effects of the photodiode capacitance. The Figures also show the simulated results using the three corner models. As expected, based on the results for the 30 finger transistor, the slow model shows the best agreement with the measured results. Transimpedance (dbω) Simulated FF Simulated TT 30 Simulated SS Measured Frequency (Hz) (a) Transimpedance (dbω) Simulated FF 30 Simulated TT Simulated SS Measured Frequency (Hz) (b) Figure 4.16: Simulated vs. Measured Transimpedance a) C P D = 0 ff b) C P D = 250 ff Figures 4.17 and 4.18 show the transimpedance gain as the AGC voltage is adjusted from 0.0 V to 3.0 V. Figure 4.17 shows the transimpedance gain with no input capacitance, Figure 4.18 shows the transimpedance gain with an external input capacitance of 250 ff. Both plots show simulated results using the slow corner model only.

77 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 60 Transimpedance (dbω) Simulated AGC=0.0 V Measured AGC=0.0 V Simulated AGC=2.4 V Measured AGC=2.4 V Simulated AGC=2.5 V Measured AGC=2.5 V Simulated AGC=2.6 V Measured AGC=2.6 V Simulated AGC=3.0 V Measured AGC=3.0 V Frequency (Hz) Figure 4.17: Simulated and Measured Transimpedance Gain with Various AGC Voltages - C P D = 0 ff Transimpedance (dbω) Simulated AGC=0.0 V Measured AGC=0.0 V Simulated AGC=2.4 V Measured AGC=2.4 V Simulated AGC=2.5 V Measured AGC=2.5 V Simulated AGC=2.6 V Measured AGC=2.6 V Simulated AGC=3.0 V Measured AGC=3.0 V Frequency (Hz) Figure 4.18: Simulated and Measured Transimpedance Gain with Various AGC Voltages - C P D = 250 ff

78 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN Group Delay Measurements Another important parameter to measure is the group delay of the TIA. It is important to have a constant group delay in the signal band. A flat group delay implies linear phase which means there is no distortion of the signal. The group delay is defined in equation 4.17 below as the negative of the derivative of the phase of the TIA with respect to frequency. The measurement of the group delay is challenging as it is the derivative of the phase, so any sudden change in the phase will result in a large spike in the group delay. Figures 4.19 a) and 4.20 a) show the measured phase of the TIA with an AGC of 0.0 V and 3.0 V respectively. Due to measurement noise, the phase measurement has a number of sharp variations. In order to get a reasonable plot of the group delay, the phase curve was smoothed using post processing before the derivative was taken. The smoothed phase is shown in the figures along with the simulated curves. Figures 4.19 b) and 4.20 b) show the resulting group delay after the phase was smoothed. τ g = dφ dω (4.17) 3 2 Simulated Measured Smoothed Simulated Measured (Smoothed) Phase (rad) Group Delay (ps) Frequency (GHz) (a) Frequency (GHz) (b) Figure 4.19: Simulated vs. Measured Phase and Group Delay - AGC = 0.0 V a) Phase b) Group Delay

79 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN Simulated Measured Smoothed 200 Phase (rad) Group Delay (ps) Frequency (GHz) (a) 0 Simulated Measured (Smoothed) Frequency (GHz) (b) Figure 4.20: Simulated vs. Measured Phase and Group Delay - AGC = 3.0 V a) Phase b) Group Delay The bit period for a 2.5 Gbps signal is equal to 400 ps. The variation in the group delay over the band of interest should be significantly less than a bit period to ensure minimal distortion of the signal. The variation in the group delay for the TIA with an AGC voltage of 0.0 V is less than 10 ps and the variation is the group delay with an AGC voltage of 3.0 V is less than 25 ps Noise Measurements Since the input referred noise current is not physical, it cannot be directly measured. Instead, the noise properties of the TIA can be characterized in terms of the following noise parameters [26]. F min R n Y opt = (G opt + jb opt ) - Minimum Noise Factor - Equivalent Noise Resistance - Optimum Source Admittance Using these noise parameters, the noise properties of the system can be calculated with different input impedances. The Y opt term is the input impedance that results in

80 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 63 the minimum noise figure F min. Using these parameters we can derive an expression for the input referred noise current density. We will start with the noise representation shown in Figure The TIA is represented by a noiseless two-port network with the noise referred to the input. The photodiode in the system is represented by a noise source and a source impedance Y S. Photodiode TIA v n Noiseless i diode Y S i n Two-Port Network Figure 4.21: Noisy Two-port Network Representation We wish to convert this representation to the one shown in Figure 4.22, where i in is the input referred noise current. Photodiode TIA i diode i in Two-Port Noiseless Y S Network Figure 4.22: Simplified Noisy Two-port Network Representation From the representation shown in Figure 4.21, we can calculate the total short circuit current as follows. i sc = i diode + i n + v n Y S (4.18)

81 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 64 We can now determine the total mean squared short-circuit noise current spectral density. d i sc 2 df = d i diode 2 df + d i n + v n Y S 2 df 2 d(i diode (i n + v n Y S )) df (4.19) Since the noise from the photodiode and the noise from the TIA are not correlated, the third term in this expression is equal to zero. We can now write the expression for the total mean squared short-circuit noise current spectral density. d i sc 2 df = d i diode 2 df + d i n + v n Y S 2 df (4.20) In this equation the second term is the mean squared input referred noise current spectral density. d i n,in 2 df = d i n + v n Y S 2 df (4.21) Since the two noise sources i n and v n are correlated, we can separate i n into the portion that is correlated i nc, and the portion that is uncorrelated i nu. The correlated source is related to the source v n using the correlation admittance i nc = Y cor v n [26]. d i n,in 2 df d i n,in 2 df = d i nu + i nc + Y S v n 2 df = d i nu + (Y cor + Y S )v n 2 df (4.22) (4.23)

82 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 65 Next, we can express the noise voltage in terms of an equivalent noise resistance R n and the uncorrelated noise current in terms of an equivalent noise conductance G u as follows d i nu 2 df d v n 2 df = 4kT 0 G u (4.24) = 4kT 0 R n (4.25) where k is the Boltzmann constant, and T 0 is the temperature in Kelvin. By substituting these expressions into equation 4.23 we can get the following expression for the input referred noise current density. The units of the input referred noise current will be A/ Hz. d i n,in 2 df = 4kT 0 G u + G S + jb S + G cor + jb cor 2 4kT 0 R n (4.26) where the uncorrelated noise conductance G u and the correlation admittance Y cor can be written in terms of the noise parameters as shown below. G cor = F min 1 2R n G opt (4.27) B cor = B opt (4.28) G u = (G 2 opt G2 cor )R n (4.29) The noise parameters of the device were measured using the technique described in appendix B. The noise figure of the device at a given source impedance is given as.

83 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 66 F = F min + R n G s Y s Y opt 2 (4.30) The noise parameters can be determined mathematically with noise figure measurements at a minimum of four unique source impedances. An impedance tuner is used to present the TIA with a number of different input impedances and the noise figure of the device is measured at each input impedance. Figure 4.23 shows the measured noise parameters and the calculated input referred noise current spectral density of the TIA with the AGC voltage set to 0.0 V. The measured data is compared with data simulated using Agilent s ADS software. As with the transimpedance data, the slow transistor model was used. A significant amount of variation is shown in the results. This is a result of the uncertainty in the noise figure measurements as well as the uncertainty in the measurement of the input impedance. The data follows the trends in the simulated data. Figure 4.24 shows the measured noise parameters and the calculated input referred noise current spectral density of the TIA at an AGC voltage of 3.5 V (minimum gain). Again the results show significant variance due to the measurement uncertainty. The results again follow the trends in the simulation Common Mode Rejection Ratio Measurement The common mode rejection ratio (CMRR) is a measure of the TIA s ability to reject common mode signals. This is important for this amplifier because its intended application is in an integrated system where there will be crosstalk generated by the other circuits on the same substrate. Cross talk from other circuits coupled into the TIA should mostly be common mode signals. If the TIA has a large CMRR, it means it will be able to reject these signals and they won t be added to the amplified signal. In order to calculate the CMRR, the equivalent differential and common mode two port S-parameters need to be calculated from the measured four port S-parameters [23].

84 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN Simulated Measured Fmin 6 4 Γopt 2 Rn (Ω) Frequency (GHz) (a) 200 Simulated Measured Frequency (GHz) (c) Equivalent Noise Current Density pa/ Hz Simulated Measured (b) Simulated Measured Frequency (GHz) (d) Figure 4.23: TIA Noise measurements AGC = 0.0 V a) Minimum Noise Factor F min b) Optimum Source Reflection Coefficient Γ opt c) Equivalent Noise Resistance R n d) Input Referred Noise Current Spectral Density

85 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN Simulated Measured 18 Fmin Γopt 12 Rn (Ω) Frequency (GHz) (a) 300 Simulated Measured Frequency (GHz) (c) Equivalent Noise Current Density pa/ Hz Simulated Measured (b) Simulated Measured Frequency (GHz) (d) Figure 4.24: TIA Noise measurements AGC = 3.5 V a) Minimum Noise Factor F min b) Optimum Source Reflection Coefficient Γ opt c) Equivalent Noise Resistance R n d) Input Referred Noise Current Spectral Density

86 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 69 Equations 4.31 to 4.38 show these conversions using the port numbering convention shown in Port Measured S Parameters 2 4 Figure 4.25: Port Numbering Convention S d1d1 = 1 2 (S 11 S 31 S 13 + S 33 ) (4.31) S d1d2 = 1 2 (S 12 S 32 S 14 + S 34 ) (4.32) S d2d1 = 1 2 (S 21 S 41 S 23 + S 43 ) (4.33) S d2d2 = 1 2 (S 22 S 42 S 24 + S 44 ) (4.34) S c1c1 = 1 2 (S 11 + S 31 + S 13 + S 33 ) (4.35) S c1c2 = 1 2 (S 12 + S 32 + S 14 + S 34 ) (4.36) S c2c1 = 1 2 (S 21 + S 41 + S 23 + S 43 ) (4.37) S c2c2 = 1 2 (S 22 + S 42 + S 24 + S 44 ) (4.38) Once the differential and common mode S-parameters have been calculated, the CMRR is defined as the ratio of the differential gain to the common mode gain. CMRR = S d2d1 S c2c1 (4.39)

87 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 70 Figure 4.26 shows a plot of the measured CMRR for the 2.5 Gbps TIA. It can be seen that the TIA achieves a CMRR of approximately 29 db throughout the frequency band of interest from 0 to 2 GHz CMRR (db) Frequency (GHz) Figure 4.26: Measured Common Mode Rejection Ratio 4.6 Conclusion A 2.5 Gbps transimpedance amplifier has been presented in this chapter. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. The cascode topology is used to reduce the input capacitance of the amplifier and increase the bandwidth. The amplifier has been designed to be pseudo differential in order to improve the common mode rejection. This is important because the intended application of the TIA is an integrated transceiver. The differential structure will help reduce the impact of noise coupled into the TIA from other system components. The TIA also has a variable gain to increase the range of acceptable input powers such that the amplifier isn t saturated. Simulation results have been presented that show a maximum transimpedance gain of 64 dbω and a transimpedance bandwidth of 1.8 GHz with a photodiode capacitance of 250 ff. The average input referred noise current spectral density over

88 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 71 the TIA bandwidth is 9.0 pa/ Hz. Using the variable gain control the TIA transimpedance gain can be reduced to 46 dbω. Measured results have also been presented for the TIA and show a good match to simulated results. The S-parameters of the differential circuit were measured to obtain the transimpedance gain, group delay and common mode rejection ratio. The noise of the TIA was characterized by first measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. The TIA performance is compared to other TIAs operating at similar bit rates below in table 4.2. The transimpedance gain and noise performance compare favourably with previous work. Table 4.2: 2.5 Gbps TIA Performance Comparison Technology Z T BW C P D Noise Supply Voltage Power Dissipation Performance [4] 0.6 µm CMOS 58 dbω 950 MHz 500 ff 6.3 pa/ Hz 5 V 85 mw [6] 0.6 µm CMOS 55.3 dbω 2.2 GHz 500 ff -17 dbm 5 V 210 mw [5] 0.25 µm CMOS 80 dbω 670 MHz 1 pf 0.54 µa 2.5 V 27 mw [15] 0.15 µm CMOS 59 dbω 5.9 GHz - 31 µap-p 2 V - [16] 0.18 µm CMOS 58.7 dbω 2.6 GHz 200 ff 13 pa/ Hz 1.8 V 47 mw [18] 0.5 µm CMOS 64.0 dbω 1.2 GHz 600 ff 0.6 µa mw This work 0.18 µm CMOS 64.0 dbω 1.8 GHz 250 ff 9.0 pa/ Hz 3.5 V 115 mw Table 4.2 shows a number of different measures of TIA noise performance. The noise performance for the TIAs in [4] and [16] are given by the average input referred noise current spectral density, with the units of A/ Hz. When multiplied by the square root of the noise bandwidth of the system, this value will give an approximation of the root mean squared input referred noise current of the device. The root mean squared input referred noise current has been reported directly for the TIAs in [5] and [18]. The noise performance of the TIA can also be measured in terms of the sensitivity. In [15] this has been stated as the minimum required peak to peak signal current at the input of the TIA to achieve a specific BER. If the TIA is integrated with a photodiode, the sensitivity can be stated as a minimum received optical power

89 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 72 to achieve a specific BER as is done in [6].

90 Chapter 5 10 Gbps Transimpedance Amplifier 5.1 Introduction It was shown in section that by using a feedback topology, the frequency of the input pole created by the photodiode capacitance could be raised by a factor approximately equal to the gain of the voltage amplifier. However, for higher bit rate TIAs, the bandwidth requirement is increased and the dominant pole of the TIA will eventually be at the output of the voltage gain stage. Generally there is a direct trade-off between the gain and the bandwidth of the voltage amplifier. If the gain is reduced to improve the bandwidth, the magnitude of the input pole of the TIA is reduced. If the gain is raised, the voltage amplifier may limit the bandwidth of the TIA. This chapter looks at using bandwidth enhancement techniques to improve the bandwidth of the voltage amplifier, while maintaining a reasonable gain. 5.2 Inductive Peaking Inductive peaking can be used to extend the bandwidth of an amplifier. The basic principle is to increase the speed of the device by allowing the load capacitance of 73

91 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 74 the device to resonate with an inductor. Inductive peaking can be accomplished in the CMOS process with the use of monolithic inductors created on the upper metal layers. Active inductors can also be used, but they generally consume more voltage headroom and add noise to the circuit. The drawback to using inductive peaking is the increased area required to create the inductors Shunt and Series Inductive Peaking Figure 5.1 shows several methods of inductive peaking. Each diagram shows the equivalent circuit of the output node of a transistor amplification stage. Figure 5.1 a) shows the equivalent circuit without inductive peaking. A resistive load is used to create broadband amplification down to DC. Assuming this is the dominant pole in the system, the bandwidth of the amplifier is determined by the RC time constant created between the resistive load and the load capacitance. An inductor is placed in series with the load capacitance C L in Figure 5.1 b) creating a series resonant circuit. As the frequency increases and nears the resonance frequency, the impedance looking into the inductor is reduced, pulling more current. This results in a speed increase as more of the current I in is used to charge the load capacitance C L. In Figure 5.1 c) the inductor is placed between the load resistor and the voltage rail. This method of inductive peaking is called shunt inductive peaking because the inductor is connected in parallel with the load capacitance. As the frequency increases, the shunt inductor increases the impedance looking into the resistor allowing more of the current I in to charge the load capacitance and increase the speed. There is a limit to the increase in bandwidth for both series and shunt peaking. As the inductance is increased, the bandwidth is increased but there will also exist an unwanted peak in the frequency response and the group delay. Beyond a certain inductance, the bandwidth will no longer be increased but the peaking will become

92 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 75 R D R D L 1 V out V out I in C L Iin C L (a) (b) L 1 R D V out I in C L (c) Figure 5.1: Various Methods of Inductive Peaking a) RC Circuit Without Inductive Peaking b) Series Inductive Peaking c) Shunt Inductive Peaking

93 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 76 larger. The values of inductance that produce a maximally flat gain response and a maximally flat group delay are given by L 1 = mr 2 D C L (5.1) where the appropriate values of m are given in Table 5.1. The values of m that maximize the bandwidth of the frequency response are also given. These values are taken from [24]. Table 5.1: Values of m for Shunt and Series Inductive Peaking Response Series Inductive Peaking Shunt Inductive Peaking Maximum Bandwidth Maximally Flat Frequency Response Maximally Flat Group Delay In order to compare the bandwidth improvement achieved using series and shunt inductive peaking, the frequency response and group delay are plotted in Figure 5.2 for each type of peaking. The plots show the normalized transimpedance gain for each circuit and the frequency axis of each plot is normalized to the 3 db bandwidth of the unmodified RC circuit. Figure 5.2 a) and b) show the frequency response and group delay of each of the circuits configured for a maximally flat group delay. Shunt inductive peaking shows a bandwidth improvement of 1.58 times, while series inductive peaking shows an improvement of 1.39 times. Figure 5.2 c) and d) show the frequency response and group delay of the unmodified RC circuit as well as the shunt and series peaked circuits configured to produce a maximally flat frequency response. In this case shunt and series inductive peaking show an improvement of 1.73 and 1.42 respectively. Figure 5.2 e) and f) show the frequency response and group delay of the same circuits configured for the maximum possible bandwidth.

94 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 77 Shunt inductive peaking provides a maximum bandwidth improvement of 1.88 times the original RC bandwidth. Series inductive peaking shows minimal improvement in bandwidth beyond the maximally flat frequency response bandwidth.

95 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 78 Normalized Transimpedance Gain (dbω) Normalized Transimpedance Gain (dbω) Normalized Transimpedance Gain (dbω) No Peaking 10 Series Peaking Shunt Peaking Normalized Frequency (a) No Peaking 12 Series Peaking Shunt Peaking Normalized Frequency (c) No Peaking 12 Series Peaking Shunt Peaking Normalized Frequency (e) Group Delay (ps) Group Delay (ps) Group Delay (ps) No Peaking Series Peaking Shunt Peaking Normalized Frequency (b) No Peaking Series Peaking Shunt Peaking Normalized Frequency (d) No Peaking Series Peaking Shunt Peaking Normalized Frequency (f) Figure 5.2: Bandwidth Improvement Using Shunt and Series Inductive Peaking a) and b) Maximally Flat Group Delay c) and d) Maximally Flat Frequency Response e) and f) Maximum Bandwidth

96 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER Shunt-Series Inductive Peaking This analysis shows that shunt and series peaking are effective at improving the bandwidth with the presence of a large capacitive load. These types of inductive peaking are particularly useful in output buffers. However, a new analysis is needed when using inductive peaking between cascaded gain stages where the parasitic capacitance at the output of the first stage is comparable to the load capacitance. Figure 5.3 shows the updated equivalent circuits for shunt and series inductive peaking. L 1 R D R D L 1 I in C 1 V out C 1 C 2 C 2 Iin V out (a) (b) Figure 5.3: Modified Shunt and Series Peaking for Interstage Bandwidth Extension a) Shunt Inductive Peaking b) Series Inductive Peaking Shunt inductive peaking is no different than before, as the two capacitances C 1 and C 2 are added in parallel. The size of the inductor will be chosen based on the combination of the two capacitances. In the case of series inductive peaking, the inductor separates the two capacitances. This causes two separate resonance frequencies in the circuit and changes the performance substantially. These resonance frequencies are shown graphically in Figure 5.4. As the frequency increases, the first resonance ω 1 occurs between the series inductor L 1 and the load capacitor C 2. ω 1 = 1 L1 C 2 (5.2) As before, the resonance creates a short circuit and pulls more current into the

97 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 80 R D ω = ω 1 R D ω > ω 1 I 1 L 1 X L 1 V out V out I in C 1 C 2 I in I 2 C 1 C 2 (a) (b) 5 I in C 1 R D ω = ω 2 L 1 C 2 V out Normalized Transimpedance Gain (dbω) ω 1 ω Normalized Frequency (c) (d) Figure 5.4: Resonance Frequencies Using Series Inductive Peaking a) Series Resonance Frequency at ω = ω 1 b) Current Reversal Between ω 1 and ω 2 c) π Network Resonance Frequency at ω = ω 2 d) Transimpedance Gain with Resonance Frequencies Marked

98 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 81 load capacitance. At frequencies above ω 1 there exists a 180 degree phase shift in the impedance of the LC circuit, which produces a negative voltage at node X. This negative voltage reverses the direction of the currents I 1 and I 2 flowing in the load resistor R D and the parasitic capacitance C 1, directing more current into the load capacitance. This additional current results in a further increase in the magnitude of the frequency response beyond the first resonance point and produces a peak in the frequency response. The response is shown in Figure 5.4 d) with the resonance frequencies marked. The frequency axis is normalized to the 3 db bandwidth of the unmodified RC circuit. In the previous case where the parasitic capacitance was negligible, the load resistance could be increased to reduce the additional current I 1 and reduce this undesired peaking. When the parasitic capacitance is comparable in size to the load capacitance, adjusting the value of the load resistance has little effect on the peak in the response since the additional current I 2 still exists. Finally, the second resonance frequency ω 2 is reached when the π network consisting of the components L 1, C 1,and C 2 resonates. ω 2 = 1 (5.3) C L 1 C 2 1 C 1 +C 2 This produces an infinite impedance at node X and all of the current flows through the load resistor, returning the magnitude of the frequency response to the DC level. By separating the capacitances C 1 and C 2, series inductive peaking significantly improves the bandwidth of the circuit when compared to shunt inductive peaking when using a similar sized inductor. The cost of this improvement is a peak in the frequency response and the group delay. The bandwidth improvement using this method of inductive peaking is limited by a midband droop as the size of the series inductor is reduced. Figure 5.5 shows the change in frequency response and group delay as the series inductor is increased. The value of the inductor is equal to L 1 = nr 2 D C 2, and the value of n is swept from 0.5 to

99 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER The frequency axis is normalized to the 3 db bandwidth of the unmodified RC circuit. Normalized Transimpedance Gain (dbω) n = n = 1.0 n = 1.5 n = Normalized Frequency (a) Group Delay (ps) n = 0.5 n = 1.0 n = 1.5 n = Normalized Frequency (b) Figure 5.5: Frequency Response and Group Delay as the Series Inductance is Reduced It is possible to improve this performance by adding a shunt inductor. If chosen properly, the shunt inductor will reduce the mid-band roll-off by increasing the impedance looking into the load resistor. The shunt inductor will interact with the other components and create a resonant circuit. It is important that this resonant frequency be greater than ω 2 such that the inductor doesn t create another unwanted peak in the frequency response and group delay. It has been found in [21] that the following component relationships create the optimal performance when C 1 is equal to C 2. L 1 = R 2 D C 2 (5.4) L 2 = 0.5L 1 (5.5) Figure 5.6 shows a comparison of shunt inductive peaking, series inductive peaking and shunt-series inductive peaking under the same load conditions. The plots show the normalized transimpedance gain and group delay for each configuration. The frequency axis is normalized to the bandwidth of the unmodified RC circuit.

100 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 83 Since both the series inductive peaking and the shunt-series inductive peaking have an unavoidable peak in their response, the inductor in the shunt inductive peaking circuit was adjusted to produce the maximum gain. Shunt inductive peaking shows a bandwidth improvement of 1.74, the series inductive peaking shows an improvement of 2.34, and the shunt-series inductive peaking shows an improvement of Normalized Transimpedance Gain (dbω) No Peaking 20 Shunt Peaking Series Peaking Series Shunt Peaking Normalized Frequency (a) Group Delay (ps) No Peaking Shunt Peaking Series Peaking Series Shunt Peaking Normalized Frequency (b) Figure 5.6: Bandwidth Improvement Using Shunt, Series, and Shunt-Series Inductive Peaking a) Transimpedance Gain b) Group Delay Shunt-series inductive peaking shows a significant improvement in bandwidth when compared to simple series or shunt inductive peaking. However, it is important to examine the effects of the peak in the frequency response and group delay on random data. The peak in the frequency response will create high frequency ringing, while the peak in the group delay will increase the inter symbol interference (ISI). Figures 5.7 to 5.10 show the simulated eye diagrams using a 10 Gbps pseudo random data sequence as the bandwidth of the circuit is reduced from 11 GHz down to 5 GHz. The pseudo random bit sequence used has a code length of bits. However, due to memory restrictions, the sequence was only run for 2000 bits. As the bandwidth is reduced from 11 GHz down to 9 GHz we see a small reduction in the eye opening in the horizontal direction. This is a result of the peak in the group delay. As the bandwidth is reduced down to 7 GHz we see more horizontal eye closure since the peak in group delay begins to have more effect. We also see a vertical eye closure due

101 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 84 to the limited bandwidth. As the bandwidth is reduced to 5 GHz we see significant vertical and horizontal eye closure. Since there is a trade-off between the bandwidth and the amount of noise, a reasonable trade-off would be to produce a bandwidth between 7 and 9 GHz Transimpedance (dbω) Group Delay (ps) Output Voltage (V) Frequency (GHz) Time (ns) (a) (b) Figure 5.7: Transient Response with a Bandwidth of Approximately 11 GHz a) Transimpedance Gain and Group Delay b) 10 Gbps Eye Diagram Transimpedance (dbω) Group Delay (ps) Output Voltage (V) Frequency (GHz) Time (ns) (a) (b) Figure 5.8: Transient Response with a Bandwidth of Approximately 9 GHz a) Transimpedance Gain and Group Delay b) 10 Gbps Eye Diagram

102 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 85 Transimpedance (dbω) Group Delay (ps) Output Voltage (V) Frequency (GHz) Time (ns) (a) (b) Figure 5.9: Transient Response with a Bandwidth of Approximately 7 GHz a) Transimpedance Gain and Group Delay b) 10 Gbps Eye Diagram Transimpedance (dbω) Frequency (GHz) Group Delay (ps) Output Voltage (V) Time (ns) (a) (b) Figure 5.10: Transient Response with a Bandwidth of Approximately 5 GHz a) Transimpedance Gain and Group Delay b) 10 Gbps Eye Diagram

103 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER Gbps TIA Design The topology chosen for the transimpedance stage is a common source configuration using shunt-shunt feedback and shunt-series inductive peaking at the output. A pseudo differential structure has been chosen for this design to reduce the effect of common mode noise on the receiver sensitivity. The design is pseudo differential since the input signal from the photodiode is not differential and will only be fed into one of the inputs. There is a sensitivity penalty for making the design differential, but this penalty will be offset by the common mode noise rejection. This is important if the TIA will be integrated on the same substrate as other receiver components. A differential design also offers other benefits such as supply independent biasing. Another important aspect of this design is that it will be DC coupled. The biasing components would need to be exceptionally large to meet the low frequency cutoff specifications discussed in chapter 1. Again, for the purpose of higher integration, the design will be DC coupled to eliminate the need for large external biasing components. Unlike the TIA presented in chapter 4, this TIA was designed with a fixed transimpedance and does not have variable gain. This was done because the transimpedance is lower in this amplifier due to the lower feedback resistance required to meet the bandwidth specifications. Figure 5.11 shows the proposed topology for the TIA input stage.

104 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 87 L 2 L 2 R D R D L 1 C L L 1 R F B R F B C L M 1 M 2 C dummy I 1 Figure 5.11: Differential TIA Input Stage Using Shunt-Series Inductive Peaking

105 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER Noise Analysis Figure 5.12 shows the equivalent half circuit of the differential topology described above. L 2 R D R F B L 1 V out I P D C P D M 1 I 1 /2 C = C L Figure 5.12: TIA Input Stage Half Circuit In this section, a noise analysis will be done on this half circuit, such that the optimum component values can be determined to maximize the sensitivity of the TIA while making reasonable trade-offs with design area and power consumption. It is desirable to determine the optimum device size for the transistor M 1 to produce the lowest possible noise. The size of the common source transistor largely determines the values of the other circuit components. The input and output parasitic capacitance of the device determine the values of the shunt and series inductors required to achieve the desired bandwidth. The load resistor is then chosen to achieve a flat magnitude response. Finally, the value of the feedback resistance is determined by the input capacitance since an input pole is formed by the feedback resistor and the total input capacitance. In order to model the noise in the TIA, the circuit is broken up into three cascaded networks as shown in Figure 5.13.

106 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 89 Y F B Y P D Y L Network 1 Network 2 Network 3 Figure 5.13: Cascaded Networks The first network is a shunt admittance that will represent the photodiode capacitance. The second network is the combination of the common source transistor and the feedback admittance. The third network is another shunt admittance representing the load resistance R D and shunt inductance L 2. For simplicity, the inductors L 1 and L 2 are treated as ideal. For this reason, the series inductor L 1 and the load capacitance are not included in the analysis since they don t contribute to the input referred noise current. In reality, the inductors will have finite Q and will have an impact on the noise of the system. This is only the case for the series inductor because series resistance in the shunt inductor can be compensated for by changing the value of the load resistance R D. The three networks above are cascaded, so we can analyze each separately and combine them using their ABCD parameters. We will then have a noiseless network with the noise referred to the input. First we need to add the noise sources to the circuit. Figure 5.14 shows the noise sources for the transistor, as well as the load and feedback resistors. We will write the ABCD parameters for each network in the form shown below. The first term in equation 5.6 is the ABCD parameters for the noiseless network and the second term represents the noise referred to the input.

107 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 90 v F B Y F B I 2 2 I 3 1 I 3 2 I 1 1 I 1 2 I 2 1 v RL V1 1 Y P D V2 1,V1 2 V N M 1 I N V 2 2,V 3 1 Y L V 3 2 Network 1 Network 2 Network 3 Figure 5.14: Cascaded Networks with Noise Sources V 1 = A C I 1 B V 2 + V N (5.6) D I 2 I N Since Network 1 is simply the photodiode capacitance, we model it as noiseless. The ABCD parameters are easily derived. I 1 1 I 1 2 V 1 1 = 1 0 V 2 1 (5.7) Y P D 1 We next derive the ABCD parameters for the common source transistor with feedback. This analysis is shown in more detail in [25] as well as appendix A. An equivalent Y parameter network is used to determine the combined Y-parameters shown below I2 1 I2 2 = I N Y 11 V N Y F B v F B Y 21 V N + Y F B v F B + (Y 11 + Y F B ) (Y 12 Y F B ) V 1 2 (5.8) (Y 21 Y F B ) (Y 22 + Y F B ) V 2 2 where Y 11, Y 12, Y 21, and Y 22 are the Y-parameters of the common source transistor

108 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 91 and Y F B is the admittance of the feedback network. V N and I N are the input referred noise voltage and noise current of the common source transistor, and v F B is the noise voltage created by the feedback resistance. These Y-parameters can then be converted to the following ABCD parameters as shown in [26]. V 1 2 = I 2 1 (Y 22 +Y F B ) (Y 21 Y F B ) y (Y 21 Y F B ) 1 (Y 21 Y F B ) (Y 11 +Y F B ) (Y 21 Y F B ) V 2 2 I ( ) Y 21 (Y 21 Y F B V ) N Y F B Y 21 v F B Y F B (Y 11 +Y 21 ) (Y 21 Y F B ) (V N v F B ) + I N (5.9) where y = (Y 22 + Y F B )(Y 11 + Y F B ) + (Y 12 Y F B )(Y 21 Y F B ) Finally, the ABCD parameters for Network 3 can be derived as shown below I 3 1 I 3 2 V 1 3 = 1 0 V (5.10) Y L 1 Y L v RL where Y L is the admittance of the load and v RL is the noise voltage that represents the thermal noise created by the resistive component of the load. Now that we have the ABCD parameters for each network we can use the following identity to convert the circuit to a single noiseless network with the noise sources referred to the input. V 1 = A1 B 1 A2 B 2 A3 B 3 V 2 + V N (5.11) I 1 C 1 D 1 C 2 D 2 C 3 D 3 I 2 I N

109 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 92 V N = A1 B 1 A2 B 2 V N 3 + A1 B 1 V N 2 + V N 1 (5.12) C 1 D 1 C 2 D 2 C 1 D 1 I N I 3 N I 2 N I 1 N Next we can use the procedure shown in [25] as well as appendix A to obtain expressions for the noise parameters R n, G u and Y cor with respect to the circuit component values. The input referred noise current spectral density can be calculated from these noise parameters using the same method shown in section d i n,in 2 df = 4kT 0 G u + G S + jb S + G cor + jb cor 2 4kT 0 R n (5.13) Optimum Device Size In order to use the noise model to determine the optimum transistor device size the model needs to be constrained. First, the photodiode capacitance is set to 250 pf, which is a reasonable value. Photodiode capacitances are generally between 100 ff and 500 ff [2]. Second, the drain current density is held constant as the transistor size is varied. The drain current density is defined as the drain bias current divided by the width of the transistor. The transistor is a multi-finger device with 2.5 µm wide fingers. Models for the transistors are only available for 2.5 µm gate widths so the finger size is restricted to this value. We will assume that this stage is loaded with a similar gain stage with the same device size such that the load capacitance is equal to the gate capacitance of the device used. The inductor L 1 is determined by rearranging equation 5.2 to get equation 5.14 below. The value of ω 1 is selected to achieve the desired bandwidth. L 2 is simply half the value of L 1 using the assumption that the load capacitance is approximately equal to the drain capacitance. Finally, the load resistance is set by rearranging equation 5.4 to get equation 5.15 below.

110 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 93 L 1 = 1 ω 2 1C L (5.14) R D = L2 C L (5.15) The next step is to determine the maximum allowable feedback resistance that will still meet the required bandwidth. The feedback resistance combines with the photodiode capacitance and the input capacitance of the common source transistor to create a pole at the input. This was shown for a general feedback TIA in equation The frequency of this pole will change with the device size since the input capacitance will change. To allow for a fair comparison, the feedback resistance should also be varied along with the device size to maintain a constant bandwidth. The change in input capacitance is approximately linear, so the feedback resistance was decreased linearly to maintain a constant bandwidth. Figure 5.15 shows the magnitude response and group delay as the transistor size is changed from 20 fingers to 100 fingers (2.5 µm width fingers). There is very little variation in the bandwidth and group delay as the device size is varied, which shows that the feedback resistance has been varied properly. The values of the feedback resistance were determined experimentally. Figure 5.16 shows the change in the feedback resistance used to compensate for the change in input capacitance. An input referred noise current spectral density curve can now be calculated for each device size. In order to compare the noise performance as the device size is varied, the input referred noise current spectral density is averaged over the TIA s noise bandwidth. The noise bandwidth of a circuit is defined as the bandwidth of a perfect rectangular filter that has the same peak value and area as the actual power gain versus frequency characteristic of the system. The noise bandwidth of a circuit is given by the following equation.

111 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 94 Transimpedance (dbω) Width = 20 Finger Width = 40 Finger 30 Width = 60 Finger Width = 80 Finger Width = 100 Finger Frequency (GHz) (a) Group Delay (ps) Width = 20 Finger Width = 40 Finger Width = 60 Finger Width = 80 Finger Width = 100 Finger Frequency (GHz) (b) Figure 5.15: Transimpedance Gain and Group Delay as the Transistor Size is Increased 400 Feedback Resistance (Ω) Transistor Size (Number of 2.5 µm Fingers) Figure 5.16: Feedback Resistance versus Device Size

112 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 95 NBW 1 H pk 2 0 H(f) 2 df (5.16) For this circuit, the plot shown in Figure 5.17 shows the average input referred noise current spectral density as the device size is swept from 10 fingers to 100 fingers (a finger width of 2.5 µm is used). The drain current density is also varied and is shown using the variable I den. The plot shows that the optimum device size for the input stage of the TIA under the specified conditions is approximately 27 fingers. Average Input Referred Noise Current Density (pa/ Hz) Iden=100 A/m Iden=150 A/m Iden=200 A/m Iden=250 A/m Iden=300 A/m Transistor Size (Number of 2.5 µm Fingers) Figure 5.17: Optimum Device Size for Various Values of the Drain Bias Current I den We also notice in Figure 5.17 that the noise performance improves as the current density is increased. Figure 5.17 shows an enlarged view of the area around the optimum device size with a broader range of current densities. We can see from this plot that the optimal current density is approximately 400 A/m. There will be a direct trade-off between the current density and the power consumption. Since the load resistor is unchanged, as the current density is increased the supply voltage is increased as well as the current, leading to a large increase in power consumption. For a 27 finger transistor with a drain current density of 400 A/m, the bias current will be approximately 27 ma. The load resistor for this configuration would be 170 Ω which

113 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 96 means there will be a 4.6 V drop across the load resistor which will raise the required supply voltage. This analysis also only considers half of the differential circuit. The power consumption of the final amplifier will be twice this value. Average Input Referred Noise Current Density (pa/ Hz) Transistor Size (Number of 2.5 µm Fingers) Iden=100 A/m Iden=250 A/m Iden=400 A/m Iden=550 A/m Iden=700 A/m Figure 5.18: Optimum Current Density Next, we need to consider the component values used to create the optimum performance. Figure 5.19 shows that as the device size is lowered, the value of the series inductance is increased to maintain the specified bandwidth. This results in an interesting trade-off. As the device size is lowered, a higher bandwidth can be achieved with the same series inductor. However, in this case increasing the bandwidth beyond the optimum value found in section results in higher noise and lower receiver sensitivity. In order to maintain the optimal bandwidth, the inductor needs to be increased as the device size is reduced. Since the series inductor will be realized using a spiral inductor, a higher inductance will result in a larger area, and a lower Q factor. As mentioned before, the Q factor of the series inductor will have an effect on the noise performance. Figure 5.19 shows the value of the series inductor as the device size varied from 10 to 100 fingers. A reasonable value of inductance using the 0.18 µm CMOS technology is approximately 2 nh. This occurs at a device size of 40 fingers. We can see from

114 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 97 previous plots that a device size of 40 fingers is a reasonable trade-off between noise performance and design area Series Inductance (nh) Transistor Size (Number of 2.5 µm Fingers) Figure 5.19: Series Inductance versus Device Size Figure 5.20 shows the calculated transimpedance gain with the transistor at the optimum size of 40 fingers. The transimpedance gain shows significant peaking. This is due to the fact that the calculations assume that ideal inductors are used. The inductor parasitics will significantly reduce the peaking Final Schematic A 10 Gbps TIA has been designed using the transimpedance input stage described above. A second voltage gain stage has been cascaded with the transimpedance stage to increase the overall transimpedance gain. Finally an output buffer has been added such that the circuit can be used to drive a 50 Ω load. Figure 5.21 shows a simplified version of the schematic for the 10 Gbps TIA. Table 5.2 lists the component values used On-Chip Inductors The shunt and series inductors are implemented using square monolithic spiral inductors. As mentioned previously, the Q factor of the shunt inductor is not important since it is placed in series with the load resistor. The load resistor can be decreased

115 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER Transimpedance (dbω) Group Delay (ps) Frequency (GHz) Frequency (GHz) (a) (b) Input Referred Noise Current (pa/ Hz) Frequency (GHz) Figure 5.20: Transimpedance, Group Delay and Input Referred Noise Current using the Optimum Device Size (c) Lshunt 1 Lshunt 1 Lshunt 2 Lshunt 2 Lshunt 3 Lshunt 3 RD 1 RD 1 RD 2 RD 2 RD 3 RD 3 Lseries 1 Lseries 2 Lseries 3 OUT+ RF B RF B Lseries 1 Lseries 2 Lseries 3 OUT- IN+ M1 M1 M2 M2 M3 M3 IN- Ibias 1 Ibias 2 Ibias 3 Transimpedance Stage Voltage Gain Stage Output Buffer Figure 5.21: 10 Gbps TIA Schematic

116 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 99 Table 5.2: 10 Gbps TIA Component Values Transimpedance Stage Component Values Component L shunt 1 L series 1 R D 1 R F B M 1 I bias 1 Value 1.1 nh 2.2 nh 60 Ω 200 Ω 100 µm 24 ma Voltage Gain Stage Component Values Component L shunt 2 L series 2 R D 2 M 2 I bias 2 Value 0.95 nh 1.9 nh 122 Ω 50 µm 12 ma Output Buffer Stage Component Values Component L shunt 3 L series 3 R D 3 M 3 I bias 3 Value 0.44 nh 0.88 nh 72 Ω 87.5 µm 20 ma to compensate for any series resistance in the inductor. Since this is the case, the inductor should be designed with the smallest possible trace width in order to reduce the overall size and parasitic capacitance. The minimum allowable trace width is determined by the current density rules since the shunt inductor will be carrying the DC bias current. Square symmetrical spiral inductors are used for the series inductors. As shown in Figure 5.22 b), symmetrical inductors use multiple cross-over points to create a symmetrical structure. This means the parasitic capacitance is more balanced between the two inputs than in a square spiral inductor. This makes more sense in this situation because it doesn t add more capacitance to one side of the π resonance structure, shown in Figure 5.4, than the other. Each of the inductors was first simulated using the ASITIC simulation software in order to get a rough approximation of the required dimensions. The optimization feature was used to find the optimum dimensions for maximum Q in the series inductors. All of the inductors were then simulated using Agilent s Momentum software and adjusted accordingly.

117 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER 100 Metal 5 Metal 6 a) b) Figure 5.22: Monolithic Inductors a) Square Spiral Inductor b) Square Symmetrical Inductor Resistors The load resistors in each stage are implemented in polysilicon over an n+ diffusion to reduce the parasitic capacitance to the substrate. A blocking layer is used to prevent the polysilicon from being doped which would reduce it s resistivity. The undoped polysilicon has a sheet resistance of approximately 290 Ω/. The design rules require that each resistor have a minimum of 5 squares and a minimum width of 2 µm in order to produce an accurate resistance. With a sheet resistance of 290 Ω/, a 5 square resistor has a resistance of approximately 1.5 kω. Unfortunately in order to make accurate small value resistors like the ones required for this design, multiple 5 square resistors must be placed in parallel. This has the undesired effect of increasing the parasitic capacitance of the resistors.

118 CHAPTER GBPS TRANSIMPEDANCE AMPLIFIER Simulation Results The final 10 Gbps TIA was simulated with Agilent s Advanced Design System (ADS) using transistor models provided by the Taiwan Semiconductor Manufacturing Company (TSMC). A chip photo of the device is shown in Figure 5.23, and the final layout is shown in Figure The TIA has a total area of 1000 µm by 875 µm, including the input and output pads. In order to account for the effects of the transmission lines, pads, and inductors, Agilent s Momentum simulator was used to do an electromagnetic (EM) simulation of the top metal layer. Ports were added to each inductor as well as the pads and at the ends of the co-planer waveguides. The active components were then connected to the ports and a co-simulation was done. 875 µm 1000 µm Figure 5.23: 10 Gpbs TIA Die Photo In order to account for the effects of the photodiode, an ideal capacitance was