An Efficient CMOS RF Power Extraction Circuit for Long-Range Passive RFID Tags

Transcription

1 An Efficient CMOS RF Power Extraction Circuit for Long-Range Passive RFID Tags by Alireza Sharif Bakhtiar B.Sc., Sharif University of Technology, 2008 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE in The Faculty of Graduate Studies (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) April 2011 c Alireza Sharif Bakhtiar 2010

2 Abstract Effective matching and efficient power conversion play key roles in longrange power telemetry. This thesis discusses challenges and suggests solutions for long-range power telemetry with an emphasis on radio-frequency identification (RFID) applications. As a proof-of-concept a radio-frequency (RF) power harvesting system in a 0.13-µm CMOS technology is designed, fabricated, and successfully tested. The RF power harvesting system must maintain matching over the the wide operation frequency range of passive RFID tags, mandated by EPCglobal. In this work, we first analyze the series-inductor matching network and show that there is a trade-off between bandwidth and efficiency. We then derive some guidelines for matching circuit design for RFID tags. To solve the matching problem over a wide frequency range, an adaptive matching system is proposed. At the startup, this system turns on while the rest of the chip is still inactive, and automatically tunes the matching network to achieve its maximum output voltage. Then the rest of the chip wakes up and functions as normal. A new CMOS rectifier stage is also proposed. This stage is capable of efficient operation even with very low input powers. In addition, this rectifier stage can be cascaded to reach higher output voltages without significantly ii

3 Abstract compromising the overall efficiency. Combination of low-power performance and cascadability makes this rectifier suitable for long-range RFID tags. The test setup and measurement results are also discussed in a separate chapter. The measurement results show a 50% rectifier efficiency at 4-µW input power. To the best of our knowledge, to date, this is the highest efficiency reported for rectifiers operating at such a low input power. Also, as compared to the output voltage at the nominal center frequency of the input matching network, the system shows less than 6% drop in output voltage over the entire 55-MHz bandwidth of the system which verifies the effectiveness of adaptive matching. iii

4 Table of Contents Abstract ii Table of Contents iv List of Tables vii List of Figures viii Acknowledgements xii 1 Introduction Motivation Objectives Contribution Efficient rectifier circuit for small input powers Adaptive matching Outline Background Information Introduction Passive RFID tag iv

5 Table of Contents Protocol overview Passive tag block diagram Equivalent model of antenna Antenna impedance Power transfer in free space Antenna equivalent circuit Rectifier Introduction Dickson-based rectifiers Four-transistor cell Proposed rectifier Design approach Driver stages Bias generation Performance High efficiency with small input amplitudes Cascadability Circuit design Number of stages Sizing the driver transistors Sizing the rectifier transistors Bias voltages and transistor chains Parasitic capacitances Design summary v

6 Table of Contents 4 Matching Introduction Series matching Adaptive matching Adaptive matching versus fixed-matching for series inductor matching Tuning loop Experimental results Test setup Functionality Tuning Rectifier performance Discussion Conclusion Introduction Achievements Matching Adaptive matching Low-power, efficient, and cascadable rectifier Testing Limitations and future work Bibliography vi

7 List of Tables 2.1 RFID frequency bands components values and dimensions value of bias voltages over process variations Pins with ESD protection Pin without ESD protection FR4 substrate profile Lumped model parameters Comparison vii

8 List of Figures 1.1 RFID system [4] A commercial passive RFID tag Voltage amplitude at the output of a first-order matching network for different values of matching network quality factor(q) passive tag reading range in different environments. Box1 and Box2 are two different environments. The tuned graphs are measured by trimming the antenna to achieve resonant frequency of about 900MHz. [23] Near-field RFID system [10] Reader to Tag modulations [1] Reader to Tag modulations [1] FM0 encoding [1] Miller-modulated subcarrier encoding for M = 4 [1] block diagram of a typical tag equivalent model of antenna Modifying Dickson stage for RFID application. Diodes can be replaced by diode-connected transistors[7] viii

9 List of Figures 3.2 Placing a voltage source between the drain and source of a transistor to reduce V th (a) schematic (b) the forward I-V curve shifts to the right and reverse current increases Circuits proposed in left:[29] right:[19] left: Efficiency of [29] and conventional Dickson stage right: Efficiency of [19] (CFR) and [29] (conventional) Four transistor cell in different half cycles, black transistors are on and gray transistors are off (a)in the first half cycle (V RF > 0) M1 and M4 turn on (b)in the second half cycle (V RF < 0) M2 and M3 turn on Four-transistor cell efficiency Top:efficiency vs V RF middle: drain current through NMOS and PMOS transistors for small V RF. Bottom: drain current through NMOS and PMOS transistors for large V RF. The reverse currents highlighted left: Output voltage of the rectifier for a given input power as a function of effective threshold voltage of transistors (V th,n = V th,p ). right: Changing the effective V th of transistors in a four transistor cell NMOS and PMOS driver stages. RF + and RF are connected to a sinusoidal voltage with amplitude V RF and V B1 and V B2 are the DC bias voltages (V B1 = V B2 = 0.7) right: V o+ outputs of the NMOS and PMOS driver settling to the steady state value connection of drivers to the rectifier transistors switched-capacitor biasing circuit ix

10 List of Figures 3.11 Two stage rectifier with transistor chain biasing performance comparison of four-transistor cell and the proposed stage [27] Comparison of output voltage of a four-transistor cell rectifier and a proposed stage rectifier as a function of number of stages for a given input amplitude sweeping rectifier s design parameters equivalent input capacitance (input connected to the top plates of capacitors) Final rectifier circuit rectifier simulated output voltage and power efficiency left: vs input amplitude right: vs input power (a) parallel inductor matching (b) series inductor matching Tuning the center frequency of the matching network by switching in capacitors. R a = 7Ω, Q L = 60, P in = 10µW, C in = 600, 650, 700, 750 ff Adaptive matching versus fixed-matching network for ω 0 = 960 MHz Tuning loop FSM state diagram Counter Die micrograph Schematic of the test board Test setup x

11 List of Figures 5.4 Package model for CFP FR4 PCB substrate Inductance and quality factor of trace-inductors left: maximum inductance right: minimum inductance Measured output voltages for three different input capacitances Test PCB s left: functionality middle: entire system right: rectifier performance Lumped model used for simulations top: comparing measurement results with simulation results middle: rectifier output voltage bottom: rectifier efficiency. 83 xi

12 Acknowledgements I would like to thank Professor Shahriar Mirabbasi for all his guidance and support throughout this process. His patience and advice made this work possible. Thank you for this opportunity. I am also thankful to my colleague, Mohammad Sadegh Jalali, for all his support and the technical discussions that played a signicant role in my research. Also, I would like to acknowledge Dr. Roberto Rosales for his kind technical and non-technical assistance during the entire design process. Last but most certainly not least, I would like to extend my deepest appreciation to my wonderful parents, who always supported me and helped me to become who I am today. It was definitely not possible without their patience, support, and guidance. They have always been the greatest source of inspiration for me, and I dedicate this thesis to them. This research is supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC). CAD tool support is provided by Canadian Microelectronics Corporation (CMC Microsystems). xii

13 Chapter 1 Introduction 1.1 Motivation A radio-frequency identification (RFID) system is comprised of a number of interrogating transceivers referred to as readers and a number of transponders 1 referred to as tags. An RFID tag typically consists of a radiofrequency (RF) transceiver, a memory, and in some cases a sensor. RFID readers on the other hand are hand-held or fixed RF transceivers that can wirelessly access the tags memory to read and write certain data on it. A complete RFID system includes several tags, some number of readers (connected to an infrastructure with a software program that normally controls communicating data to and from the readers), and the enterprise system that monitors all the activities in the system (Figure 1.1). An RFID system can be thought of as a wireless barcode system where the tags act like barcodes except that they can be read wirelessly from a relatively longer distance and the readers as barcode readers which gather the data and provide it to the central system. Compared to barcodes, RFID tags have the advantage of being faster and also the information of the tags can be accessed wirelessly by an authorized user. Therefore it is more convenient and 1 Transmitter-responder 1

14 1.1. Motivation Figure 1.1: RFID system [4] practical to repalace barcodes with RFIDs. RFID is contentiously becoming prominent part of many application domains including transportation, asset management, baggage handling, animal tracking, toll collection, and supply chain management. For instance in an inventory system it is important to keep account of the assets at any given point in time. One solution is to attach RFID tags containing some information about the item on every item in the inventory. Now, all the data about the inventory assets can be gathered wirelessly in a few seconds at any time using readers strategically installed in the inventory area. Depending on the application, RFID tags come in different sizes, prices, and capabilities. Some tags have sensors on them, for example to measure environmental parameters such as temperature and pressure. In large areas such as airports where it is not convenient to place too many readers, reading range (the maximum distance between the reader and the tag over which the reader can communicate with the tag) becomes important. In inventory systems where a large number of tags must be utilized the low price of the 2

15 1.1. Motivation tags also becomes a priority. Based on how they are powered, RFID tags are categorized into three classes: active, semi-active, and passive. Active tags have an onboard battery to power their circuitry. Because of availability of the battery, active tags typically have a longer reading range. Also, they can perform more sophisticated functions as compared to the other types of tags. The drawbacks of active tags include increased price, and limited battery life and thus reliability. Similar to active tags, semi-passive tags also have a battery to power their circuits. However, semi-passive tags do not use the battery for sending signal to the reader. They use electromagnetic reflection for data transmission. Whenever, the reader expects a response from a semi-passive tag, it transmits a sinusoidal RF signal to the tag. Then the tag sends data to the reader by changing the amplitude or phase of the signal and reflecting it back to the reader. Readers sense these variations in the reflected signal and extract the data. Unlike the first two categories passive tags do not have any onboard battery. They typically scavenge the power from the RF signal that is transmitted by the reader to power and then use the same reflection technique that is used by semi-passive tags to transfer data to the reader. Since passive tags do not have any onboard power source, e.g., batteries, they can be low cost, small, and reliable with a very long life time. These properties make passive tags favorable to applications where a large number of tags are required, or size of the tag is required to be small. Some passive tags even include sensors and sensor interface circuitry which makes them 3

16 1.1. Motivation Figure 1.2: A commercial passive RFID tag capable of simple monitoring and measurements [12]. Figure 1.2 shows a commercial RFID tag. Some of the passive RFID applications include [12], access control in buildings or using RFID as tickets for public transit, ski resorts or similar ticketing systems animal identification for monitoring animal behavior, tracing origin, controlling epidemics, and quality assurance anti-theft systems in cars by placing a secure RFID tag into the car key container and part identification in cargo transportation and production lines inventory control a vast number of applications in health care varying from controlling medicines in hospitals to monitoring patient conditions, etc One major drawback of passive RFID tags is their limited operating range. Readers in passive RFID systems send RF signal with finite power (constrained by local regulations [3]) to the tags. Because of the channel 4

17 1.2. Objectives attenuation, only a portion of this RF signal reaches the tags. Tags convert this power to a DC supply voltage to power up their onboard circuits. As the distance between the tag and the reader increases, the channel attenuation increases sharply and the share of the tag from the reader s RF signal power becomes smaller and beyond a maximum distance the power reaching the tag is not sufficient enough to power the tag. In practice, this maximum operating distance is limited to a few meters. To read tags located in a large area like an inventory system, a large number of readers must be carefully installed to cover the area [21]. As the operating range of the tags decreases the number of readers grows rapidly and it becomes more difficult to cover the whole space which make RFID solution more costly and less reliable. 1.2 Objectives This thesis discusses challenges and suggests solutions for long-range power telemetry with an emphasis on radio-frequency identification (RFID) applications, and proposes techniques and circuits to improve the operation range of passive RFIDs. To comply with the industry trend, the targeted technology for implementation of the proposed circuits is 130-µm CMOS technology which while cost effective can accommodate a large number of transistors and logic gates in a reasonable active area. To verify the proposed technique a test-chip is designed, fabricated, and successfully tested as discussed in Section 5. 5

18 1.3. Contribution 1.3 Contribution Efficient rectifier circuit for small input powers Passive tags use an AC/DC voltage converter circuit, namely a rectifier to convert the received narrow-band RF signal into a DC supply voltage to power up their internal circuits. Similar to conventional AC/DC converters, these rectifiers use either diodes or transistors to rectify the input current and generate DC voltage. The problem with these rectifiers is that as the signal power drops due to the attenuation of the propagation channel the voltage swing in the input of the rectifier becomes too small to completely switch the rectifier diodes and/or transistors. Therefore, the rectifiers efficiency degrades and the effective operating range of RFID tag decreases. In other words, as the received power from the reader decreases, because of the increased distance between the tag and the reader, the rectifier becomes less effective which in turn further limits the maximum operating range. There has been many efforts to improve the efficiency of rectifiers under low input powers. One way is by properly biasing the transistors [19, 29]. These approaches achieve a higher efficiency in standard CMOS technology for some bias voltages however in such circuits the reverse current of transistors is increased which in turn decreases the performance. Performance can be further improved by using structures with inherently higher efficiency. The other trend has been the use of more advanced technologies with zero/low threshold transistors which is of course more costly to fabricate [25, 30]. Another approach is using more efficient structures such as those in [17, 24]. These techniques are revisited in more depth in Chapter 3. 6

19 1.3. Contribution This work combines an efficient rectifier [17, 24] with a novel biasing technique. As a result the new rectifier circuit can operate effectively even for low-input RF power. This is very desirable in terms of increasing the maximum operating range of the passive tags. Utilizing a rectifier that can function with low input powers, the bottleneck for the maximum range of operation becomes the power consumption of the tag s onboard circuitry. Additionally, unlike many previously reported rectifiers the proposed CMOS rectifier can be cascaded without loosing efficiency (and it can be implemented in a standard CMOS technology). In chapter 4, it will be explained that this property relaxes the constraints on the quality factor of the matching circuit components and improves matching between the tag and its antenna Adaptive matching Figure 1.2 shows a commercial passive RFID tag. Passive RFID tags uses an antenna to receive and reflect RF signal. According to EPCglobal protocol tags must be capable of receiving RF signal in the frequency range of 860M to 960 MHz [1]. To guarantee maximum power transfer from the tag antenna to the onboard circuitry, an effective matching must be maintained between the antenna and the chip input impedance over the operation bandwidth. The more effective the matching is, the more power becomes available to the tag and thus the maximum operating range of the tag increases. For the sake of simplicity and cost, passive tags typically use simple (low-order) matching circuits [7]. 7

20 1.3. Contribution These matching circuits are band-pass in nature, so the matching becomes worse, as the frequency of the RF signal deviates more from the center frequency of the matching network. Quality factor of the matching network is indicative of bandwidth of the matching network. 2 Higher Q translates to a narrower bandwidth for a given center frequency. So it is desirable to have a low-q matching network so we can maintain matching over a wider range of frequency. However, there is a tradeoff between the bandwidth and the voltage in the output of the matching network (input of the rectifier) at a given power. This tradeoff is shown the Figure 1.3. As the bandwidth increases, the voltage at the input of the rectifier decreases. Low Q is favorable since its bandwidth is larger, on the other hand, the higher Q results in higher rectifier efficiency. [16] explains the benefits of high Q in RFID passive tags. It is mathematically shown that the higher the quality factor the larger the rectifier input voltage amplitude which in turn increases the rectifier efficiency. In long-range RFID tags, the Q must remain relatively high to achieve a reasonably large voltage swing from a small input power. As a result, a large portion of the received power is wasted because of the mismatch when the tag is operating in the extremes of the frequency range allowed in the protocol. In [23] the read range for a passive tag in different environments is measured. These measurements indicate that not only the read range is a function of frequency (also shown in Figure 1.4) the optimal frequency is a function of 2 The quality factor (Q) is defined as the ratio of the center frequency of the bandpass network (ω 0) to the 3-dB bandwidth of the network. 8

21 1.4. Outline Voltage amplitude (V) Q=20 Q=10 Q= Frequency (MHz) Figure 1.3: Voltage amplitude at the output of a first-order matching network for different values of matching network quality factor(q) package as well as the surrounding environment. The read range varies from 1 m to 5 m because of the frequency-dependent mismatch between the tag and the antenna. The adaptive matching can be implemented to mitigate all these problems. This work uses a feedback system to configure the matching circuit for a better matching in all frequencies in the protocol. This feedback system facilitates effective tag operation over a wide range of frequency while taking advantage of the simplicity of the first-order matching circuit. 1.4 Outline This thesis is organized as follows. In Chapter 2 some RFID principles and background information about RFID are reviewed. Chapter 3 discusses the rectifier design. Chapter 4 explains the matching circuit and the trade offs 9

22 1.4. Outline Figure 1.4: passive tag reading range in different environments. Box1 and Box2 are two different environments. The tuned graphs are measured by trimming the antenna to achieve resonant frequency of about 900MHz. [23] in designing matching circuits. Chapter 5 presents the measurement and simulation results and finally Chapter 6 concludes the thesis. 10

23 Chapter 2 Background Information Passive RFID 2.1 Introduction Passive RFID systems are not powered by an external source of power like batteries and receive their power from the RF signal sent by the reader. Tags receive power and information from the reader, and respond back by reflecting back the RF signal from the reader. Based on the physical coupling method RFID tags can fit into two classes. Systems with write and read ranges of up to 1m are known by collective name of remote coupling or near-field systems. Almost all remote coupled systems are based on inductive (magnetic) coupling, in which power and data is transferred between two coupled inductors. These systems usually operate at LF and HF frequency bands (Table 2.1). Figure 2.1 illustrates such a system. As it is shown the power is transfered between two loosely coupled inductors from the reader side (L 1 ) to the transponder (L 2 ). Systems with operating ranges significantly above 1m are know as long-range or far-field systems. In these systems data and power is transfered through electro- 11

24 2.1. Introduction Figure 2.1: Near-field RFID system [10] Table 2.1: RFID frequency bands Frequency band Description Range 125k-134kHz Low-frequency (LF) up to 18 inch M MHz High frequency (HF) 3-10 ft. 860M - 960MHz ultra-high frequency (UHF) ft. 2.45GHz Microwave +10 ft. magnetic waves in the UHF and microwave frequencies.[12] Most of the long-range passive tags operate in the UHF band ( MHz) and comply with EPCglobal[1]. In this work we discuss the latter class of tags and refere to them as passive tags. The remaining of this section briefly explains some of the important background information which are used in the later sections. 12

25 2.2 Passive RFID tag Protocol overview 2.2. Passive RFID tag Reader-to-tag channel: In the physical layer an Interrogator (Reader) sends information to one or more tags by modulating an RF carrier using double-sideband amplitude shift keying (DSB-ASK), single-sideband amplitude shift keying(ssb-ask) or phase-reversal amplitude shift keying (PR- ASK) using a pulse-interval encoding (PIE) format. Tags receive their operating energy from this same modulated RF carrier. Figure 2.2 shows examples of the modulated wave forms for a given data. An interrogator receives information from a tag by transmitting an unmodulated RF carrier and listening for a backscattered reply. Tags communicated information by backscatter-modulating the amplitude and/or phase of the RF carrier. The encoding format, selected in response to interrogator commands, is either FM0 or Miller-modulated subcarrier. The communications link between interrogators and tags is half-duplex, meaning that tags shall not be required to demodulate interrogator commands while backscattering. A tag shall not respond using full duplex communications to a mandatory or optional command. Data encoding The reader uses PIE signaling to communicate with tags. Defining Tari as the reference time interval (6 µs Tari 25 µs) the PIE signaling is as shown in Figure

26 2.2. Passive RFID tag Figure 2.2: Reader to Tag modulations [1] 14

27 2.2. Passive RFID tag Figure 2.3: Reader to Tag modulations [1] Tag-to-reader channel: When the reader wants to receive data from the tag it transmits continuous wave unmodulated RF signal to the tag and tag responds by backscatter modulation. More specifically tag responds by switching its reflection coefficient between two states. The tag selects the modulation format (ASK and/or PSK) and the reader selects the encoding and the data rate. The tag uses either FM0 baseband or a Miller modulation of a subcarrier encodings. FM0 Encoding In this scheme one transition in middle of a bit interval translates to a 0 data and no transition translated to a 1 data and the signal always toggles in the beginning of each bit. Figure 2.4 illustrates examples of FM0 sequences. Miller-modulated subcarrier Encoding The baseband output of this scheme is a square wave with frequency of M times the data rate. In this scheme the phase inverts between two data- 0 sequence. Also it places a phase inversion in the middle of a data- 1. Figure 2.5 shows an example of this encoding with M = 4. 15

28 2.2. Passive RFID tag Figure 2.4: FM0 encoding [1] Figure 2.5: Miller-modulated subcarrier encoding for M = 4 [1] 16

29 2.2. Passive RFID tag Passive tag block diagram Figure 2.6 shows the block diagram of a typical RFID tag. Not all tags necessarily have the exact same structure but almost all of them follow a similar structure. Antenna and matching Tag uses an antenna to receive data and power from the reader and back-scatter the signal to the reader to respond. The matching block is to maintain a good matching between the antenna and the chip for efficient power transfer. The matching circuit is usually integrated into the antenna design. For instance [17] uses the antenna to implement a second-order LC-like matching circuit. Rectifier This block is an AC/DC converter which receives the incoming RF signal from the antenna and generates the DC power supply for the circuits on the tag. Chapter 3 is devoted to this block. Demodulator This block is essentially an envelope detector and a comparator. As explained in section the information is transmitted in the envelope of the signal. The demodulator needs to detect the envelope of the signal and compare it to a proper threshold. Because the tag input voltage amplitude varies largely depending the tag distance from the reader the envelope detector might be preceded by an attenuator and the comparator by a pre-amplifier. [5] explains the design of a CMOS voltage-base demodulator with automatic threshold adjustment and a variable gain attenuator and [19] describes a current-mode demodulator. 17

30 2.2. Passive RFID tag Modulator To modulate the back-scatter signal the tag changes its input impedance via switching in/out a given impedance. This block is usually either a CMOS switch connecting the input node to ground [25] or a switch varying the control voltage of a varactor [13] Voltage-controlled oscillator (VCO) To generate the clock signal for the tag circuits (usually digital blocks) some tags incorporate a low-power VCO [8, 16, 19]. The output frequency of this VCO is low and about a few megahertz. [6] explains a very low-power and low-voltage oscillator for RFID applications. Alternatively since some tag use the demodulated data to generate a clock signal. For instance in [13] the inverted envelope of RF signal is used as clock signal for the tag s finite-state machine (FSM), where each rising edge denotes the arrival of a new bit 3. The clock generated using the Schmitt trigger has a high phase noise. In [14] because of the high tag-to-reader data rate a low-phase noise was required. So the system uses an injection oscillator with 650µ A current consumption to generate a clean clock. Bias generation and power-on-reset tags typically include some onchip bias generation circuits. A power-on-reset (POR) circuit is also used to turn on the chip after the supply voltage (generated by the rectifier) exceeds a certain value which guarantees a more reliable tag operation. 3 This tag also has an internal clock generation which uses the clock from demodulated signal. However [13] does not provide any details on this block 18

31 2.3. Equivalent model of antenna antenna Matching CHIP UHF Pad ESD Rectifier POR Voltage control & Bias VCO CLK Vdd Logic and Memory Demodulator Modulator Figure 2.6: block diagram of a typical tag Digital core EPCglobal requires tags to do some logic operation and include a minimum amount of memory. This memory is mostly used for saving the password, running cyclic-redundancy check, and saving some data about the item carrying the tag and some user memory. 2.3 Equivalent model of antenna Antenna impedance The input impedance of an antenna is the impedance presented by the antenna at its terminals. The input impedance will be affected by other antennas or objects nearby, but for this discussion we assume that the antenna is isolated. In the case of RFID tags this environmental variations can change the behavior of the tag (see Figure 1.4) so some precaution must be taken [18]. The input impedance consists of a real part and an imaginary part and can be written as: Z a = R r + R ohmic + jx a (2.1) 19

32 2.3. Equivalent model of antenna In Equation (2.1) R r is the radiation resistance of the antenna, R ohmic is the ohmic resistance of the antenna, and X a represents the power stored in the near field of the antenna. If a current I in passes through the antenna, the average power dissipated in the antenna would be equal to: P a = P r + P ohmic = 1 2 R r I in R ohmic I in 2 (2.2) In Equation (2.2) P r is the power radiated by the antenna into space (transmit antenna), and P ohmic is the antenna ohmic loss. R r is a function of the physical properties of the antenna like the shape and the dimensions of the antenna. The ohmic resistance of the antenna is caused by the finite conductivity of the antenna and is increased by skin effect at higher frequencies 4 For many antennas the ohmic resistance remains negligible compared to the radiation resistance. According to reciprocity in antennas, it can be shown that the same impedance can be used to model the antenna regardless of whether the antenna is a transmit or receive antenna.[28]. At the operation frequency of the antenna(i.e. the resonant frequency of the antenna) the imaginary part of the antenna impedance X a tends towards zero. For loss-free antenna Z a (f res ) = R r [12]. 4 For conductors carrying ac current the current density decrease by moving from the surface of the conductor towards the center. This effect reduces the effective cross section of the inductor and increases the resistance of the conductor at higher frequencies. In the case of the infinitely thick plane conductor the current density drops exponentially and reaches 1/e of its maximum value at distance 2σ ωµ angular frequency, and µ is the magnetic permeability where σ is the resistivity, ω is the 20

33 2.3. Equivalent model of antenna Now let us say an antenna with impedance Z a is connected to a load of impedance Z in and receives an RF signal. The RF signal generates a voltage V a in the antenna as shown in Figure 2.7. The power dissipated in the load is given by: thus, P load = 1 2 Re(V in I in) = 1 2 Re( Va 2 (R in jx in ) R in +R a+j(x a+x in ) = 1 ) 2 2 P load = V a 2 ( 1 8R a In Equation (2.3), P avail is defined as, Va 2 R in (R in +R a) 2 +(X in +X a) 2 Z in Z 2 ) a (2.3) Z in + Z a P avail = V 2 a /8R a (2.4) Which is the power that the load receives from the antenna under the condition Z in = Z a (the antenna is connected to the matched load). Reflection coefficient can also be define as Γ = Z in Z a Z in +Z a. By replacing P avail and Γ Equation (2.3) can be written as, P load = P avail (1 Γ 2 ) (2.5) Power transfer in free space The power transfer from a transmit antenna with gain G t 5 and transmit power of P t to a receive antenna of gain G r in free space is described by Friis transmission formula Equation (2.6). 5 Gain of the antenna represents the ability of the antenna to focus the radiated beam (Directivity) and its efficiency which is smaller than 1 because of the antenna loss 21

34 2.3. Equivalent model of antenna P r = P t G t G r ( λ 4πr )2 (2.6) where P r is the power received by the receive antenna, λ is the wavelength of the transmit signal, and r is the distance between the transmitter and the receiver. This is the power that an antenna provides to the matched load (Z a = Z in ). Referring to section we can see that the power P r in the Friis formula is what we called P avail when finding the equivalent model for the antenna. Equation (2.7) reiterates this fact. P r = P t G t G r ( λ 4πr )2 = V a 2 (2.7) 8R a The equivalent model of an antenna is illustrated in Figure 2.7 It is worth mentioning that an important radio technology term in this connection is the EIRP (effective isotropic radiation power). P EIRP = P t G t (2.8) This figure can often be found in radio licensing regulations and indicates the transmission power at which an isotropic emitter (i.e. G t = 1)would have to be supplied in order to generate a defined radiation power at distance r. An antenna with a gain G t may therefore be supplied with a transmission power P t that is lower than the value P EIRP /G t. P EIRP varies based on the local regulations. For example regulations allow for 4 W EIRP in north America. 22

35 2.3. Equivalent model of antenna antenna jx a R a V a Z in Figure 2.7: equivalent model of antenna Antenna equivalent circuit Putting all the information in the past two subsections together, it yields that the antenna can be modeled as a voltage source, whose voltage regardless of the load is given by (see Equation (2.4)), V a = 8P avail R a (2.9) where P avail is given by the Friis formula (Equation (2.6)). The output impedance of this voltage source at resonance is R a. This simple equivalent model is shown in Figure 2.7 R a is a function of the type of the antenna as well as physical dimensions of the antenna compared to RF wavelength. For instance, in short dipole antennas (L < λ/4 where L is the length of the antenna and λ is the RF wave length) we have: R a = 20π 2 ( L λ ) (2.10) In passive RFID tags the dimensions of the tag is typically small compared to the signal wavelength (λ 30 cm) thus R a remains in the range of a few 10 s Ohms to a few 100 s Ohm based on the type of the antenna. 23

36 Chapter 3 Rectifier 3.1 Introduction Designing an efficient rectifier is the key to long-range RFID tag design. As the distance between the tag and the reader increases, the power available to the tag rapidly drops(equation (2.6)). This small available power combined with the small efficiency of the CMOS rectifiers puts a limit on the operating range of the tags. On the other hand the efficiency of rectifiers drops for small input powers which further decreases the maximum operating range of passive RFID tags. To address this problem, a rectifier with high efficiency for small input powers is designed. In this chapter we first review the rectifiers in the literature. After that we introduce a new CMOS rectifier which can operate more efficiently than the reported state of the art rectifier at low input powers Dickson-based rectifiers Dickson-based rectifiers have been widely used in passive RFID tags. The original circuit was proposed in 1976 as a voltage multiplier. By a simple modification (as shown in Figure 3.1)this circuit can be used as RFID 24

37 3.1. Introduction rectifier. The operation of this circuit is explained in [9]. We calculate the output voltage of this circuit when the input is connected to a sinusoidal signal with amplitude V IC and frequency of f and output DC current of I Load. We assume only the first stage of the rectifier (D 1, D 2, C C1, and C L1 ) and let us say C C1 = C L1 = C c and C s represents the parasitic capacitance at node X i. In the first half of the input negative halfcycle (V IC < 0) node X 1 goes to the minimum voltage of V D, where V D is the voltage drop on conducting diodes, and then all diodes turn off. In the next half of the negative half-cycle and the first half of the positive half-cycle the input changes from V IC to V IC. Assuming no current is drawn from the output (I Load = 0) all diodes remain off in this time interval. As a result node X 1 goes from V D to V D + 2V IC C c+c s. In steady state D 2 remains off and the X 2 voltage remains at V X1,max V D = ( V D +2V IC C c+c s ) V D. In the presence of I Load, the load draws the average current of I Load from all capacitors which gives a 2I Load (C c+c s)f C c C c average voltage drop for the first stage. Putting all this together the output voltage of this stage with only two C diodes becomes equal to ( 2V D + 2V c IC C c+c s ) 2I Load (C c+c s)f. Extending this analysis, which assumed only two diodes, to the general case of N diodes it yields that the output voltage of this circuit is equal to, ( C ) c V DC = V IC.( ) V D N I LoadN C c + C s (C c + C s )f (3.1) By ignoring the effect of parasitics(c c C s ) and high input frequency the output voltage can be approximated by V DC = N(V IC V D ). If implemented with diode connected MOS transistors, we have V D 25

38 3.1. Introduction Figure 3.1: Modifying Dickson stage for RFID application. Diodes can be replaced by diode-connected transistors[7] V th 6. With the typical input amplitudes of less than 1V and threshold voltages of few hundreds of millivolts, the output voltage of Dickson rectifier would be too small for long-range RFID tags. This is one of the drawbacks of Dickson stage. One solution proposed to mitigate this problem is to put a DC bias voltage between the drain and the gate of diode connected transistors in a Dickson stage. Figure 3.2 plots the I-V characteristic of a diode-connected NMOS with a DC bias voltage connected between its drain and gate. As it can be seen in the forward region (V ds > 0 for NMOS and V ds < 0 6 Threshold voltage of transistors 26

39 3.1. Introduction for PMOS ) the transistor behaves like a low-v th transistor with a smaller voltage drop. The problem is in the reverse region when the transistor must be off (conduct no current) and V D < V S the transistor starts conducting a reverse current with V GS = V Bias. These reverse currents have two undesirable effects (a) Reverse currents discharge the capacitors (C c and C L ) which results in larger ripple on the supply voltage and reduces the supply voltage value for a given number of stages. (b) Reverse currents increase the power disspation in transistors. Note that V ds of the reversed bias transistors can be almost as large as 2V IC and the dissipated power is the product of V ds times the current through the transistors. Despite the reverse current conduction, by careful selection of the bias voltages this technique results in better low-power performance. [19, 29] have used this bias voltage in combination with Dickson-based rectifiers to enhance the low-power performance. In [29] also shown in Figure 3.3, a pre-charged capacitor is placed between the drain and the gate of transistors by MOS switches. The charge on this capacitor generates the bias voltage to lower the turn on voltage of the diodeconnected transistors. The switches recharge the capacitor with a frequency of as low as 100Hz. This low recharging frequency keeps the power overhead of the bias generator circuit negligible (the biasing circuit draws 0.2 na from a 1.5 V supply). This circuit needs a secondary battery to run its bias generator circuit. [19] uses V GS of other transistors as bias voltages for diode connected transistors. As shown in Figure 3.3 (right), the small current passing through M pb creates a DC voltage between the gate and drain of this transistor. Con- 27

40 3.1. Introduction Reverse Current 0 I D (µa) 50 V GD =0.3 V 100 VGD = V DS (V) Figure 3.2: Placing a voltage source between the drain and source of a transistor to reduce V th (a) schematic (b) the forward I-V curve shifts to the right and reverse current increases necting the gates of M p1 and M pb together ensures that the gate voltage of M p1 is lower than its drain voltage by V GS Mpb. As discussed earlier this reduces the voltage drop on M p1 when it is conducting current. Similar argument can be made for M nb and M n1. This scheme reduces the parasitic capacitance (C s ) of the Dickson stage compared to [29]. This lower capacitance increases the output voltage according to Equation (3.1). Using the biasing scheme in combination with low C s, symmetrical structure and small number of stages, this stage outperforms the circuit in [29] (Figure 3.4) in addition to self-sufficiency 7. Although this technique results in leaky reverse diodes, performance improvement has been reported [19, 29]. The graph on the left side of Figure 3.4 compares the performance of [29] with conventional diode-connected Dickson stage. The proposed stage operates 7 The rectifier does not need a secondary source of power 28

41 3.1. Introduction Figure 3.3: Circuits proposed in left:[29] right:[19] Figure 3.4: left: Efficiency of [29] and conventional Dickson stage right: Efficiency of [19] (CFR) and [29] (conventional) at lower input powers where the conventional Dickson stage is incapable of operation. The figure on the right compares the stage proposed in [19] (CFR) with the one in [29] (conventional). 8 Another alternative to overcome this problem is using low and zerothreshold voltage transistors. These transistors have very low threshold voltages and can be used in diode-connected configuration without too much forward voltage drop. However, these devices are costly to fabricate and low cost is an important factor in passive RFID systems. [14, 25, 30] are 8 For the comparison to be fair authors in [19] have measured the conventional performance in their particular technology. 29

42 3.1. Introduction examples of such rectifiers. Using more advanced technologies providing zero V th devices [30] reports a 33.69% efficiency for 40 µw input power. [14] uses a 16-stage Dickson stage with low-v th PMOS transistors. The use of PMOS transistors enables the circuit to eliminate the destructive effect of V th increase due to body-effect. This rectifier reaches 10.94% efficiency at 63.1 µw input power at 450 MHz. [25] uses a four-stage Dickson stage with native devices. 9 This rectifier achieves 6.7% efficiency with 15.2 dbm (30 µw) input power Four-transistor cell In [17, 24] a rectifier stage namely Four transistor cell has been proposed. This stage outperforms Dickson based rectifiers because of its inherently more efficient structure. This stage functions as follows: As Fig 3.5 (a) depicts, in the first half cycle of the input voltage (V RF > 0) M 1 and M 4 turn on to charge the decoupling capacitor (C L ), meanwhile M 2 and M 3 turn completely off by reversing the polarity of their V GS. In the next half cycle (V RF < 0) transistors M 3 and M 2 turn on to charge the decoupling capacitor with M 1 and M 4 in cut off. Unlike Dickson-based stages all transistors in this stage turn on with V GS,on V RF for reduced voltage drop on transistors and turn off by reversing the polarity of transistors V GS for a solid cut off with no reverse current near the input extremes. Thus this stage outperforms Dickson-based stages especially for small input amplitudes. 9 These transistors provide lower-threshold voltage compared to normal MOS transistors because of lower channel doping. 30

43 3.1. Introduction + Vx M3 M4 VRF VH VH VRF M1 M2 VY Load + Vx M3 M4 M1 VY M2 Load (a) (b) Figure 3.5: Four transistor cell in different half cycles, black transistors are on and gray transistors are off (a)in the first half cycle (V RF > 0) M1 and M4 turn on (b)in the second half cycle (V RF < 0) M2 and M3 turn on The efficiency of the four-transistor cell first increases by increasing the input amplitude (V RF ), it peaks at V RF,opt and then drops (Figure 3.6). This is because when the input amplitude is too small, the transistors do not completely turn on, which results in a large drain-source voltage drop on conducting transistors that consequently drops the output DC voltage. The minimum voltage drop on conducting transistors ( V DS min ) can be reduced by increasing gate-source voltage ( V GS ) of those transistors. On the other hand, when the input amplitude is too large, transistors conduct a reverse current from the decoupling capacitor back to node X/Y for a short period of time before and after PMOS transistors turn on in the forward direction (current from V X /V Y to V H ). 10 This effect is shown in Figure 3.6. The reverse current drops the efficiency of the rectifier and 10 The reason for this reverse current say in the first half cycle when V X > V Y is when the input signal becomes large, right before the transistors turn on in the forward direction, the gate voltages ( V G ) are large enough to turn on transistors. However V X is less than V H and V Y is higher than V L. This voltage different causes a current in the reverse current. 31

44 3.1. Introduction increases the voltage repel on the decoupling capacitor. It can be shown that for input amplitudes larger than, V RF > V th,p MOS/NMOS + 2 V DS,P MOS/NMOS min (3.2) The PMOS/NMOS transistors conduct the reverse currents. To avoid huge reverse currents in NMOS/ PMOS transistors and incomplete turn on in the other pair of transistors (PMOS/NMOS), in a well-designed rectifier the value of V th +2 V DS min must be about the same for NMOS and PMOS transistors. About this voltage amplitude, the V GS,max of the transistors is large enough to prevent large voltage drop on reasonable sized conducting transistors and the reverse current is not considerable. Thus the maximum conversion efficiency of the rectifier occurs about this voltage amplitude. We shall call the amplitude at which the conversion efficiency is maximum V RF,opt (V RF,opt V th + 2 V DS min ). V RF,opt dependents on the threshold voltage of the rectifier transistors (Equation (3.2)). Four transistor cell has two major problems; (a) given a set of (V th,nmos, V th,p MOS ) designer does not have much control over the value of V RF,opt (although V RF,opt is weakly proportional to the transistors aspect ratio) (b) (in absence of deep n-well) in multistage rectifiers, due to the body effect the threshold voltage of NMOS transistors increases as we move to later stages. This effect drops the efficiency of the rectifier. Our proposed rectifier solves this problem by using driver stages to the control the gate voltage of transistors. 32

45 3.1. Introduction Efficiency (%) VRF,opt Amplitude (V) Voltage (V) Vout VRF+ VRF I (µa) 0 Inmos I (µa) Ipmos Time (sec) x 10 6 Voltage (V) Ripple Vout VRF+ VRF I (µa) I (µa) Reverse Current Reverse Current Ipmos Inmos Time (sec) x 10 6 Figure 3.6: Four-transistor cell efficiency Top:efficiency vs V RF middle: drain current through NMOS and PMOS transistors for small V RF. Bottom: drain current through NMOS and PMOS transistors for large V RF. The reverse currents highlighted 33

46 3.2 Proposed rectifier 3.2. Proposed rectifier Design approach As mentioned in section a transistor with threshold voltage V th and a bias voltage (V b ) in series with its gate behaves approximately similar to a transistor with threshold voltage of V th V b in the forward direction. We used this property to enhance the efficiency of the rectifier for any given power. Figure 3.7 shows a four-transistor cell with bias voltages connected to the gate of transistors. V H is rectifier s DC output and V L is rectifier s DC terminal which is either connected to ground or to the output of the previous stage. Sweeping the bias voltages (V osn, V osp ) at a given input power and a given load in Figure 3.7 shows that the output voltage (and hence rectifier efficiency)peaks at some particular bias voltage. In other words by controlling the DC bias of the rectifier transistors gate, the rectifier can operate at the peak of its performance curve. The proposed rectifier utilizes two driver stages (per rectifier stage) to generate a given bias voltage on the gate of rectifier transistors while driving the gates with the same AC amplitude as that of four-transistor cell Driver stages Figure 3.8 shows one NMOS and one PMOS driver stage connected to DC bias voltages V b1 and V b2. Figure 3.9 shows how these drivers should be connected to the rectifier transistors. In Figure 3.8 the outputs of the drivers are connected to the load capacitances C load which models the gate capacitance of rectifier transistors and other parasitic capacitances on those nodes. The 34

47 3.2. Proposed rectifier Output dc Voltage (V) Effective threshold voltages (mv) rectifier efficienc scheme does no highly s biasing impleme schemat presente paper. Figure 3.7: left: Output voltage of the rectifier for a given input power as a function of effective threshold voltage of transistors (V th,n = V th,p ). right: Changing the effective V th of transistors in a four transistor cell inputs of the drivers are connected to the sinusoidal voltage of amplitude V RF. In Figure 3.8 at the startup there are no charge on capacitors C 1 and C 2. The sinusoidal voltage at the RF inputs creates a sinusoidal gate-source voltage (V GS ) on the transistors M1 and M 2 which results in charge transfer from the bias terminals (V BN/BP ) to the capacitors and slowly charges the capacitors. In steady state the output voltages of the NMOS driver (V O+/ ) vary between V B1 V DS,min < V O+/ < V B1 V DS,min +V RF C 1,2 C 1,2 + C load V B1 V DS,min +V RF (3.3) with 180 phase difference. The PMOS driver outputs (V O+/ ) change in 35

48 3.2. Proposed rectifier 1.25 v /NMOS_OUT; tran (V) /VBias<0> V (V) v /PMOS_OUT; tran (V) /VBias<1> V (V) time (ns) Figure 3.8: NMOS and PMOS driver stages. RF + and RF are connected to a sinusoidal voltage with amplitude V RF and V B1 and V B2 are the DC bias voltages (V B1 = V B2 = 0.7) right: V o+ outputs of the NMOS and PMOS driver settling to the steady state value Figure 3.9: connection of drivers to the rectifier transistors 36

49 3.2. Proposed rectifier the range of (3.4) where V DS,min is the minimum drain-source voltage drop on driver transistors. The approximations in Equations (3.3) and (3.4) assume C 1,2 C load. Setting the voltages given by Equations (3.3) and (3.4) equal to those at the gates of the rectifier transistors of Figure yields, V b1 = V L + V osn, V b2 = V H V osp (3.5) By meeting the condition given in Equation (3.5) the rectifiers in Figure 3.7 and 3.9 will have similar performances. Note that in steady state the currents passing through the driver transistors (M 1 and M 2 ) are negligible and only consists of the leakage current of transistors and capacitors. Therefore, the drivers can perform well even with small voltage amplitudes (V RF ) which is a key feature at very low powers where V RF is small Bias generation This section describes two different ways of bias voltages generation (V B1 and V B2 in Figure 3.8) used by drivers in each stage. a. Switched capacitor One way to create the bias voltages V B1 and V B2 is to connect a charged capacitor with initial voltage equal to the offset volt- 11 NMOS drivers equal to the gate voltages of NMOS transistors in Figure 3.7 and PMOS drivers equal to the gate voltages of PMOS transistors of the same Figure 37

50 3.2. Proposed rectifier ages V osn and V osp between V L and V H of each rectifier stage, respectively. The DC current through the biasing voltage sources is almost zero. In the beginning of the operation the driver capacitors (C 1 and C 2 in Figure 3.8) draw some current from the bias voltage source (V b ). After that the current through those voltage sources drop to almost zero. Therefore, placing a large enough charged capacitor (C bias ) instead of V osn and V osp provides the desirable bias voltages. C bias must be recharged every once in a while since it is continuously discharged by a (small) leakage current, however, the recharging frequency can be as low as a few khz. Note that the leakage of the capacitors are negligible when metal-insulator-metal (MIM) capacitors are used, in which case, the only leakage is through transistors. The low recharging frequency is desirable since it reduces the overhead power of the biasing circuit and increases the overall efficiency of the rectifier. The biasing circuit is shown in Figure This technique enables the rectifier to change the value of V osn and V osp dynamically, and thus, allows for improving performance at all powers. However, it requires an initial voltage source at the power up to start operation and therefore is suitable for semipassive tags. A small low-capacity battery should be included to supply the bias voltages when the biasing circuits are to startup for charging C bias of different stages and switch the transistors in the recharging circuit. Spectre simulations show that the average current through C bias capacitors in 0.13 µm technology can be as large as 8 na. This means that for 50 mv bias voltage variation using a C bias = 1pF, the recharge frequency must be as high as 160 khz. The high recharge frequency increases the power overhead of the biasing scheme and makes it less viable for low power 38

51 3.2. Proposed rectifier Figure 3.10: switched-capacitor biasing circuit operations. Although this frequency can be reduced to some extent by tolerating more voltage variation and using larger C bias s, switched-capacitor technique was not used in this project. b. Transistor Chain In this biasing technique, a number of transistors are connected in series (Figure 3.11). The dimensions of the transistors in the chain determine the value of the bias voltages that are generated. The current through the biasing network can be of the order of a few tens of na, and therefore the power consumption of the biasing network is minuscule. At the startup as the output of each rectifier stage increases the bias voltages (V osn and V osp ) also increase until the rectifier reaches its desirable operation. This technique has the following advantages: (a) considerably smaller die area compared to the switched-capacitor network since no large capacitor (C bias ) is required (b) makes the rectifier self-sufficient. In RFID tags self- 39

52 3.3. Performance NMOS driver PMOS driver VRF V out C L Bias Stage Figure 3.11: Two stage rectifier with transistor chain biasing. sufficient rectifiers are preferable since they do not require any additional components to function, e.g., an additional battery. 3.3 Performance In this section we review the performance advantages of the proposed stage High efficiency with small input amplitudes Different bias voltages,result in different voltage amplitudes where the efficiency peaks 12. To show this effect, two versions of the proposed rectifier one in 0.13 µm and the other one in 0.35 µm and their four-transistor cell counter parts where simulated. 13 All offset voltages are equal to 150 mv. 12 see Equation (3.2) 13 The biasing scheme does not have a prominent effect on the results because of small power over head of both schemes but transistor chain biasing is used in these simulations. 40

53 3.3. Performance The shift in performance is illustrated in Figure Figure 3.12.c plots the efficiencies of the rectifiers as a function of the input power. It is can be seen that the efficiency of the proposed stage maximizes for lower powers. This can also be seen that for low powers like 5µW where the four-transistor cell has an efficiency of as low as 14% the proposed stage has 47% efficiency. The optimum input amplitude has also decreased by approximately the value of the bias voltages (150 mv) 14. As it will be explained in more detail in section 4.2 this property can be used to reduce the input resistance of the rectifier which in turn relaxes the constraints on the quality factor of the matching circuit components and makes this rectifier very attractive to low-power applications. Since the presented rectifier uses the same operation principle as that of four-transistor cell (which is more efficient than Dickson-based rectifiers), the proposed stage easily outperforms Dickson-based rectifiers as well. 14 Note that for both four-transistor cell and the proposed stage the efficiency versus amplitude peaks at some V RF,opt and then decreases. That is the reason that the two graphs cross at Amp = 440 mv 41

54 3.3. Performance Rectifier output voltage (V) Proposed Circuit four-transistor cell Conversion efficiency (%) Input signal Amplitude (mv) (a) Proposed Circuit four-transistor cell Input amplitude (mv) (b) Figure 3.12: performance comparison of four-transistor cell and the proposed stage [27] 42

55 3.3. Performance Cascadability A number of rectifier stages are often connected in cascade to generate a larger output DC voltage from a small input amplitudes, a number of rectifier stages are connected in cascade. The problem is that the source of NMOS transistors in latter stages are connected to higher DC voltage. Because of the body effect 15 NMOS transistors have higher threshold voltage than those in former stages. This effect drops the efficiency of the rectifier when a large number of stages are connected in series 16. In the proposed rectifier higher offset voltage for NMOS transistors of latter stages can be chosen to compensate for the V th increase. Figure 3.13 compares the output voltage of the a four-transistor cell and a proposed rectifier for different number of stages. For four-transistor cell the output voltage will not increase by increasing number of stages more than four, but the output voltage of the proposed stage keeps increasing with the number of stages. As mentioned earlier the input impedance of a rectifier can be presented by a capacitance and an equivalent resistance. The value of the resistance is given by, R = V 2 RF 2P in (3.6) where V RF is the voltage amplitude at the input of the rectifier and P in is the input power of the rectifier (of which ηp in 17 goes to the output of the 15 Threshold voltage of transistors is given by V t = V t0 +γ( 2φ f + V SB 2φ f ), where phi f and γ are technology dependent constants and V SB is the source-bulk voltage of the transistor [11] 16 Here standard n-well CMOS process is assumed. In the tripple-well CMOS technology NMOS transistors can be put in separate wells to avoid body effect at the expense of higher technology cost 17 η is the conversion efficiency or simply efficiency which is defined as the ratio of 43

56 3.3. Performance 2.5 Output DC voltage (V) Proposed stage Four transistor cell Number of Stages Figure 3.13: Comparison of output voltage of a four-transistor cell rectifier and a proposed stage rectifier as a function of number of stages for a given input amplitude rectifier).in section 4.2 it is explained that sometimes for efficient matching we need to reduce the input resistance of the rectifier. Equation (3.6) implies that if the rectifier can consume P in at a smaller input voltage swing (V RF ) it has a smaller input resistance R. Smaller V RF gives smaller output voltage per rectifier stage, therefore a number of stages must be put in cascade to generate a certain output voltage. Cascading a number of rectifier stages to generate a sufficiently large output voltage from a small V RF is feasible only if rectifier stages are capable of efficient operation with small input swings, and if the efficiency does not drop by cascading stages. rectifier s output power over its input power. 44

57 3.4 Circuit design 3.4. Circuit design Number of stages Larger number of stage means smaller rectifier input resistance. As shown in Figure 1.3 and will be mathematically shown in section 4.2 lower input resistance decreases the rectifier input amplitude for a given power. However the rectifier can generate a larger DC output voltage with larger number of stages. In general there is an optimum value for the number of stages. This value can be found by co-simulation of the source impedance, matching circuit, and different number of stages. As a result of the optimization of the matching circuit and the rectifier, this work uses a two-stage rectifier with transistor chain biasing, as shown in Figure Sizing the driver transistors These transistors (M 1 and M 2 in Figure 3.8) do not conduct a large current in steady state. However at startup they have to charge C 1 and C 2 in Figure 3.8 with a very small input RF amplitude. Driver transistors must be large enough to conduct that current with the minimum input amplitude. The smaller the input amplitude becomes the larger driver transistors must be. Note that for small amplitudes these transistors operate in the subthreshold region. Similar to the active region equation the transistor current is linearly proportional to the W/L ratio of transistors 18. so increasing 18 Drain current is equal to I D = W µ L eff VthC 2 γ ox e q(v GS V T 0 )/mkt (1 e qv DS /kt ) 2 2Φ B +V SB where Φ B and γ are technology dependent constants [22] 45

58 3.4. Circuit design W/L ratio increases the current charging the capacitors. The amount of parasitic capacitance on the output nodes of the drivers puts a limit on how wide the driver transistors can get. Too much capacitance on the output of the drivers decreases the drivers output swing (Equations (3.3) and (3.4)) and consequently degrades the performance of the rectifier. This design uses W L = 10 µm 0.12 µm for all PMOS and NMOS drivers. The wide transistors guarantee that the drivers can function with amplitudes as low as 250 mv. These wide transistors in combination with 680 f F driver capacitors the output amplitude of drivers becomes almost 95% of the RF input amplitude Sizing the rectifier transistors These transistors shown as M 1 M 4 in Figure 3.9 are the transistors in charge of AC/DC conversion. There is an optimum value for the aspect ratios of these transistors. If they are too small, the voltage drop on them becomes too large and if they are too wide both the parasitic capacitance on the input RF nodes and reverse current leakage increase. In either case the efficiency degrades. The optimum value is a function of load current and the minimum input amplitude that the rectifier is being designed for Bias voltages and transistor chains The values of V BN and V BP can be used to set the optimum input amplitude/power. The proposed circuit uses two separate transistor chains one for biasing the NMOS transistors and the other one for biasing PMOS transistors. The optimum biasing voltages must be found in the schematic level simulations 46

59 3.4. Circuit design by use of ideal voltage sources. In the next step assuming the output voltages and optimum bias voltage values determined in the previous step, the chain can be designed. The bias current of the chains can be very small to reduce the power overhead of the biasing circuits. Figure 3.14 shows the behavior of a single-stage rectifier e.g. output voltage and efficiency, for different values of NMOS and PMOS aspect ratios and bias voltages for a given load and input amplitude. 19 It can be seen that increasing W n and W p increases that output voltage. This is because increasing transistors aspect ratio reduces the voltage drop on conducting transistors. But at some point making transistors wider will not help reducing the voltage drop anymore since transistors are deeply in triode and the V DS across them is fairly small. However The efficiency starts dropping for very wide transistors. This is because of the increased reverse current which drops the conversion efficiency. A similar argument holds true for the NMOS and PMOS bias voltages V N and V P in Figure Increasing bias voltage reduces the voltage drop on conducting transistors by increasing V GS of transistors while conducting forward current. On the other hand when the bias voltages become too large, the rectifier transistors do not turn completely off which leads to more reverse current and lower conversion efficiency. For all four parameters (W n, W p, V N, and V P ) a value near the peak efficiency point has been selected. Table 3.1 summarizes all design parameters. 19 The design parameters used in the design are determined after several sweeps to reach the optimum values. Graphs in Figure 3.14 are just examples of such sweeps on a singlestage rectifier. 47

60 3.4. Circuit design Figure 3.14: sweeping rectifier s design parameters 48

61 3.4. Circuit design Parasitic capacitances Rectifier stages have both high frequency and DC nodes. The parasitic capacitances do not have a destructive effect on the DC nodes but they can reduce the voltage swing on high frequency nodes. Some of the parasitic capacitors like the gate capacitance of transistors are already taken into account in the schematic simulation. However some of parasitic capacitances are layout dependent e.g. the capacitance between different pieces of conductors together and to the substrate. Interconnects usually are not considerably wide and their capacitance to other conductors can be minimized by proper spacing and the capacitance to the substrate can be kept small by using higher metal layers in the layout. The main potentially troublesome capacitance is the capacitance between the bottom plate of capacitors to the substrate. This parasitic capacitance is proportional to the value of the capacitor so its value can be assumed to be C b = αc where α is constant (the bigger the capacitor, the larger its bottom plate becomes which means more capacitance between the substrate and that plate). The input RF nodes (RF + / ) can either be connected to the top or the bottom plates of capacitors (Figure 3.15). In the former case where the RF input is connected to the top plate the swing that the rectifier/driver transistors see is equal to, V rect = V RF C load αc C load + (α + 1)C < V RF (3.7) To maximize the swing in this design the input nodes are connected to the bottom plates of capacitors. This forces a larger capacitance in the input. However this is not very concerning because 49

62 3.4. Circuit design C V rect Stage N V RF C b C load C pad C V rect Stage 1 C b C load Figure 3.15: equivalent input capacitance (input connected to the top plates of capacitors) as long as the number of stages is not very large the input capacitance is dominated by pads (and potentially protection circuits) the design uses dual MIM capacitors with α 1 The tradeoff between the larger swing and larger input capacitance due to capacitors connections must be more closely considered in the case of other type of capacitors like MOM capacitors with larger α values Design summary Figure 3.16 shows the final rectifier. To have a self-sufficient rectifier a transistor chain is used to bias different stages. All capacitors except the output decoupling capacitor are MIM capacitors. Since the linearity and parasitics of the output decoupling capacitor are not important the output decoupling capacitor is an NMOS capacitor. The transistor sizes are optimized for maximum efficiency. The dimensions are given in Table 3.1. The rectifier is designed to be matched to a 50 Ω source using series inductor matching (explained in section 4). In the design a 100 kω resistor is assume as the load. The bias voltages range is shown in Table 3.2. These 50

63 3.4. Circuit design Cd C Cd Cd C Cd N1.b ND.b PD.b P1.b N2.b ND.b PD.b P2.b VRF V out N1.a ND.a PD.a P1.a N2.a ND.a PD.a P2.a C L Cd C Cd C Cd Cd Bias Stage VN1 VP1 VN2 VP2 Figure 3.16: Final rectifier circuit. values assume that the output of the fist rectifier stage is at 260 mv and the second stage output at 520 mv. The first stage of the rectifier shown in Figure 3.16 does not have the rectifier capacitors C. The first stage capacitors can be remove to save area as long as the DC level of the input is not forced to zero by, say the matching circuit. For instance a parallel-inductor matching provides a DC short from the RF inputs to ground and the first stage rectifier capacitors are inevitable, however, the proposed system uses series matching with no DC path from the inputs to ground. Figure 3.17 shows the simulated performance of this stage with 100 kω output load respect to input amplitude and input power. The efficiency peaks at about 350 mv/ 4.25 µw input amplitude/ power. It is important to note that although the efficiency drops for amplitudes larger that 350 mv the output voltage keeps rising with input amplitude. 51

64 3.4. Circuit design Table 3.1: components values and dimensions Transistor W (µm) L(µm) N P N P PD PN Capacitors value(pf) W (µm) L(µm) C C d Table 3.2: value of bias voltages over process variations Bias voltage min/max (V) V N /0.18 V P /0.16 V N 2 0.2/0.23 V P / Efficiency (%) V OUT (V) Efficiency (%) V OUT (V) Amplitude (V) Input power (µw) Figure 3.17: rectifier simulated output voltage and power efficiency left: vs input amplitude right: vs input power 52

65 Chapter 4 Matching 4.1 Introduction In [7] three different matching techniques, i.e. transformer matching, series inductor, and parallel inductor are discussed. Transformer matching requires a transformer and is usually too costly [7]. Figure 4.1.(a) shows input matching by parallel inductor and Figure 4.1.(b) shows that with the aid of series inductor where, the parallel combination of resistor R and Cin represents the input impedance of the tag. In this figure R a is the antenna radiative resistance, V a is the antenna open circuit voltage when P avail watts power is available to the antenna as described in section 2.3. The matching network matches R a to the impedance seen by the antenna for maximum power transfer from the antenna to the transponder. In the parallel inductor matching, an external inductor is placed in parallel with the input capacitance of the chip, C in. This inductor resonates with C in, and the imaginary value of the impedance seen by the antenna becomes zero at the resonant frequency. The real part of the chip input impedance R and R a must be matched by proper design of the antenna and the rectifier. Although the parallel inductor matching provides a good ESD protection, in addition to matching [7], it is not suitable for weak input RF powers. At low input 53

66 4.1. Introduction Z in R a V rectifier V a L C in R (a) R a Z in L V rectifier V a C in R Antenna Matching Chip (b) Figure 4.1: (a) parallel inductor matching (b) series inductor matching powers a relatively large R a is required to generate the minimum voltage swing across the antenna to properly activate the rectifier. Because of the relatively long wavelength of the signal (approximately 30 cm) designing antennas with large radiative resistances (R a ) with small dimensions of a tag remains a challenge. As a result R a of RFID tag antennas typically remains in the range of a few tens to a few hundred of ohms. Using parallel inductor matching, an antenna with R a = 1 kω for 10 µw input power results in 8P avail R a =283 mv antenna open-circuit voltage (V a ) of which only half of this voltage goes to a matched load. Small input amplitudes are not desirable because rectifiers, typically, show a better conversion efficiency as the input amplitude increases. In series matching (Figure 4.1.b) an inductor is placed between the antenna and the chip. This inductor with the input capacitance of the chip form a LC-network that passively amplifies the input voltage amplitude. Series and parallel inductor matching networks are 54

67 4.2. Series matching capable of maintaining matching condition over a narrow range of frequency around the resonant frequency of the inductor and the parasitic capacitances. As the frequency of the input RF signal deviates from the resonant frequency of the matching network the matching becomes less effective and the chip reflects back greater portion of the incoming power. According to [1] tags must be capable of receiving RF signals in the relatively wide range of 860 MHz to 960 MHz. This implies that mismatch causes a drop in the power harvesting efficiency over a potentially wide range of frequencies. To overcome this problem, in section 4.3 an auto tuning system is introduced that monitors the rectifier output voltage and based on the voltage automatically tunes the center frequency of the matching network for the best matching on the entire frequency range. The presented system uses series matching which is primarily reviewed in the next section. 4.2 Series matching The presented system uses a series-inductor matching circuit. A typical value of R a in this type of matching is large enough for matching the rectifier and the antenna. The matching network passively boosts the voltage to supply a sufficiently large voltage amplitude to the rectifier. Fig. 4.1(b) shows a simplified equivalent circuit of the matching antenna, series matching inductor, and the chip input which is modeled by an equivalent resistance (R) and input capacitance (C in ). The voltage amplitude at the input of the chip is indicated by V rectifier which is the same voltage that drives the rectifier. The inductor has the quality factor equal to (Q L ). We also define ideal 55

68 4.2. Series matching tank quality factor as Q t = RC in ω 0. At the frequency ω 0 1/ LC in the series inductor resonates with C in. At this frequency the impedance seen by the antenna (Z in ) becomes real and its value becomes equal to the real value of the (non-ideal) inductor impedance plus the real value of the parallel R and C in impedance. Z in = Lω Q L + R 1 + Q 2 t (4.1) Assuming Q 2 t, Q 2 L >> 1 Equation (4.1) becomes, Z in = 1 C in ω 0 ( 1 Q L + 1 Q t ) = 1 C in ω 0 1 Q tot (4.2) For a matched system (R a = Z in 20 ), the non-ideal inductor dissipates some fraction of the available power (P avail ) and the rest goes into the chip. At resonance the real part of the inductor impedance (Lω/Q L ) and the input impedance of the chip (R/(1 + Q 2 t )) act like a resistive divider, so the share of the chip from P avail becomes, P R = P avail R/(1+Q 2 t ) R/(1+Q 2 t )+Lω 0/Q L = P avail 1+(1+Q 2 t )/Q L.Lω 0 /R Therefore the power available to the chip (P R ) is given by, P R = P avail Q2 t Q tq L P avail 1 + Qt Q L (4.3) 20 The optimum value of R a maximizes V rectifier. V rectifier = V a R/(1+Q 2 t ) R/(1+Q 2 t )+Lω/Q L+R a, replacing V a by 8P avail R a and setting dva dr a = 0 yields R a = Lω/Q L + R/(1 + Q 2 t ) = Z in 56

69 4.2. Series matching and results in a voltage amplitude given by Equation (4.4) at the input of the chip. V rectifier = 2P avail Q tot 2P R.R R = 2P avail (4.4) 1 + RC in ω 0 /Q L C in ω 0 From Equations (4.2), (4.3), and (4.4) the following rules of thumb can be concluded: 1. C in must be as small as possible. Setting dp R /dq t = 0 in Equation (4.3) shows that the optimum value for tank quality factor is Q t = 1. Since Q t = RC in ω 0, smaller C in allows for a bigger R. The larger R becomes, according to Equation (4.4) V rectifier becomes larger. Typically C in consists of the parasitic capacitances of the pad, ESD protection, and RFID tag input devices and there is a limit on how small it can get. Thus occasionally R also has to be reduced. This can be done by cascading a number of rectifier stages as explained in section The other reason to keep C in small is that in Equation (4.2) both 1/C in ω 0 and 1/Q t decrease with C in. This implies that the required R a of the matched antenna rapidly decreases with C in. For very small values of R a when R a becomes comparable to the ohmic resistance of the antenna, the ohmic dissipation of the antenna increases (Equation (2.2)) and degrades the efficiency of the antenna. 2. The quality factor of the series inductor must be much greater than that of the chip input impedance (Q t Q L.) This is 57

70 4.3. Adaptive matching resulted from Equation (4.3). It can be seen that the larger Q t the less power reaches the RFID chip. Additionally P R becomes less sensitive to Q t and Q t can become larger than unity without a significant drop in P R. 3. Rectifier must perform efficiently with low input voltage swing. Ideally if the rectifier be capable of generating required output voltage with a small voltage swing its input resistance becomes very small 21. For this rectifier both the tank quality factor Q t and the optimum V rectifier are small. Therefor the constraints on the quality factors of the matching network components become more relaxed and C in can become larger without causing much trouble. As seen in section 3.2 the value of optimum V RF can be controlled by changing the rectifier bias voltages. This becomes feasible by lowering V RF,opt of each stage and putting more rectifier stages in cascade. This feature makes the proposed rectifier attractive to low-power applications. 4.3 Adaptive matching The EPCglobal protocol requires tags to be capable of operation over the wide range of frequencies from 860 MHz to 960 MHz [1]. A simple matching network cannot achieve an effective matching over the entire range of operation. However the bandwidth is broken down to 500kHz channels, and the 21 it can be looked at as a load which draws some power from a small amplitude sinusoidal voltage source. For a given power the smaller the amplitude the smaller the equivalent input resistance, see Equation (3.6). 58

71 4.3. Adaptive matching reader uses one channel at a time for a given tag. 22 The proposed system tunes the resonant frequency of its matching network, around the frequency of strongest input signal. This way it improves the matching for a large range of frequencies. Figure 4.2 shows how tuning of the matching network by changing the input capacitance of the chip enhances the efficiency of the circuit. The tuning operation ensures that the tag operates near the optimum frequency of the matching network, and V rectifier remains large enough in the entire frequency range of 860 M MHz. Note that the real part of Z in at the angular frequency of ω equals r + R/(R 2 Cin 2 ω ) where r is the inductor series resistance. Unlike the parallel inductor matching, for series inductor matching the real part of the input impedance is a function of the input capacitance of the chip (C in ). This implies that in the tuning process when C in varies, R a must also be changed to meet the matching condition. However R a is a function of the antenna geometry and is constant for a given antenna. Inspite of this mismatch which slightly decreases the peak value of V rectifier curves in Figure 4.2 by increasing C in, tuning improves the performance (See Figure 4.2). In section 4.4 it is mathematically shown that the effect of mismatch caused by changing the input capacitance is much smaller than the matching improvement because of the tuning of the center frequency of the matching network. 22 The band of operation follows local regulations and is much narrower than 860 M MHz. For example the band of operation in north America is 902 M MHz and in Japan is 952M-954MHz 59

72 4.4. Adaptive matching versus fixed-matching for series inductor matching V rectifier (V) to 960 MHz Frequency (MHz) Figure 4.2: Tuning the center frequency of the matching network by switching in capacitors. R a = 7Ω, Q L = 60, P in = 10µW, C in = 600, 650, 700, 750 ff 4.4 Adaptive matching versus fixed-matching for series inductor matching In this section first a compact mathematical expression of the absorbed power under two condictions (a) for a fixed series inductor matching network RF input signal frequency (ω) which is not necessarily equal to the center frequency of the tank (b) for an adaptive-matching system where we have perfect matching at frequency (ω 0 ), but the center frequency of the tank is shifted to the frequency of RF input signal (ω) by adding input capacitance. Comparison between the two expression supports the need for 60

73 4.4. Adaptive matching versus fixed-matching for series inductor matching adaptive matching. Consider the series matching circuit if Figure 4.1. For sake of simplicity it is assumed that Q L 1 so all the absorbed power is dissipated in the input resistance of the chip (R). The tank quality factor is shown with Q The value of Z in at the angular frequency of ω is given by, Z in = Ljω + R RCjω + 1 (4.5) At the resonance frequency (ω 0 ) the input impedance becomes Z in (ω 0 ) = Ljω 0 + Z in (ω 0 ). R RCjω This value is real and for matching we must have R a = According to Equation (2.3) the power absorbed by the chip is equal to, Z in R P R = P avail (1 2 ) a (4.6) Z in + R a replacing Equation (4.5) and the expression for R a in Equation (4.6) gives the power dissipated by R. The result is a formidable equation which makes comparison difficult. However using ω 0 = 1/ LC in and Q = RC in ω 0, and the fact the variation of the RF signal frequency from the center frequency of the tank ( ω ω 0 ω 0 ) the result can reduces to, P R = P avail ( 1 ( ω ω 0 ) 2 ) 1 + Q 2 ( ω ω 0 ) 2 (4.7) In Equation (4.7) P R is the power received by the load R. The RF signal has the average power of P avail and the offset frequency between the RF signal frequency and the center frequency of the tank is shown with ω 23 According to Equation (4.1) with Q L 1 this value is equal to R a = R/(1 + Q 2 ) R/Q 2 61

74 4.5. Tuning loop (= ω ω 0 ). The second scenario assumes the same RF signal and matching network (values for L, R, R a, ω, and P avail are similar to the previous case). However, C in is increased to C in to tune the center frequency of the tank e.i. ω 0 = ω. The new Z in is given by, Z in = R 1 + Q 2 R Q 2 (4.8) Where Q = RC in ω is the new tank quality factor. Z in given by Equation (4.8) is not equal to R a = R/Q 2, therefore only a part of P avail is absorbed by R (P R P avail ). The amount of the power absorbed by R is, P R = P avail (1 Γ 2 ) = P avail 4(1 + ω ω 0 ) 2 (1 + (1 + ω (4.9) ω 0 ) 2 ) 2 For ω/ω = 10% Equation (4.9) anticipates an effective power matching (P R /P avail = 99%). Figure 4.3 plots Equation (4.7) and (4.9) for ω 0 = 960 MHz and Q = 10 (at 960 MHz)). It can be seen that the power reflection in adaptive matching is significantly smaller than that of fix-matching. 4.5 Tuning loop A feedback loop tunes the matching network to the strongest incoming RF frequency within the frequency range of operation. The loop is designed to be able to operate under a low supply voltage and consumes a small power. At the tag startup when the matching network is not properly tuned the rectifier cannot supply a large output voltage for the entire chip. At this 62

75 4.5. Tuning loop Normalized rectifier voltage (V/V) Adaptive Matching Fixed Capacitance Matching Frequency (Hz) x 10 8 Figure 4.3: Adaptive matching versus fixed-matching network for ω 0 = 960 MHz point only the tuning loop turns on. Because of the relatively small power consumption of the loop circuits, the V DD voltage does not drop drastically. The loop keeps changing the resonant frequency of the matching network by changing the input capacitance of the chip and measures the variations of the output DC voltage of the rectifier. A finite state machine (FSM) tries to keep the output supply voltage rising. After the tuning phase the power harvesting system is ready to provide larger load currents so the rest of the chip can turn on. Different blocks of the tuning loop are illustrated in Fig In every clock cycle the counter switches in/out a small capacitor in the input of the chip. At the same time the loop samples the supply voltage by a simple pass transistor switch and a sampling capacitor (C sample ). A Schmitt trigger comparator compares this sample with the value of the supply voltage half a clock cycle later and determines whether the change in the input 63

76 4.5. Tuning loop Series inductors 8 PMOS tuning capacitors Ra Va Cpar Rectifier V out CLKB CLK + - C sample UP C par CLKB FSM Chip UP Down Counter / Q D Counter up\down control signal Q CLK Figure 4.4: Tuning loop capacitance has resulted in an increase or decrease in the supply voltage value. The result is a 0 or 1 signal named UP. UP = 1 means that the supply voltage has increased and UP = 0 means that the supply voltage has decreased. Based on this knowledge, a finite state machine (FSM) generates a binary signal that controls the Count up/ down control signal of an 8-bit up/down counter. The output bits of the counter are connected to the control voltage (V ctrl ) terminals of PMOS capacitors pair. When V ctrl goes high, effective input capacitance seen from the gates of the PMOS pair increases, that in turn increases the input capacitance of the chip. The control loop changes the input capacitance, and thus the resonant frequency of the matching network, by switching on/off these PMOS pairs. The loop exploits a Schmitt trigger as opposed to a comparator to reduce the chance of wrong readings because of the fluctuations on the supply 64

77 4.5. Tuning loop Figure 4.5: FSM state diagram voltage at clock edges. This circuit keeps its output (the direction that the counter is counting) unchanged if the signal from the Schmitt trigger is high, i.e. the DC supply voltage increases or remains unchanged after an increase. Otherwise FSM changes its output signal. The state diagram of the FSM is shown in Figure 4.5. The output of the FSM goes to the up/down counter, shown in Figure 4.6. At each instant of time bits 1 to k (out of eight bits of the counter) is 1. At the next negative edge of the clock signal, if the counter up/ down control signal equals to 1 counter sets k + 1 th output bit, otherwise it resets the k th output bit. In this counter a maximum of two flip-flops see the clock signal at each clock edge. This property helps to keep the dynamic power consumption of the circuit low even when the number of bits is more than eight[26]. 65

78 4.5. Tuning loop Up/ Down control signal D SET Q Q 1 Q 2 D SET Q D SET Q Q 7 Q 8 D SET Q CLR Q CLR Q CLR Q CLR Q CLK Figure 4.6: Counter 66

79 Chapter 5 Experimental results As a proof of concept, a CMOS chip in IBM 0.13-µm technology was fabricated and tested. Figure 5.1 shows the die micrograph. The area of the chip is 1000 µm 700 µm, and the chip is pad limited. The fabricated chip includes the proposed system with adaptive matching control circuits, two copies of proposed rectifier one with and one without internal biasing. The outer pad ring on the top and in the bottom are related to the complete proposed system. The input RF signal pads, system output voltage, reset signal of the digital blocks, external clock signal for the sampling and the finite-state machine as the main siganls and reference current for the Schmitt trigger, 3-bit binary encoded 8-bit output of the counter, a buffered version of the output of the Schmitt trigger, and bufferred Up/Down control signal from the FSM to the counter as observable test points and correction signals 24. These signal are connected to ESD diodes. The rest of the pads are ground pads, RF inputs of the other two rectifiers, and four bias signals for the proposed rectifier without internal biasing. These signals are not connected to ESD diodes and were meant for probing. However later on they were tested by aid of wire-bonding. 24 Schmitt trigger could stop working if its bias current was not sufficient 67

80 5.1. Test setup ESD diodes were only connected to the pads which were connected to the package to make handling of the packaged chips easier. For those of pad which are being probed ESD problems can be prevented by connecting all the equipment and people to a common ground and ESD diodes can be avoided so reduce the input parasitics. When we eventually tested unprotected pads by wirebonding them to the PCB, chips were treated with extra care to avoid any ESD incidents. Table 5.1: Pins with ESD protection Pin Description in +/ RFdifferential inputs V dd T est external supply for test point buffers RST reset signal for the FSM and the counter B 1 3 Binary encoded output of the counter V out output of the rectifier CLK clock signal for adaptive matching circuit I ref reference current for the tail current of the schmitt trigger U P D Buffered Up/Down signal from the FSM CM P Buffered output of the schmitt trigger Table 5.2: Pin without ESD protection inmf T 1+/ RF differential inputs of the proposed rectifier without internal biasing V N 1,2 andv P 1,2 Bias voltages of the proposed rectifier without internal biasing V out,1 output of the proposed rectifier without internal biasing inmf T 2 +/ RF differential inputs of the proposed rectifier with internal biasing V out,2 output of the proposed rectifier with internal biasing 5.1 Test setup To test the chip, four different printed-circuit boards (PCB) were designed and fabricated. The first PCB is shown in Figure

81 5.1. Test setup Figure 5.1: Die micrograph Functionality The first PCB is designed to verify the functionality of the adaptive matching circuits. This PCB included all the additional circuits to generate test signals to monitor the behavior of the tuning loop that includes proper clock signal, reset signal, and the bias current for the schmitt trigger circuit. The schematic of the test board is shown in Figure 5.2 Using a micro-switch, a de-bouncer 25, and a 7555 timer 26 a mono-stable clocking circuit is built. Everytime that the micro-switch is pressed this circuit generates a low clock signal with 2 µsec pulse width. This way all outputs and test-points of the adaptive matching circuit could be observed after each clock edge. The pulse-width of the clock signal should be less than 10 µsec. The reason for that is at the negative edge of the clock signal the output of the rectifier is sampled. This sample must be unchanged until it is processed 25 MAX6816EUS 26 CMOS variation of 555 times IC which has a higher operating frequency 69

82 5.1. Test setup VDD CLK DE- BOUNCER 1nF 1kΩ 7555 VDD 2kΩ Differential RF signal DUT CLK CLK Iref VddTest RST Vout B1-3 cmp Up/ Down 5kΩ 1kΩ VDD ~2 µsec Iref A VddTest 10kΩ RST 1MΩ VDD VDD 5kΩ 1kΩ 1nF Figure 5.2: Schematic of the test board at the next positive edge. The leakage current tends to discharge the sampling capacitor, therefore the time difference between the negative-positive edge should remain small. However, the period of the clock signal can be arbitrarily large. The bias current of the schmitt trigger is controlable through a variable resistor. The reset signal (triggered by a second micro-switch) can be used to reset the state of the counter and the FSM. The test setup is shown in Figure 5.3. A signal generator generates a single-ended RF signal with required power and frequency. Since the rectifier uses a differential input signal, a balanced-to-unbalanced transformer (BALUN) is used. BALUN s 70

83 5.1. Test setup generate a differential output with 0 V common-mode level from a singleended input. As explained in section the fabricated rectifier lacks the rectifier capacitors in the first stage. Therefore a DC block is inserted between the BALUN and each of the circuit s RF inputs to enable the rectifier to change its input DC level. DC blocks are very large capacitors (2.2 µf) and act as short-circuit at the frequencies of operation and only block the DC level of the signal. The differential output of the BALUN (after passing through the DC-block circuits) goes to two SMA connectors on the PCB and after going through the series matching inductors goes to the (packaged) chip. The RF PCB traces are kept much shorter than the signal wave-length (< 2 cm/30 cm) therefore there are no transmission lines used on the PCB. Since the output node of the rectifier is connected to an output pad without any buffers, its voltage be forced by connecting a voltage source like signal generator or DC voltage source to it. Note that this is the same node that the adaptive matching circuit monitors its voltage. So the function of the adaptive matching circuit can be verified by applying some particular input voltage to the input of the adaptive matching circuit and clock the circuits and check if all intermediate and output signals are fine. Using one signal generator the clock signal signal for sampling switch was generated. Using another signal generator (sycronized with the first generator) a square wave signal with DC between 0.4 V and 1 V and small peak-to-peak voltage was generated. This signal was applied to the output votlage of the rectifier (the same voltage that the tuning loop samples). By varying the peak-topeak value of the second voltage source and observing the buffered output of the comparator the sensitivity of the schmitt-trigger was measurred about 71

84 5.1. Test setup Signal Generator Test PCB 50Ω DUT DC BLOCK SMA connectors BALUN Figure 5.3: Test setup 10 to 20 mv, with bias current of 600 na. The power consumption of the entire feedback loop was measured by applying 400 mv and 500 mv DC voltage sources to the output of the rectifier while a 1 MHz clock signal was being applied to the system. The current drawn from each DC source was measured to be 1.5 µa and 1.6µ A, respectively. This board uses fixed value surface mount device (SMD) inductors for series matching. There are two problems with these inductors. First the inductors quality factors drops to about 60 at 1 GHz. Second their values are fixed, therefore there is no room for fine-tuning the input resonance frequency which must ideally be at 960 MHz. This is why, for some of our experiments, we designed and used PCB s without SMD type matching inductors. Instead, PCB traces were used to create the required series matching inductance. Design details are reviewed in section Figure 5.8 shows these PCB s. RFID tags typically do not use packaged-chips because of the size and price constraints. Flip-chip and wire-bonding are usually used to connect 72

85 5.1. Test setup PIN i-1 PIN i 3.75fF 2Ω 254.7pH 0.4 pf 0.4 pf 3.75fF Conneted to pads on the die PIN i+1 Figure 5.4: Package model for CFP24 the chip to the antenna. These types of connections reduce parasitics in the input of the chip and minimizes the area taken by the chip. Wire-bonding is used to connect the die to the PCB traces in some of our PCB testboards. In this method the bare die is glued on the PCB surface and then using a wire-bonder the pads are connected to the PCB traces using thin gold wires. This method reduces all parasitics (inductive, capacitive, and resistive) on the pad. Figure 5.4 shows the equivalent lumped model of the package provided in CMC design kit. Because of the large package parasitic capacitances (two 0.4 pf capacitors) and its large series resistance (2 Ω) it becomes imperative to use wirebonding when high efficiency is required. Since the functionality of the adaptive matching system is verified earlier, the latter PCB s do not include the clock generation circuits. A signal generator can take over the clock generation. 73

86 5.1. Test setup Tuning PCB design Agilent ADS-Momentum EM simulator was used to model the impedance of the PCB traces. EM simulators need substate information to calculate S-parameters for a given structure. The test PCBs use the low-cost FR4 substrate with 1 oz of copper. The relative permitivity (ε r ) of FR4 boards varies between 3.8 to 4. The thikness of the FR4 substrate is 62 mil and 1 oz copper translates to 1.4 mil trace thickness. With resistivity equal to 1.68 µω cm the copper traces have sheet resistance of almost 0.5 mω/square. The FR4 substrate profile is summarized in Table 5.3 and Figure 5.5 Trace Copper FR4 Figure 5.5: FR4 PCB substrate Table 5.3: FR4 substrate profile parameter value unit substrate thickness 62 mil. conductor thickness 1.4 mil. ε r,f R sheet resistance 0.5 mω/square After laying out the PCBs of Figure 5.8 in Momentum layout environment the S-parameters where calculated by the simulator. This data is used to find the inductance and quality factor of the PCB traces. The simulated values are shown in Figure

87 5.1. Test setup Figure 5.6: Inductance and quality factor of trace-inductors left: maximum inductance right: minimum inductance As marked in Figure 5.8 the inductors have a bend in the middle. By adjusting the length of this bend, the value of the inductor changes which is used for fine-tuning the center frequency of the matching network. In Figure 5.6 the inductance and quality factor is plotted for the two cases where the inductor has its maximum and minimum value. It can be seen that the inductance can be varied by approximately 40%. Also the inductors have very high quality factors (> 105) compared to SMD inductors. There are two reason for the high Q. (a) PCB traces can be very wide therefore their AC resistance can potentially be low. (b) Strip inductors typically have higher quality factor and self-resonance frequency compared to spiral inductors Therefore they are attractive to very high frequency applications [15] 75

88 5.1. Test setup Tuning results Figure 5.8 shows the PCB used in this measurement. The bent inductor was used to adjust the center frequency around 910 GHz. Figure 5.7 shows how changing the chip input capacitance can improve matching over a wide frequency range. Eech graph is the output voltage of the rectifier versus frequency for a given input capacitance. It is obvious that the output voltage droops rapidly when the input freq deviates from the center frequency (where the matching is the best). However, by changing the input capacitance the output voltage always remains close to the maximum value, hence the tag can almost function equally well over the 55 MHz frequency bandwidth. The reason that the capacitance change does not cover the entire bandwidth is the underestimation of the ESD capacitive parasitics in the input. The large fixed-parasitic capacitance of the ESD devices reduces the maximum to minimum capacitance value ratio and limits the range of the frequency that the resonance frequency can have Rectifier performance In the litrature the efficiency of rectifier is usually measured by applying a given power (P sig ) to the input of the rectifier. The power entering the rectifier is equal to P sig (1 Γ 2 ) (Equation 2.5). Γ is the same parameter as S 11 and can be measured by a vector network analyser (VNA). The output power is the square of the output DC voltage divided by the load resistance. The ratio of the the output power and the power entering the rectifier is the recitifer efficiency [20, 24]. Since the output of the normal VNA is 76

89 Normalized Output Voltage (V/V) 5.1. Test setup % 55MHz Frequency (MHz) Figure 5.7: Measured output voltages for three different input capacitances single-ended, this method is only applicable to rectifiers with single-ended RF inputs. [24] uses a 4-port programmable network analyser (PNA) to measure the reflection coefficient for a four-transistor cell. However this equipment is not available in our test-lab. The other way is to perfectly match the rectifier to the load at some frequency, and then assume that Γ 0 [20]. This is not an easy task without knowing the the input resistance of the chip, and takes many trial and error efforts to finally achieve matching. This method is useful for verfying results measured using the PNA and is not very precise for performance measurements. The approach taken in this work is to model every component in the 77

90 5.1. Test setup signal path and then de-embbed them. The test-setup is similar to the one in Figure 5.3. The PCB used is shown in Figure 5.8. It uses a PCB-trace inductor for series matching and the die was directly wirebonded to the PCB traces. The first step was to find the frequency where we had the best matching and measure the output voltage as a function of signal generator output power. The bias voltages the rectifier are adjustable using four variable resistors on the PCB. The bias voltages where adjusted for the maximum output voltage. The next step is to de-embedd the effect of different components to find the efficiency of the rectifier. In the de-embbeding process the first component that was models was the BALUN 28. This BALUN operates from 4 MHz to 6.5 GHz and maintains phase match of better than ±1%. Unlike other BALUNs, it matches to 100 Ω differential output resistance. The return losses for the input, non-inverting output, and inverting output is typically less than -30dB, -30dB, and -15dB [2]. The BALUN input was connected to the 50 Ω output of a signal generator and its outputs were connected to the 50 Ω inputs of an oscilloscope. The input power was read off the signal generator and the output power was calculated using the voltage amplitudes measured by the oscilloscope. The equivalent model of the BALUN is shown in Figure 5.9. It is similar to that shown in Figure 2.7 except that the loss of the BALUN must also be accounted for by subtracting the loss in db from the power generated by the signal generator (in db). DC blocks are 2.2 µf capacitors connected to high-frequency connectors. According to the datasheet their loss is less than 0.5 db. Their effect can Phase matched BALUN from Picosecond 78

91 5.1. Test setup Figure 5.8: Test PCB s left: functionality middle: entire system right: rectifier performance 79