An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.3, JUNE, 2015 ISSN(Print) ISSN(Online) An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL Jong Mi Lee, Dong-Woo Jee, Byungsub Kim, Hong-June Park, and Jae-Yoon Sim Abstract This paper presents a 1.9-GHz digital ΔΣ fractional-n PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dbc/hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region. Index Terms ΔΣ modulator, FIR filtering, fractional-n PLL, frequency synthesizer, phase noise, TDC, phase rotator I. INTRODUCTION The differential signaling is widely used for highspeed interface because of its superior immunity to environmental noise and the low EMI. The digital circuits shrink rapidly with the advent of recent semiconductor processes. Also the supply voltage is Manuscript received Oct. 21, 2014; accepted Dec. 24, 2014 of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Gyeongbuk, Korea jysim@postech.ac.kr reduced to about 1 V for the state-of-the-art semiconductor processes. Efforts are driven to develop the CMOS inverter-based differential signaling schemes [1, 2]. The fractional-n PLL with a DSM-driven divider [3] in feedback loop has been a general architecture in frequency generation for wireless and wireline applications. While the DSM provides nearly limitless resolution in frequency generation, the trade-off in filtering between in-band VCO noise and DSM noise eventually limits the overall noise suppression. Various methods have been proposed to suppress the DSM noise. Use of a low-pass noise-shaping TDC [4] can be an approach to reduce high-frequency part of the DSM noise. To obtain the stability, however, the constraints on the bandwidths of noise-shaping TDC and PLL loop eventually limits the designable loop bandwidth of PLL. To relieve the trade-off limitation, FIR filtering technique has been an actively researched topic since it simply performs running averaging of DSM noise without affecting PLL loop dynamics. For the summing operation in FIR filtering, analog implementations such as phase blending [1] and the use of multiple CPs, PFDs, and dividers [2, 5, 6] suffer from power overhead and matching requirements as the number of taps increases. Recently, an eight-tap digitaldomain FIR filtering scheme was implemented in an alldigital PLL [7]. However, a complicated digital-domain calculation is needed for gain matching between TDC path and FIR filtering path. Moreover, the maximum number of taps in previously reported implementations is only eight, resulting in the first zero falls on 1/8 of reference frequency and little filtering effect on in-band frequency region.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.3, JUNE, allocated as the tap experiences more delay. The 32nd tap is provided by PR-TDC path, and its output is added up at TDC output stage, completing the 32-tap FIR filter. The gain through PR and TDC for 32nd tap should match the gain through digital logic for other taps. For this, a gain factor (G A ) is allocated for scaling the 31-tap FIR filter output. To obtain requirements on G A, the desired PR-TDC gain can be derived as a function of G A. If the 32nd tap were implemented with digital logic as the other taps, the gain should be 32 G A, resulting in Fig. 1. Block diagram of the proposed PLL. This paper presents a 32-tap FIR-embedded digital fractional-n PLL. The contributions of this paper are 1) proposing a circuit scheme to simply extend the number of FIR taps without complicated calculation for gain matching, 2) presenting analyses and a design method to find the optimum number of FIR taps when TDC resolution is given, and 3) the first demonstration of the in-band noise filtering with 32-tap FIR filter. Section II describes circuit details of the proposed FIR-embedded digital PLL. Section III presents analysis to find the optimum number of taps. Section IV shows chip measurement results, and Section V concludes this work. II. CIRCUIT DESCRIPTION Fig. 1 shows circuit diagram of the proposed PLL which follows an overall architecture of phase rotator (PR) based fractional division scheme. The phase rotator is implemented with a dual-referenced interpolator [8] controlled by a 3rd order DSM output. An LC-DCO generates complementary 1.9GHz outputs followed by two toggle D-flipflops providing four-phase 950 MHz. A phase expander with inverter-based averaging circuits generates 8 seed phases for the dual-referenced interpolation which divides one period of 950 MHz into 32 steps. Therefore, 2 TDCO is divided into 32 steps, where TDCO represents one period of DCO output. For FIR filtering, DSM output is applied to a chain of 31 flipflops, generating 31 taps of FIR filter. Since DSM output represents frequency, an incremented weighted sum of tapped outputs forms a phase-domain 31-tap alldigital FIR filtering. In other words, larger weight is (2 T DCO ) /32/ Δt TDC = 32 G A (1) where Δt TDC is the resolution of TDC. In this work, G A was chosen to be 1/4, which can be simply implemented by bit shifting without complicated digital-domain gain adaptation. Instead, Δt TDC is controlled to be (2 T DCO )/256. Since 2 T DCO is 1/950MHz or 1052 ps, the target Δt TDC becomes about 4 ps. The TDC is designed with a vernier delay chain whose resolution is adjusted by a delay control loop. The maximum output from the proposed phase-domain 31- tap FIR is 496 (summation from 1 to 31), so the output needs to be expressed with a 9b. Since the resolution of PR is 1052 ps/32 which corresponds to the resolution of 32nd tap, the LSB in 9b FIR output corresponds to 1052 ps/(32x32) or almost 1 ps. Therefore, the chosen Δt TDC of 4 ps is 4x bigger than the resolution of FIR filter. This work claims that the use of finer resolution in 31-tap FIR filtering still helps noise suppression even used with coarser TDC resolution for 32nd tap. Detailed analysis for finding the optimum resolution of FIR filter will be presented in the next Section. The block in dotted line was synthesized with standard cells. Fig. 2 shows the Δt TDC calibration scheme. The Δt TDC is controlled with two loops. The upper loop finds a 5b binary code (C1[4:0]) to equalize 16 τ 1 to 2 T DCO. The second loop adjusts 16 τ 2 to be equal to τ 1 with a code (C2[4:0]). Thus, τ 2 is eventually adjusted to (2 T DCO )/256 corresponding to about 4 ps. Though τ 2 is conceptually drawn with a delay cell in Fig. 2, it was implemented with a vernier delay which is replica cell in TDC. This calibration process for Δt TDC is performed during initialization. When the process is completed, these loops are turned off with C2[4:0] stored. The obtained C2[4:0] is applied to TDC.

3 344 JONG MI LEE et al : AN IN-BAND NOISE FILTERING 32-TAP FIR-EMBEDDED ΔΣ DIGITAL FRACTIONAL-N PLL 3 rd Order DSM [ : ] [ : ] Fig. 2. Block diagram of Dt TDC calibration scheme. III. OPTIMUM NUMBER OF TAPS The effect of phase noise generated by DSM decreases as the number of FIR taps increases. On the other hand, the in-band phase noise (L) caused by a finite TDC resolution is fixed and is given by [9]. Delta Sigma noise with the N tap FIR filter Fig. 3. Modeling of N-tap FIR filter to simulate the effect of DSM-driven phase noise. L = (2π) 2 /(12 F ref ) ( Δt TDC /T DCO ) 2 (2) The ideal FIR-filtered DSM noise can be estimated by MATLAB with the schematic in Fig. 3. Simulated DSM noise is shown in Fig. 4 for different tap numbers varying from 8 to 64. The simulated TDC noise is also plotted for a reference. This reveals that increasing the number of taps more than 32 barely helps in overall noise suppression since the maximum noise level is rather limited by TDC resolution. Therefore, 32 can be an optimal candidate for the minimum number of taps which can eliminate the trade-off limitation in the choice of bandwidth. However, this analysis assumes an ideal FIR filter as in Fig. 3, so it can be valid only when FIR filter perfectly works. In the digital PLL, where FIR filtering function is embedded by using TDC operation, the resolution of TDC should be also considered. In the proposed scheme, the 32nd tap of FIR filter is provided through TDC path and summed with 31-tap digital FIR filter output. While the LSB of 31-tap FIR output represents 1 ps, Δt TDC is 4 ps which is 4x bigger than the resolution of digital FIR filter. Therefore, it is necessary to evaluate FIR filtering performance if one tap is 4x coarser than other 31 taps. To obtain the effect of TDC and FIR resolutions on the phase noise at PLL output, a closed loop PLL model [10] is Δt TDC set up and is simulated with MATLAB. Fig. 5 Phase Noise[dBc/Hz] Fig. 4. Simulated phase noise with 8, 16, 32, and 64-tap FIR filter. shows simulated phase noise at PLL output as the number of taps varies from 8 to 32 for three cases (16 ps, 8 ps, and 4 ps) of Δt TDC. When the Δt TDC is large (16 ps and 8 ps) as in Figs. 5(a) and (b), noise suppression is rather limited by Δt TDC, where increasing the number of taps over 8 and 16 does not help further noise suppression, respectively. On the other hand, when Δt TDC is small (4 ps) as in Fig. 5(c), the DSM noise is effectively filtered by 32 tap FIR filter. Fig. 6 summarizes simulated maximum phase noise level at PLL output for various resolutions of TDC and digital FIR. When Δt TDC is small enough (e.g. 2 ps), it does not limit the noise filtering by FIR. In this case, the

4 Output Phase Noise [dbc/hz] JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.3, JUNE, (a) DtTDC = 16 ps (b) DtTDC = 8 ps (c) DtTDC = 4 ps Fig. 5. Simulated closed loop phase noise as the number of taps varies from 8, 16, and 32 for three cases of DtTDC (16 ps, 8 ps, 4 ps). Fig.5(a) Fig.5(b) Fig.5(c) # Fig. 6. Summary of phase noise simulation. performance is dominated by the resolution of FIR (i.e. the number of taps). However, as ΔtTDC increases, it becomes another limiting factor in the maximally achievable noise suppression. Once the noise level is limited by FIR, finer resolution of TDC does not give further benefit. Therefore, the optimum number of taps with given ΔtTDC can be chosen where the horizontal line crosses the asymptotic diagonal boundary. In this work, with the given ΔtTDC of 4 ps, the optimum number of taps is in between 32 and 64. We selected 32. This simulation validates that 31-tap digital FIR with 1 ps resolution still works well with the 32nd tap with 4 ps resolution. Fig. 7 shows simulated digital code at the input of loop filter in locked state, showing that fluctuations in code are effectively reduced by the proposed filtering. Fig. 7. Transients of input codes of loop filter. IV. MEASUREMENTS The proposed PLL was implemented in 0.11 μm CMOS (Fig. 8). The core area is 0.84 mm2 with LCDCO area of 0.49 mm2. For comparison, the chip was designed to include three options; 1) conventional scheme with a dual-modulus divider only, 2) dual-referenced PR without FIR filtering, and 3) dual-referenced PR with FIR filtering. Fig. 9 shows measured phase noise for option 1) and 2) with the reference frequency of 57 MHz. The output frequency and the loop bandwidth were set to GHz and 3 MHz, respectively. The use of PR instead of dual-modulus divider reduces the phase noise by 15 db. To verify the effect of the proposed FIR

346 JONG MI LEE et al : AN IN-BAND NOISE FILTERING 32-TAP FIR-EMBEDDED ΔΣ DIGITAL FRACTIONAL-N PLL Table 1. Performance comparioson Proposed [7] [1] [2] [5] [11] [4] Output Freq[GHz] 1.81~.

5 346 JONG MI LEE et al : AN IN-BAND NOISE FILTERING 32-TAP FIR-EMBEDDED ΔΣ DIGITAL FRACTIONAL-N PLL Table 1. Performance comparioson Proposed [7] [1] [2] [5] [11] [4] Output Freq[GHz] 1.81~ f BW [Hz] 3M 1M 3.2M 1M 200k 3.2M 1M In-band PN[dBc/Hz/] Method Digital FIR+PI Digital FIR FIR+PI FIR FIR PI Noise Reshaping Power[mW] Area[mm 2 ] 22.8 (@DCO 13.2) (@DCO 0.49) CMOS[nm] VCO LC LC Ring Ring LC LC LC TDC, Delay Control Block Digital Block LCDCO Fig. 8. Chip photo. PR, Phase Expander, etc. Dual-modulus divider Fig. 10. Measured phase noises without FIR filtering (option 2) and with FIR filtering (option 3). with previously reported fractional-n PLLs. Compared with the previous approach with analog-domain 8-tap FIR filtering [1] consuming 13.2 mw without VCO, the proposed digital-domain 32-tap FIR filtering consumes less power of 9.6 mw without DCO. 15dB V. CONCLUSIONS Dual-referenced PR Fig. 9. Measured phase noises with conventional dual-modulus divider (option 1) and dual-referenced PR without FIR filtering (option 2). filtering, Fig. 10 compares smoothed plots of phase noise with the option 2) and 3). The proposed scheme (option 3) shows a well-regulated phase noise of less than dbc/hz in entire range inside the bandwidth of 3 MHz, while the option 2) suffers from unfiltered inband DSM noise. The suppression in the maximum noise level is about 5 db. Table 1 compares the proposed PLL This work firstly demonstrates a 32-tap FIR filtering embedded in a fractional-n PLL for actual in-band noise suppression. To increase the number of taps with minimal cost in hardware and power consumption, we propose a phase-domain digital FIR and a TDC gain calibration schemes. Design considerations are also addressed in choosing the optimum number of taps when TDC resolution is given. To verify the proposed circuit and design method, a 1.9-GHz digital ΔΣ fractional-n PLL was implemented in 0.11-μm CMOS. Measurements show a well-regulated inband phase noise of less than -100 dbc/hz for the entire range inside the bandwidth of 3 MHz, revealing the proposed schemes are promising in the design of low-noise PLL with FIR-embedded architecture.

$1-fref BW 1 GHz fractional-n PLL with FIRembedded phase-interpolator-based noise filtering, in ISSCC Dig. Tech. Papers, Feb. 2011, pp.94-95 [2] X. Yu, Y. Sun, L. Zhang, W. Rhee, and Z.$ $Wang, An FIR-embedded noise filtering method for ΔΣ fractional-n PLL clock generators, IEEE J. Solid- State Circuits, vol. 44, no. 9, pp. 2426 2436, Sep. 2009. [3] A. Kavala et a.$ $, A 2GHz fractional-n digital PLL with 1b noise shaping ΔΣ TDC, IEEE J. Solid- State Circuits, vol. 47, no.4, pp. 875 883, Apr. 2012. [5] X. Yu et al.$

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.3, JUNE, REFERENCES [1] D.-W. Jee, Y. Suh, H.-J. Park, and J,-Y. Sim, A 0.1-fref BW 1 GHz fractional-n PLL with FIRembedded phase-interpolator-based noise filtering, in ISSCC Dig. Tech. Papers, Feb. 2011, pp [2] X. Yu, Y. Sun, L. Zhang, W. Rhee, and Z. Wang, An FIR-embedded noise filtering method for ΔΣ fractional-n PLL clock generators, IEEE J. Solid- State Circuits, vol. 44, no. 9, pp , Sep [3] A. Kavala et a., A PVT-compensated 2.2 to 3.0 GHz digitally controlled oscillator for all-digital PLL, Semiconductor Technology and Science, Journal of, vol.14, no.4, pp , Aug [4] D.-W. Jee et al., A 2GHz fractional-n digital PLL with 1b noise shaping ΔΣ TDC, IEEE J. Solid- State Circuits, vol. 47, no.4, pp , Apr [5] X. Yu et al., A ΔΣ fractional-n synthesizer with customized noise shaping for WCDMA/HSDPA applications, IEEE J. Solid-State Circuits, vol. 44, no. 8, pp , Aug [6] M. Kondou, A. Matsuda, H. Yamazaki, and O. Kobayashi, A 0.3 mm 2 90-to-770 MHz fractiona- N synthesizer for a digital TV tuner, in ISSCC Dig. Tech. Papers, Feb. 2010, pp [7] I.-T. Lee, H.-Y. Lu, and S.-I. Liu, A 6-GHz alldigital fractional-n frequency synthesizer using FIR-embedded noise filtering technique, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 5, pp ,May [8] D.-W. Jee et al., A FIR-embedded phase interpolator based noise filtering for widebandwidth fractional-n PLL, IEEE J. Solid State Circuits, vol. 48, no. 11, pp , Nov [9] R. B. Staszewski, P. T. Balsara. All-Digital Frequency Synthesizer in Deep-Submicron CMOS. Hoboken, NJ: Wiley, [10] M. H. Perrott, M. D. Trott, and C. G. Sodini, A modeling approach for Σ-Δ fractional-n frequency synthesizers allowing straightforward noise analysis,ˮ IEEE J. Solid-State Circuits, vol. 37, no. 8, pp , Aug [11] M. Zanuso, S. Levantino, C. Samori, and A. L. Lacaita, A wideband 3.6 GHz digital ΔΣ fractional-n PLL with phase interpolation divider and digital spur cancellation, IEEE J. Solid-State Circuits, vol. 46, no.3, pp , Mar Jong Mi Lee was born in Seoul, Korea, on She received the B.S. degree in the Department of Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in She is currently pursuing the Ph.D. degree in the Department of Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea. Her interests include analog/digital frequency synthesizer PLL and ultra-low-power analog circuits. Dong-Woo Jee received the B.S., M.S., and Ph.D. degrees in electronic and electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2006, 2009, and 2013, respectively. From 2011 to 2012, he was a Visiting Researcher with the University of Michigan, Ann Arbor, MI, USA. In 2013, he joined IMEC in Leuven, Belgium, where he is currently working as an Analog IC Designer. His research interests include circuit technique for scaled CMOS device, analog/digital frequency synthesizer PLL, ultra-lowpower clock generation for sensor node system, and analog circuits for biomedical applications. Dr. Jee was the recipient of the Gold Prize at the 17th Human Tech Paper Award hosted by Samsung Electronics in Byungsub Kim received the B.S. degree in Electronic and Electrical Engineering (EEE) from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2000, and the M.S. (2004) and Ph.D. (2010) degrees in Electrical Engineering and Computer Science (EECS) from Massachusetts Institute of Technology (MIT), Cambridge, USA. From 2010 to 2011,

348 JONG MI LEE et al : AN IN-BAND NOISE FILTERING 32-TAP FIR-EMBEDDED ΔΣ DIGITAL FRACTIONAL-N PLL he worked as an analog design engineer at Intel Corporation, Hillsboro, OR, USA.

Kim received several honorable awards. In 2011, He received MIT EECS Jin- Au Kong Outstanding Doctoral Thesis Honorable Mentions, and IEEE 2009 Journal of Solid-State Circuits Best Paper Award.

7 348 JONG MI LEE et al : AN IN-BAND NOISE FILTERING 32-TAP FIR-EMBEDDED ΔΣ DIGITAL FRACTIONAL-N PLL he worked as an analog design engineer at Intel Corporation, Hillsboro, OR, USA. In 2012, he joined the faculty of the department of Electronic and Electrical Engineering at POSTECH, where he is currently working as an assistant professor. Dr. Kim received several honorable awards. In 2011, He received MIT EECS Jin- Au Kong Outstanding Doctoral Thesis Honorable Mentions, and IEEE 2009 Journal of Solid-State Circuits Best Paper Award. In 2009, he received Analog Device Inc. Outstanding Student Designer Award from MIT, and was also a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 IEEE Internal Solid- State Circuits Conference. Hong June Park received the B.S. degree from the Department of Electronic Engineering, Seoul National University, Seoul, Korea, in 1979, the M.S. degree from the Korea Advanced Institute of Science and Technology, Taejon, in 1981, and the Ph.D. degree from the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, in He was a CAD engineer with ETRI, Korea, from 1981 to 1984 and a Senior Engineer in the TCAD Department of INTEL from 1989 to In 1991, he joined the Faculty of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea, where he is currently Professor. His research interests include CMOS analog circuit design such as high-speed interface circuits, ROIC of touch sensors and analog/digital beamformer circuits for ultrasound medical imaging. Prof. Park is a member of IEEK. He served as the Editor-in-Chief of Journal of Semiconductor Technology and Science, an SCIE journal ( from 2009 to 2012, also as the Vice President of IEEK in 2012 and as the technical program committee member of ISSCC, SOVC and A-SSCC for several years. He received the Haedong Academics Award from IEEK in Jae-Yoon Sim received the B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea, in 1993, 1995, and 1999, respectively. From 1999 to 2005, he worked as a senior engineer at Samsung Electronics, Korea. From 2003 to 2005, he was a post-doctoral researcher with the University of Southern California, Los Angeles. From 2011 to 2012, he was a visiting scholar with the University of Michigan, Ann Arbor. In 2005, he joined POSTECH, where he is currently an Associate Professor. He has served in the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC), Symposium on VLSI Circuits, and Asian Solid- State Circuits Conference (ASSCC). He was a corecipient of the Takuo Sugano Award at ISSCC His research interests include high-speed serial/parallel links, PLLs, data converters and power module for plasma generation.

A Single-Stage 37 db-linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014 http://dx.doi.org/10.5573/jsts.2014.14.5.579 A Single-Stage 37 db-linear Digitally-Controlled Variable Gain Amplifier for Ultrasound