HIGH resolution time-to-digital converters (TDCs)

Transcription

1 3064 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010 A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method Nan Xing, Jong-Kwan Woo, Woo-Yeol Shin, Hyunjoong Lee, Student Member, IEEE, and Suhwan Kim, Senior Member, IEEE Abstract This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 m CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mw power. Index Terms Delay-locked loop (DLL), fractional conversion scheme, input range, resolution, time-to-digital converter (TDC), triggerable voltage controlled oscillator (TVCO). I. INTRODUCTION HIGH resolution time-to-digital converters (TDCs) have found many applications, including all-digital phase-locked loops (ADPLLs) [1], capacitive sensor readouts [2], large range finders [3], and on-chip time-signal measurement [4]. Various designs of time-to-digital converters have been proposed to meet the requirements of different applications. They can be generally classified into indirect and direct conversion schemes. Indirect conversion TDCs usually have a time-to-analog stage and an analog-to-digital stage. Ramp TDCs [5] and dual-slope TDCs [6] are of this type. In a dual-slope TDC circuit, one capacitor is discharged to a reference level by a run-down current, which is relatively large in the content of the time interval to be measured. The time to discharge the other capacitors to the same reference level is sampled by an external clock. One disadvantage of indirect conversion schemes is the extra error caused by the time-to-analog stage. During time-to-voltage conversion, the signal is distorted due to the nonlinearity of the capacitors and the leakage current. Another disadvantage of this type of Manuscript received April 12, 2010; revised June 29, 2010; accepted August 15, Date of publication October 07, 2010; date of current version December 15, This work was supported in part by the grant from the Industrial Source Technology Development Program ( , ) of the Ministry of Knowledge Economy (MKE) of Korea. This paper was recommended by Associate Editor S. Sezer. The authors are with the Department of Electrical Engineering, Seoul National University, Seoul, , Korea ( suhwan@snu.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSI Fig. 1. (a) Schematic and (b) timing diagrams of Vernier delay line. circuit is the low sampling rate, which presents a trade-off between resolution and conversion time. In direct TDC circuits, delay lines are usually used to measure the short interval between the rising edges of the START and STOP signals. The simplest arrangement is a tapped delay-line with one D flip-flop (DFF) connected to each tap. In this case the resolution is the propagation delay of a single delay buffer. Higher resolutions can be achieved using a Vernier delay line (VDL), as shown in Fig. 1. The propagation delay in the upper buffer chain is slightly larger than the propagation delay in the lower chain, and the resolution is the difference between these two delays. While Vernier delay lines are popular and straightforward to integrate into TDCs, they suffer from three major drawbacks: the resolution of a VDL itself is vulnerable to process, voltage, and temperature (PVT) variations; its dynamic range is limited by the number of delay stages; and the conversion rate is slow [7] /$ IEEE

2 XING et al.: A 14.6 ps RESOLUTION, 50 ns INPUT-RANGE CYCLIC TIME-TO-DIGITAL CONVERTER 3065 Some approaches have been proposed to achieve high resolution as well. One scheme is a coarse-fine TDC [8]; the fine part has a time amplifier which exploits the meta-stability of SR latches, and the resulting TDC can achieve a resolution as high as 1.25 ps. However, the gain of a time amplifier is very sensitive to PVT variations, making it unsuitable for sensor applications. Matthew et al. [9] proposed a TDC with an effective resolution of 1 ps. It employs a gated ring oscillator (GRO) and a first-order noise shaping technique. However, it requires repetition of the input signal, which is not available in many applications. Besides, the uncertainty of the skew in a GRO makes it difficult to compensate for PVT variation by using a PLL or DLL. The important performance metrics for a TDC are similar to those of an analog-to-digital converter, including resolution, conversion time, integral nonlinearity (INL), differential nonlinearity (DNL), gain error, and dynamic range [10]. While many previous efforts have been focused on high resolution, this is not the only target. In general, TDCs should be designed to suit their application. Sensor readout circuits achieve accurate output through high resolution and low INL/DNL. However, since accuracy can be undermined by even a small error in gain caused by ambience variation, environmental robustness is also required. Besides, due to the wide range of sensor output, large dynamic range is also desirable in such TDCs. In this paper, we propose a Vernier-based and DLL-stabilized high-resolution TDC for applications that require PVT compensation and wide dynamic range, such as readout integrated circuits. A novel fractional Vernier conversion scheme is used to stabilize delay and also to enhance resolution. The dynamic range of the TDC is increased by adopting the principles of the cyclic Vernier delay line (CVDL). The rest part of this paper is organized as follows. In Section II we review the previous work on PVT compensation and dynamic range improvement, including PLL/DLL compensation and CVDL. In Sections III and IV we describe the operating principles of the proposed TDC and its circuit implementation. Section V is devoted to the experimental results. Conclusions are drawn in Section VI, after comparing with other works. II. RELATED WORK A. PVT Compensation VDL can achieve sub-gate delay resolution but, as we have already described, its resolution is sensitive to PVT variations. One popular way to compensate for PVT variations is to use feedback in the DLL or PLL. In a conventional DLL-stabilized Vernier TDC [11], as depicted in Fig. 2, the DLL contains N stages and operates at a reference clock frequency of. In the locked mode, the total delay difference between two delay lines equals one reference clock cycle, thus the resolution of the VDL can then be expressed as Equation (1) shows that resolution of TDC is proportional to reference clock frequency and number of stages. Trade-off (1) Fig. 2. Schematic diagram of a DLL-stabilized Vernier TDC. Fig. 3. Schematic diagram of a dual-dll Vernier TDC. exists between resolution, power, and area. Higher resolution can be achieved by higher clock frequency or larger number of stages at the cost of increased power and area. In the dual DLL structure [12] shown in Fig. 3, a DLL with stage and another with stages are combined to stabilize the propagation delay of the upper and lower lines. The single-cell propagation delay in the upper line,, and in the lower line,, respectively can be expressed as follows: The resolution of the VDL is the difference between and Now the resolution is no longer limited by the reference clock frequency. Since the single-cell propagation delay for a particular technology is relative constant, the usual way to improve resolution is to add more stages to the DLL, at the cost of area and power. (2) (3) (4)

3 3066 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010 Fig. 4. (a) Schematic and (b) timing diagrams of a cyclic VDL. B. Extending the Dynamic Range Other problems with VDL are its slow conversion rate and limited dynamic range. For instance, a VDL with a resolution of 20 ps and a dynamic range of 20 ns has a maximum conversion time equivalent to 1000 gate delays, and it must have 1000 stages. This is expensive in terms of both area and power consumption. The above problems can be alleviated by adopting the principles of a cyclic VDL [13], which has the schematic and timing diagrams shown in Fig. 4. When the START signal arrives starts oscillating, and starts oscillating when the STOP signal arrives. samples at each cycle, and a phase coincidence is detected when the sampled value changes from 1 to 0. After a delay of more than one cycle, the end-of-conversion (EOC) signal is released to disable the counters. In theory, the dynamic range of a cyclic VDL is limited only by the number of bits in its counter. However, jitter in the VCO actually limits its dynamic range. III. PROPOSED TDC We have proposed a high-resolution TDC that incorporates a novel fractional difference conversion scheme and the principles of a cyclic Vernier delay line, as shown in Fig. 5. Two DLLs, DLL1 and DLL2, generate control voltages for two triggerable VCOs, TVCO1 and TVCO2. The outputs of these VCOs are forwarded to phase-coincidence detectors (PCDs) and other digital logic such as counters for readout. The DLLs are of different number of stages and operate at fractional frequencies. A. Fractional Difference Conversion The high resolution of our TDC is achieved by a fractional difference conversion scheme in which two DLLs with and stages operate at fractional frequencies, as shown in Fig. 6. Fig. 5. Block diagram of the proposed TDC. The delay cells in DLLs and triggerable VCOs share identical schematic and coupling capacitances are matched by careful layout, so that: and. The single-stage delay of the upper and lower delay lines can be expressed as follows: As will be explained later, the resolution of the VDL is the half of the difference between and By careful choice of,, and the numerator of the last of these fractions can be 1, then this expression for resolution reduces to (5) (6) (7) (8)

4 XING et al.: A 14.6 ps RESOLUTION, 50 ns INPUT-RANGE CYCLIC TIME-TO-DIGITAL CONVERTER 3067 Fig. 7. Block diagram of a modified cyclic VDL. Fig. 6. Fractional difference conversion scheme. To compare the performance of our proposed scheme with that of a dual-dll TDC, let us assume (9) (10) Since the resolution is relatively small, or even negligible, compared to the delay of a single stage, we constructively assume that the propagation delay of a single stage in any of the four DLLs are approximately the same, which allow us to write Combining (4), (8), (9), (10), and (11), we obtain (11) (12) Thus, we see that the resolution of the proposed TDC is at least times higher than that of a dual DLL TDC. In our design, and are chosen to be 4 and 5, respectively. Expressions can also be obtained for the switching power consumed by the delay-lines in each case (13) (14) where is the load capacitance of a single delay cell. Using the approximation represented by (11), the ratio between and can be shown to have the following relation: (15) Thus, we see that the delay lines in new TDC consume comparable power while achieving much higher resolution compared to dual-dll scheme. B. Modified Cyclic VDL Instead of sampling the signal only on rising edge, as shown in Fig. 7, two phase coincidence detectors (PCDs) work on both rising and falling edges of and. This dual-edge sampling doubles the resolution of the VDL. As shown in Fig. 8, TVCO1 starts oscillating when the rising edge of the START signal arrives, and TVCO2 is triggered by the rising edge of the STOP signal. is sampled by both the rising and falling edges of. A positive edge phase coincidence is detected when the sampled value of the rising edge changes from 1 to 0. A negative edge phase coincidence is similarly detected when the sampled value of the negative edge changes from 0 to 1. The EOC signal is not released immediately after the detection of a phase coincidence, but after a delay of. This delay is added to reduce meta-stability in the phase coincidence detector, as we will describe shortly in more details. The following inequalities can be obtained from the timing diagram: (16) (17) In an ideal case, with a 50% duty cycle and no jitters, a positive phase coincidence should be detected during the same cycle or one cycle later than negative phase coincidence, so that (18) If we let, then can obtain the readout value of from (16), (17), and (18) (19) Determining the resolution and dynamic range of a cyclic VDL is a little bit more complicated than it is for a conventional VDL. Equation (19) can be rewritten as (20) As we will explain in the next section, is a multiple of. Thus we can view the cyclic VDL as a coarse-fine conversion scheme. At the coarse level, its resolution is and output

5 3068 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010 Fig. 8. Timing of a modified cyclic VDL. equals. At the fine level, the resolution is and the output is. We use four 7-bit counters, and thus the maximum output of each counter is 127. reaches its maximum of when,, and. The dynamic range of our cyclic VDL is much greater than that of a conventional one. The conversion time approximately equals, which is comparable to for large input [13]. However, in the noncyclic VDL case, conversion time equals to, which is much larger than. C. Limits on Resolution and Dynamic Range Equation (12) suggests that choosing very large value of and allow us to achieve a very fine TDC resolution. Unfortunately, this is not actually the case. The resolution and dynamic range of the TDC are limited by oscillation jitter [14]. To discuss these limitations in more details, let us assume that each delay stage, either in the DLLs or the cyclic VDL, contributes equally to the total jitter of that DLL or VDL. So let us suppose that (21) Let us further assume that the jitter contributed by different delay stages is independent. The jitter of the DLL1 and DLL2 outputs can be expressed as follows: (22) (23) For a general case, TDC output jitter can then be expressed as follows: (24) The output jitter reaches a maximum when and reaches their maxima. The value of is limited by the number of counter bits n, while that of is limited by the ratio between the period of the slow clock and the resolution, which yields Thus, the maximum jitter can be expressed as follows: (25) (26) (27) It becomes clear that having too many stages in the DLLs or counters with too many bits produces large output error that eventually overwhelms the benefits of a higher resolution. IV. CIRCUIT IMPLEMENTATION A. Phase Coincidence Detector The above equations and inequalities are established for an ideal case. However, in reality nonidealities should be dealt with great effort. One problem is the meta-stability of the PCD. A conventional PCD mainly consists of three DFFs. is used to hold the value of sampled by. is used to delay by one clock cycle. One cycle after the phase of catches up with that of, toggles from 1 to 0 while equals 1 and EOC is released. However, if the rising edge of is too close to that of, then can suffer from a meta-stability problem, so that the phase coincidence is missed. To solve the above problem, a DFF,, is inserted between and, delaying by one additional cycle, and thus allowing more time for to reach a stable

6 XING et al.: A 14.6 ps RESOLUTION, 50 ns INPUT-RANGE CYCLIC TIME-TO-DIGITAL CONVERTER 3069 Fig. 9. PCD designed to both reduce meta-stability errors and suppress bubbles. Fig. 10. Timing of a PCD with bubble suppression. Fig. 12. Die photo of the TDC implemented in 0.18 m CMOS technology. Fig. 11. Schematic diagram of a TVCO. voltage level. This greatly reduces the probability of a metastability error [13]. Beside the meta-stability issue, another problem with the PCD circuit is bubbles. Ideally, a sequence of signal values at takes the form. It consists of alternating sections of continuous 1 and continuous 0. However, in the presence of oscillation jitter and other noises, one or more sections may be corrupted with an occasional 1 or 0, regarded as bubbles. Bubbles are highly undesirable, as they cause false detection. We have therefore proposed a new form of PCD, as shown in Fig. 9, to suppress bubble. The timing diagram shown in Fig. 10 shows that a phase coincidence is now detected only when 100 is found in the time sequence at. Thus, bubbles with length of 1 can be successfully eliminated. B. Triggerable VCO The TVCO consists of a starved inverter and a NAND gate, as shown in Fig. 11. Unlike a gated ring oscillator, in which oscillation starts from a random phase, oscillation starts from a certain phase. When TRIG is 0, output of NAND gate is 1, and oscillation is disabled. When TRIG is 1, NAND gate behaves as an inverter and the TVCO becomes effectively a three-stage VCO. V. EXPERIMENTAL RESULTS To demonstrate the effectiveness of the proposed TDC, a prototype chip is designed and fabricated in 0.18 m CMOS technology. Fig. 12 shows a micrograph of the chip. The core TDC occupies 0.33 mm area and consumes 6.4 mw at 2 M samples/s. Fractional clocks, 96.1 MHz and 76.9 MHz are provided to two DLLs, which have 9 and 11 stages, respectively. A ramp input is used to obtain the short-range output curve. A 1 MHz clock is provided to START signal and a 1 MHz clock with 125 Hz down-ramp phase-modulation is provided to STOP signal. Since the clock jitter can be as large as 70 ps, 25 measurement results were averaged to ensure the validity of the output [13]. Fig. 13 shows the short-range output curve with an input time interval between 1 ns and 2 ns. Code density test and FFT is performed to obtain the short-range DNL and INL [15]. Figs. 14 and 15 show the measured short-range DNL and INL. DNL is within 0.6 LSB and 0.7 LSB. INL is within 0.2 LSB and 0.8 LSB. The short-range DNL and INL are relatively large in the central region of the graph. This is because of the larger values of and. From (24), output jitter increases with and. To obtain the long-range output curve of the TDC [8], two clocks with slightly different periods, 1 and , are provided for START and STOP signals. The phase difference between the START and STOP signals changes gradually over time. Fig. 16 shows the long-range output characteristic curve of the proposed TDC. The proposed TDC achieves a resolution of 14.6 ps and a dynamic range of 50 ns is demonstrated. There is a small deviation from measured and theoretical resolution. The

7 3070 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010 Fig. 17. Measured long-range DNL. Fig. 13. Short-range output characteristic of the proposed TDC. Fig. 18. Measured long-range INL. Fig. 14. Measured short-range DNL. Fig. 15. Measured short-range INL. Fig. 19. Single-shot histograms of the proposed TDC for (a) time interval = 2nsand (b) time interval = 33 ns. Fig. 16. TDC output characteristics. deviation is mainly due to the layout mismatch between VCO and DLL delay cells. To obtain the long-range INL and DNL, a 1 MHz square clock is provided to START signal, while a 1 MHz clock signal with 125 Hz sinusoidal phase-modulation is provided to STOP signal. 100 measurement results were averaged for output. Figs. 17 and 18 show the measured long range DNL and INL. DNL is within 1 LSB and 1.2 LSB and INL is within 1.5 LSB. In order to see the noise contribution in the TDC [11], a single shot histogram of the proposed TDC is provided in Fig. 19. Two coupled clocks with fixed delays of 2 ns and 33 ns are provided to START and STOP signals outputs were measured for each input. Since jitter in START and STOP signals cancels each other in the coupled case, histograms test shows good noise performance. Standard deviations of the two histograms are 0.03 LSB and 0.04 LSB, respectively.

8 XING et al.: A 14.6 ps RESOLUTION, 50 ns INPUT-RANGE CYCLIC TIME-TO-DIGITAL CONVERTER 3071 TABLE I COMPARISON BETWEEN PROPOSED TDC AND OTHER DLL/PLL-STABILIZED TDCS VI. CONCLUSIONS We have proposed a high-resolution TDC which employs DLL stabilization and has an extended dynamic range. A novel fractional difference conversion scheme is used to achieve high resolution. A cyclic Vernier delay line is modified and adopted to extend dynamic range while improve the resolution. Instead of sampling on only rising edges, the new TDC samples on both the rising and falling edges of the triggerable VCOs output. Our TDC has been fabricated in 0.18 m CMOS technology. The core area of the TDC is 0.33 mm and consumes 6.4 mw. Its resolution can be as high as 14.6 ps, and the short-range DNL and INL are within 0.7 LSB and 0.8 LSB, respectively. The dynamic range of the TDC is up to 50 ns. Table I compares our TDC with other PLL or DLL stabilized Vernier delay-line counterparts. It is clear that our proposed TDC is competitive in terms of resolution, dynamic range and power consumption. ACKNOWLEDGMENT The authors gratefully acknowledge the support of the IC Design Education Center (IDEC), by the provision of CAD tools, and the support of the Inter-university Semiconductor Research Center (ISRC). REFERENCES [1] C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, A low-noise wide-bw 3.6-GHz digital 16 fractional-n frequency synthesizer with a noiseshaping time-to-digital converter and quantization noise cancellation, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp , Dec [2] P. Chen, C.-C. Chen, C.-C. Tsai, and W.-F. Lu, A time-to-digitalbased CMOS smart temperature sensor, IEEE J. Solid-State Circuits, vol. 40, no. 8, pp , Aug [3] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 3, pp , Mar [4] J.-C. Hsu and C. Su, BIST for measuring clock jitter of charge-pump phase-locked loops, IEEE Trans. Instrum. Meas., vol. 57, no. 2, pp , Feb [5] M.-J. Hsiao, J.-R. Huang, and T.-Y. Chang, A built-in parametric timing measurement unit, IEEE Des. Test Comput., vol. 21, no. 4, pp , Jul [6] P. Chen, C.-C. Chen, and Y.-S. Shen, A low-cost low power CMOS time-to-digital converter based on pulse stretching, IEEE Trans. Nucl. Sci., vol. 53, no. 4, pp , Aug [7] N. Xing, W.-Y. Shin, D.-K. Jeong, and S. Kim, High-resolution time-to-digital converter utilizing fractional difference conversion scheme, Electron. Lett., vol. 46, no. 6, pp , Mar [8] M. Lee and A. A. Abidi, A 9 b 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue, IEEE J. Solid-State Circuits, vol. 43, no. 4, pp , Apr [9] M. Z. Straayer and M. H. Perrott, A multi-path ring oscillator TDC with first-order noise shaping, IEEE J. Solid-State Circuits, vol. 44, no. 4, pp , Apr [10] P. Crippa, C. Turchetti, and M. Conti, A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 4, pp , Aug [11] P. Dudek, S. Szczepanski, and J. V. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line, IEEE J. Solid-State Circuits, vol. 35, no. 4, pp , Feb [12] C.-S. Hwang, P. Chen, and H.-W. Tsao, A high-precision time-todigital converter using a two-level conversion scheme, IEEE Trans. Nucl. Sci., vol. 51, no. 4, pp , Aug [13] P. Chen, C.-C. Chen, J.-C. Zheng, and Y.-S. Shen, A PVT insensitive Vernier-based time-to-digital converter with extended input range and high accuracy, IEEE Trans. Nucl. Sci., vol. 54, no. 2, pp , Apr [14] N. Xing, H. Song, D.-K. Jeong, and S. Kim, A PVT-insensitive time-to-digital conver using fractional difference vernier delay lines, in Proc. IEEE SOCC, Sep. 2009, pp [15] J. Doernberg, H.-S. Lee, and D. A. Hodges, Full-speed testing of A/D converters, IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp , Dec Nan Xing received the B.S. degree in electronic science and technology from Shanghai Jiao Tong University, Shanghai, China, in He is currently working toward the M.S. degree at Seoul National University, Seoul, Korea. His research interests are in high-frequency phase locked loops and high-resolution time-to-digital converters.

9 3072 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 12, DECEMBER 2010 Jong-Kwan Woo received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in Since 2004, he has been working toward the Ph.D. degree at the same university. His research interests include data converters and low-power analog CMOS circuits. Hyunjoong Lee (S 06) received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2005 and 2007, respectively. He is currently working toward the Ph.D. degree at Seoul National University. His research interests include sensor interface for MEMS and bio-applications, data converter, and analog techniques in CMOS circuits. Woo-Yeol Shin received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in He is currently working toward the Ph.D. degree in electrical engineering at Seoul National University. His research interests include highspeed I/O circuits and high-speed memory interfaces. Suhwan Kim (SM 07) received the B.S. and M.S. degrees in electrical engineering and computer science from Korea University, Seoul, in 1990 and 1992, respectively, and the Ph.D. degree in electrical engineering and computer science from the University of Michigan, Ann Arbor, in From 1993 to 1999, he was with LG Electronics, Seoul. From 2001 to 2004, he was a Research Staff Member in IBM T. J. Watson Research Center, Yorktown Heights, NY. In 2004, he joined Seoul National University, Seoul, where he is currently an Associate Professor of Electrical Engineering. His research interests encompass high-performance and low-power analog and mixed signal integrated circuits, digitally compensated analog circuits, and high-speed I/O circuits.