32 x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers

Transcription

1 9-; Rev ; 8/ EVALUATION KIT AVAILABLE x 6 Nonblocking Video Crosspoint Switch General Description The is a 6 highly integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) Insertion. This device operates from dual ±V to ±5V supplies or from a single +5V supply. Digital logic is supplied from an independent single +.7V to +5.5V supply. Individual outputs can be switched between an input video signal source and OSD information through an internal, dedicated fast : mux (4ns switching times) located before the output buffer. All inputs and outputs are buffered, with all outputs able to drive standard 75Ω reverse-terminated video loads. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPI -compatible, three-wire serial interface and initialized with a single update signal. The unique serial interface operates in two modes facilitating both fast updates and initialization. On power-up, all outputs are initialized in the disabled state to avoid output conflicts in large-array configurations. Superior flexibility, high integration, and space-saving packaging make this nonblocking switch matrix ideal for routing video signals in security and video-ondemand systems. The is available in a 44-pin TQFP package and specified over an extended -4 C to +85 C temperature range. The evaluation kit is available to speed designs. Applications Security Systems Video Routing Video-On-Demand Systems CAMERAS Typical Operating Circuit IN IN OUT MONITOR Features 6 Nonblocking Matrix with Buffered Inputs and Outputs Operates from a ±V, ±5V, or +5V Supply Fast Switching (4ns) : OSD Insertion Mux Each Output Individually Addressable Individually Programmable Output Buffer Gain (A V = +V/V or +V/V) High-Impedance Output Disable for Wired-OR Connections.dB Gain Flatness to MHz Minimum -6dB Crosstalk, -db Isolation at 6MHz.5%/. Differential Gain/Differential Phase Error Low 95mW Power Consumption (.8mW per point) Ordering Information PART TEMP RANGE PIN PACKAGE ECE -4 C to +85 C 44 TQFP Pin Configuration appears at end of data sheet. IN IN IN IN x 6 SWITCH MATRIX Functional Diagram OSDFILL OSDFILL OSDFILL5 : OSD MUX A V* A V* A V* A V* ENABLE/DISABLE OUT OUT OUT OUT5 OSD GENERATOR IN OSDFILL OSDKEY OSDFILL OSDKEY OSDFILL5 OSDKEY5 OUT OUT5 MONITOR MONITOR RESET DIN SCLK UPDATE CE POWER-ON RESET SERIAL INTERFACE THERMAL SHUTDOWN DISABLE ALL OUTPUTS A-A MODE DECODE LOGIC LATCHES MATRIX REGISTER BITS UPDATE REGISTER 6 BITS OSDKEY OSDKEY5 OSDKEY *A V = +V/V OR +V/V V CC V EE AGND V DD DGND DOUT AOUT SPI/QSPI are trademarks of Motorola, Inc. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 x 6 Nonblocking Video Crosspoint Switch ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (V CC - V EE )...+V Digital Supply Voltage (V DD - DGND)...+6V Analog Supplies to Analog Ground (V CC - AGND) and (AGND - V EE )... +6V Analog Ground to Digital Ground...-.V to +.V IN, OSDFILL Voltage Range... (V CC +.V) to (V EE -.V) OUT Short-Circuit Duration to AGND, V CC, or V EE...Indefinite SCLK, CE, UPDATE, MODE, A_, DIN, DOUT, RESET, AOUT, OSDKEY...(V DD +.V) to (DGND -.V) Current Into Any Analog Input Pin (IN_, OSDFILL_)...±5mA Current Into Any Analog Output Pin (OUT_)...±75mA Continuous Power Dissipation (T A = +7 C) 44-Pin TQFP (derate 8.6mW/ C above +7 C)...W Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)... + C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±5V (V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND =, V IN _=, V OSDFILL _ =, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Range V CC - V EE Guaranteed by PSRR test V Logic Supply Voltage Range V DD to DGND V (V EE +.5V) < V IN_ < (V CC -.5V), A V = +V/V, R L = 5Ω (V EE +.5V) < V IN_ < (V CC -.5V), A V = +V/V, R L = kω Gain (Note ) A V (V EE +.75V) < V IN_ < (V CC -.75V), A V = +V/V, R L = 5Ω V/V (V EE +.75V) < V IN_ < (V CC -.75V) A V = +V/V, R L = kω (V EE + V) < V IN_ < (V CC -.V), A V = +V/V, R L = kω Gain Matching R L = kω.5.5 (Channel to Channel) R L = 5Ω.5 % Temperature Coefficient of Gain TC AV ppm/ C R L = kω V E E + V C C -. A V = +V/V R L = 5Ω V E E +.5 V C C -.5 Input Voltage Range V IN _ V R L = kω V EE + V C C -. A V = +V/V R L = 5Ω V E E +.75 V C C -.75

3 x 6 Nonblocking Video Crosspoint Switch DC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±5V (continued) (V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND =, V IN _=, V OSDFILL _ =, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) Output Voltage Range PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R L = kω V EE + V C C -. V V OUT R L = 5Ω V E E +.5 V C C -.5 V Input Bias Current I B 4 µa Input Resistance R IN_ (V EE + V) < V IN_ < (V CC -.V) MΩ A V = +V/V ±5 ± Output Offset Voltage V OFFSET A V = +V/V ± ±4 mv Output Short-Circuit Current I SC Sinking or sourcing, R L = Ω ±4 ma Enabled Output Impedance Z OUT (V EE + V) < V IN_ < (V CC -.V). Ω Output Leakage Current, Disable Mode DC Power-Supply Rejection Ratio Quiescent Supply Current I OD (V EE + V) < V OUT_ < (V CC -.V).4 µa PSRR 4.5V < (V CC - V EE ) <.5V 6 7 db I CC R L = I EE R L = Outputs enabled, T A = +5 C 6 Outputs enabled 85 Outputs disabled 6 8 Outputs enabled, T A = +5 C 5 6 Outputs enabled 85 Outputs disabled 55 8 ma I DD 4 8

4 x 6 Nonblocking Video Crosspoint Switch DC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±V (V CC = +V, V EE = -V, V DD = +V, AGND = DGND =, V IN _ =, V OSDFILL _ =, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Range Logic Supply Voltage Range V CC - V EE Guaranteed by PSRR test V V DD to DGND V (V EE + V) < V IN_ < (V CC -.V), A V = +V/V, R L = 5Ω (V EE + V) < V IN_ < (V CC -.V), A V = +V/V, R L = kω Gain (Note ) A V (V EE + V) < V IN_ < (V CC -.V), A V = +V/V, R L = 5Ω V/V (V EE + V) < V IN_ < (V CC -.V) A V = +V/V, R L = kω Gain Matching R L = kω.5.5 (Channel to Channel) R L = 5Ω.5 % Temperature Coefficient of Gain TC AV ppm/ C Input Voltage Range V IN_ A V = +V/V A V = +V/V R L = kω V EE + R L = 5Ω V EE + R L = kω V EE + R L = 5Ω V EE + V CC -. V CC -. V CC -. V CC -. V R L = kω V EE + Output Voltage Range V OUT RL = 5Ω VEE + V CC -. V CC -. V Input Bias Current I B 4 µa Input Resistance R IN (V EE + V) < V IN_ < (V CC -.V) MΩ Output Offset Voltage A V = +V/V ±5 ± V OFFSET A V = +V/V ± ±4 mv 4

5 x 6 Nonblocking Video Crosspoint Switch DC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±V (continued) (V CC = +V, V EE = -V, V DD = +V, AGND = DGND =, V IN _ =, V OSDFILL _ =, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Short-Circuit Current I SC Sinking or sourcing, R L = Ω ±4 ma Enabled Output Impedance Z OUT (V EE + V) < V IN_ < (V CC -.V). Ω Output Leakage Current, Disable Mode DC Power-Supply Rejection Ratio Quiescent Supply Current I OD (V EE + V) < V OUT_ < (V CC -.V).4 µa PSRR 4.5V < (V CC - V EE ) <.5V 6 75 db I CC RL = Outputs enabled 95 Outputs disabled 5 I EE Outputs enabled 9 R L = Outputs disabled 45 I DD ma DC ELECTRICAL CHARACTERISTICS SINGLE SUPPLY +5V (V CC = +5V, V EE =, V DD = +5V, AGND = DGND =, V IN _ = V OSDFILL _ = +.75V, A V = +V/V, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Range Logic-Supply Voltage Range V CC Guaranteed by PSRR test V V DD to DGND Gain (Note ) A V (V EE + V) < V IN < (V CC -.V), A V = +V/V, R L = kω V (V EE + V) < V IN < (V CC -.5V), A V = +V/V, R L = 5Ω Gain Matching (Channel to R L = kω.5 Channel) R L = 5Ω.5 Temperature Coefficient of Gain TC AV Input Voltage Range V IN A V = +V/V Output Voltage Range V OUT A V = +V/V, R L = kω A V = +V/V, R L = 5Ω R L = kω R L = 5Ω V EE + V EE + V EE + V EE + V CC -. V CC -.5 V CC -. V CC -.5 V % ppm/ C V V 5

6 x 6 Nonblocking Video Crosspoint Switch DC ELECTRICAL CHARACTERISTICS SINGLE SUPPLY +5V (continued) (V CC = +5V, V EE =, V DD = +5V, AGND = DGND =, V IN _ = V OSDFILL _ = +.75V, A V = +V/V, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Bias Current I B 4 µa Input Resistance R IN V EE + V < V IN < V CC -.V MΩ Output Offset Voltage V OFFSET A V = +V/V ± ±4 mv Output Short-Circuit Current I SC Sinking or sourcing, R L = Ω ±5 ma Enabled Output Impedance Z OUT (V EE + V) < V IN < (V CC -.V). Ω Output Leakage Current, Disable Mode DC Power-Supply Rejection Ratio I OD (V EE + V) < V OUT _ < (V CC -.V).4 µa PSRR 4.5V < V CC - V EE < 5.5V 5 65 db Quiescent Supply Current Outputs enabled, T A = +5 C 85 I CC R L = Outputs disabled 5 Outputs enabled, T A = +5 C 8 I EE R L = Outputs disabled I DD 4 ma 6

7 x 6 Nonblocking Video Crosspoint Switch LOGIC-LEVEL CHARACTERISTICS (V CC - V EE) = +4.5V to +.5V, V DD = +.7V to +5.5V, AGND = DGND =, V IN _ = V OSDFILL _ =, R L = 5Ω to AGND, and T A = T MIN to T MAX, unless otherwise noted. Typical values are at TA = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V DD = +5.V Input Voltage High Level V IH V DD = +V Input Voltage Low Level Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Output Current High Level Output Current Low Level V DD = +5.V.8 V IL V DD = +V.6 I IH I IL V I > V V I < V Excluding RESET -. RESET - - Excluding RESET -. RESET - -5 I SOURCE = ma, V DD = +5V V OH I SOURCE = ma, V DD = +V.7.9 I SINK = ma, V DD = +5V.. V OL I SINK = ma, V DD = +V.. V DD = +5V, V O = +4.9V 4 I OH V DD = +V, V OUT = +.7V 8 V DD = +5V, V O = +.V 4 I OL V DD = +V, V O = +.V 8 V V µa µa V V ma ma AC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±5V (V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND =, V IN _ = V OSDFILL _ =, R L = 5Ω to AGND, and T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small-Signal -db Bandwidth Medium-Signal -db Bandwidth Large-Signal -db Bandwidth Small-Signal.dB Bandwidth Medium-Signal.dB Bandwidth Large-Signal.dB Bandwidth Slew Rate SR BW SS V OUT_ = mvp-p A V = +V/V 95 A V = +V/V 7 V A V = +V/V 9 BW OUT_ = MS mvp-p A V = +V/V 7 BW LS V OUT_ = Vp-p BW.dB-SS V OUT_ = mvp-p A V = +V/V 4 A V = +V/V 5 A V = +V/V 5 A V = +V/V 5 V A V = +V/V 5 BW OUT_ =.db-ms mvp-p A V = +V/V 5 BW.dB-LS V OUT_ = Vp-p V OUT_ = V step, A V = +V/V V OUT_ = V step, A V = +V/V A V = +V/V A V = +V/V 5 6 MHz MHz MHz MHz MHz MHz V/µs 7

8 x 6 Nonblocking Video Crosspoint Switch AC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±5V (continued) (V CC = +5V, V EE = -5V, V DD = +5V, AGND = DGND =, V IN _ = V OSDFILL _ =, R L = 5Ω to AGND, and T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V A V = +V/V 6 Settling Time t OUT_ = to V S.% step A V = +V/V 6 Switching Transient A V = +V/V 5 (Glitch) (Note ) A V = +V/V 5 ns mv AC Power-Supply f = khz 7 Rejection Ratio f = MHz 68 Differential Gain R L = kω. Error (Note 4) R L = 5Ω.5 Differential Phase R L = kω. Error (Note 4) R L = 5Ω. db % d eg r ees Crosstalk, All Hostile f = 6MHz -6 db Off-Isolation, Input-to-Output f = 6MHz - db Input Noise Voltage Density e n BW = 6MHz 7 µv RMS Input Capacitance C IN 5 pf Disabled Output Capacitance Capacitive Load at db Output Peaking Amplifier in disable mode pf pf Output Impedance Z OUT f = 6MHz Output enabled Output disabled 4k Ω AC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±V (V CC = +V, V EE = -V, V DD = +V, AGND = DGND =, V IN _= V OSDFILL _ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small-Signal V A V = +V/V 9 BW OUT_ = SS MHz -db Bandwidth mvp-p A V = +V/V 65 Medium-Signal -db Bandwidth Large-Signal -db Bandwidth Small-Signal.dB Bandwidth V A V = +V/V 9 BW OUT_ = MS mvp-p A V = +V/V 65 BW LS V OUT_ = Vp-p A V = +V/V A V = +V/V 5 V A V = +V/V 5 BW OUT_ =.db-ss mvp-p A V = +V/V 5 MHz MHz MHz Medium-Signal.dB Bandwidth V A V = +V/V 5 BW OUT_ =.db-ms mvp-p A V = +V/V 5 MHz Large-Signal.dB Bandwidth BW.dB-LS V OUT_ = Vp-p A V = +V/V A V = +V/V MHz 8

9 x 6 Nonblocking Video Crosspoint Switch AC ELECTRICAL CHARACTERISTICS DUAL SUPPLIES ±V (continued) (V CC = +V, V EE = -V, V DD = +V, AGND = DGND =, V IN _= V OSDFILL _ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Slew Rate SR V OUT_ = V step A V = +V/V V OUT_ = V step A V = +V/V Settling Time t S.% V O = to V step A V = +V/V 6 A V = +V/V 6 Switching Transient A V = +V/V 5 (Glitch) (Note ) A V = +V/V AC Power-Supply f = khz 6 Rejection Ratio f = MHz 4 Differential Gain Error R L = kω. (Note 4) R L = 5Ω. Differential Phase R L = kω.8 Error (Note 4) R L = 5Ω. Crosstalk, All Hostile f = 6MHz -6 db Off-Isolation, Input to Output f = 6MHz - db V/µs ns mv db % d eg r ees Input Noise Voltage Density e n BW = 6MHz 7 µv RMS Input Capacitance C IN_ 5 pf Disabled Output Capacitance Amplifier in disable mode pf Capacitive Load at db Output Peaking Output Impedance ZOUT f = Output enabled 6MHz Output disabled 4k pf Ω 9

10 x 6 Nonblocking Video Crosspoint Switch AC ELECTRICAL CHARACTERISTICS SINGLE SUPPLY +5V (V CC = +5V, V EE =, V DD = +5V, AGND = DGND =, V IN _ = V OSDFILL _ =.75V, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small-Signal -db Bandwidth Medium-Signal -db Bandwidth BW SS V OUT_ = mvp-p 9 MHz BW MS V OUT = mvp-p 9 MHz Large-Signal -db Bandwidth Small-Signal.dB Bandwidth Medium-Signal.dB Bandwidth Large-Signal.dB Bandwidth BW LS V OUT =.5Vp-p 8 MHz BW.dB-SS V OUT = mvp-p MHz BW.dB-MS V OUT_ = mvp-p MHz BW.dB-LS V OUT_ =.5Vp-p MHz Slew Rate SR V OUT_ = V step, A V = +V/V V/µs Settling Time t S.% V OUT _ = to V step 6 ns Switching Transient (Glitch) 5 mv AC Power-Supply f = khz 7 Rejection Ratio f = MHz 69 Differential Gain Error R L = kω. (Note 4) R L = 5Ω.5 Differential Phase R L = kω.6 Error (Note 4) R L = 5Ω. db % d eg r ees Crosstalk, All Hostile f = 6MHz -6 db Off-Isolation, Input-to- Output f = 6MHz - db Input Noise Voltage e n BW = 6MHz 7 µv RMS Input Capacitance C IN_ 5 pf Disabled Output Capacitance Capacitive Load at db Output Peaking Amplifier in disable mode pf pf Output Impedance Z OUT f = 6MHz Output enabled Output disabled 4k Ω

11 x 6 Nonblocking Video Crosspoint Switch SWITCHING CHARACTERISTICS ((V CC - V EE ) = +4.5V to +.5V, V DD = +.7V to +5.5V, DGND = AGND =, V IN _ = V OSDFILL _ = for dual supplies, V IN _ = V OSDFILL _ = +.75V for single supply, R L = 5Ω to AGND, CL = pf, A V = +V/V, and T A = T MIN - T MAX, unless otherwise noted. Typical values are at T A = +5 C. ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay: UPDATE to Video Out t PdUdVo V IN =.5V step 45 ns Delay: UPDATE to AOUT t PdUdAo MODE =, time to AOUT = low after UPDATE = low Delay: OSDKEY_ to Output t PdOkVo/ t PdOfVo V OUT =.5V step V DD = +5V 4 V DD = +V 6 ns Logic state change in DOUT on active Delay: SCLK to DOUT Valid t PdDo ns SCLK edge Delay: Output Disable t PdHOeVo V OUT =.5V, kω pulldown to AGND 8 ns Output disabled, kω pulldown to AGND, Delay: Output Enable t PdLOeVo 8 ns V IN =.5V Setup: CE to SCLK t SuCe ns Setup: DIN to SCLK t SuDi ns Hold Time: SCLK to DIN t HdDi ns Minimum High Time: SCLK t MnHCk ns Minimum Low Time: SCLK t MnLCk ns Minimum Low Time: UPDATE t MnLUd ns Setup Time: UPDATE to SCLK t SuHUd Rising edge of UPDATE to falling edge of SCLK Hold Time: SCLK to UPDATE t HdHUd Falling edge of SCLK to falling edge of UPDATE Setup Time: MODE to SCLK t SuMd Minimum time from clock edge to MODE with valid data clocking ns ns ns ns Minimum time from clock edge to MODE Hold Time: MODE to SCLK t HdMd ns with valid data clocking Minimum Low Time: RESET t MnLRst ns Delay: RESET t PdRst kω pulldown to AGND 6 ns Note : Associated output voltage may be determined by multiplying the input voltage by the specified gain (A V ) and adding output offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths. Note : Logic level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A A, MODE, AOUT, and OSDKEY_. Note : Switching transient settling time is guaranteed by the settling time (t S ) specification. Switching transient is a result of updating the switch matrix. Note 4: Input test signal:.58mhz sine wave of amplitude 4IRE superimposed on a linear ramp ( to IRE). IRE is a unit of video-signal amplitude developed by the International Radio Engineers: 4IRE =.V. Note 5: All devices are % production tested at +5 C. Specifications over temperature limits are guaranteed by design.

12 x 6 Nonblocking Video Crosspoint Switch SYMBOL TYPE DESCRIPTION Ao Symbol Definitions Signal Address Valid Flag (AOUT) Ce Signal Clock Enable (CE) Ck Signal Clock (SCLK) Di Signal Serial Data In (DIN) Do Signal Serial Data Output (DOUT) Md Signal MODE Oe Signal Output enable Rst Signal Reset Input (RESET) Ud Signal UPDATE Vo Signal Video Out (OUT) H Property High- or Low-to-High transition Hd Property Hold L Property Low- or High-to-Low transition Mn Property Minimum Mx Property Maximum Pd Property Propagation delay Su Property Setup Tr Property Transition W Property Width Naming Conventions: All parameters with time units are given t designation, with appropriate subscript modifiers. Propagation delays for clocked signals are from active edge of clock. Propagation delay for level sensitive signals is from input to output at 5% point of a transition. Setup and Hold times are measured from 5% point of signal transition to 5% point of clocking signal transition. Setup time refers to any signal that must be stable before active clock edge, even if signal is not latched or clocked itself. Hold time refers to any signal that must be stable during and after active clock edge, even if signal is not latched or clocked. Propagation delays to unobservable internal signals are modified to setup and hold designations applied to observable IO signals.

13 x 6 Nonblocking Video Crosspoint Switch Ce: CE Ck: SCLK Di: DIN Do: DOUT Ud: UPDATE Vo: OUT_ t MnHCk DATA AND CONTROL TIMING t SuCe t MnLCk t SuDi t HdDi t PdDo t HdUd t MnLUd t SuUd Hi-Z t PdUdVo t WTrVo t HdCe Hi-Z Timing Diagram TIMING PARAMETER DEFINITIONS NAME DESCRIPTION t HdDi Hold Time: Clock to Data In t MnHCk Min High Time: Clk t MnLCk Min Low Time: Clk t MnLUd Min Low Time: Update t SuHUd Setup Time: UPDATE to Clk with UPDATE High Not Valid Setup Time: UPDATE to Clk with UPDATE Low t HdHUd Hold Time: Clk to UPDATE with UPDATE high Not Valid Hold Time: Clk to UPDATE with UPDATE Low t PdDiDo Asynchronous Delay: Data In to Data Out t MnMd Min Low Time: MODE t MxTr Max Rise Time: Clk, Update t MnLRst Min Low Time: Reset t PdRstVo Delay: Reset to Video Output Ao: AOUT Rst: RESET t PdHOeVo Oe: OUTPUT ENABLE IN_ t PdLOeVo t PdUdAo OSD: KEY AND FILL TIMING t PdRstVo t MulRst VIDEO SOURCE (SELECTED ) TIMING PARAMETER DEFINITIONS NAME DESCRIPTION t PdUdVo Delay: Update to Video Out t PdUdAo Delay: UPDATE to Aout t PdOkVo Delay: OSD Key to Video Output t PdOfVo Delay: OSD Fill to Video Output t PdDo Delay: Clk to Data Out t PdHOeVo Delay: Output Enable to Video Output (High: Disable) t PdLOeVo Delay: Output Enable to Video Output (Low: Enable) t SuCe Setup: Clock Enable to Clock t SuDi Setup Time: Data In to Clock Of: OSDFILLi Ok: OSDKEYi OUTi t PdHOkVo VIDEO OUTPUT (WITH SUPERIMPOSED OSD) t PdLOkVo t PdLOfVo Figure. Timing Diagram

14 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±5V (V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) LARGE-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V -7. A V = +V/V toc MEDIUM-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V -7. A V = +V/V toc SMALL-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V -7. A V = +V/V toc LARGE-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V -7. A V = +V/V toc4 MEDIUM-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V -7. A V = +V/V toc SMALL-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V -7. A V = +V/V toc LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY A V = +V/V toc LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY R L = kω A V = +V/V A V = +V/V toc8 LARGE-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf 4 C L = 5pF C L = 45pF toc A V = +V/V

15 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±5V (continued) (V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) LARGE-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 5pF 7. C L = 45pF toc MEDIUM-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = 45pF C L = pf C L = 5pF -. toc MEDIUM-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 45pF C L = 5pF -. toc CROSSTALK (db) CROSSTALK vs. FREQUENCY A V = +V/V -. toc CROSSTALK (db) A V = +V/V CROSSTALK vs. FREQUENCY -9. toc4 DISTORTION (dbc) A V = +V/V DISTORTION vs. FREQUENCY ND HARMONIC ND HARMONIC -. toc5 DISTORTION (dbc) A V = +V/V DISTORTION vs. FREQUENCY ND HARMONIC -. ND HARMONIC toc6 OUTPUT IMPEDANCE (Ω) ENABLED-OUTPUT IMPEDANCE vs. FREQUENCY.. toc7 OUTPUT IMPEDANCE (Ω) M k k k DISABLED OUTPUT IMPEDANCE vs. FREQUENCY. toc8 5

16 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±5V (continued) (V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) OFF ISOLATION (db) OFF ISOLATION vs. FREQUENCY toc9 PSRR (db) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY toc VOLTAGE NOISE (nv Hz) VOLTAGE NOISE vs. FREQUENCY toc - k M M M FREQUENCY (Hz) G -75 k k M M M FREQUENCY (Hz) k k k M M FREQUENCY (Hz) LARGE-SIGNAL PULSE RESPONSE (A V = +V/V) toc LARGE-SIGNAL PULSE RESPONSE (A V = +V/V) toc MEDIUM-SIGNAL PULSE RESPONSE (A V = +V/V) toc4 V/div 5mV/div mv/div OUTPUT V/div OUTPUT V/div OUTPUT mv/div ns/div ns/div ns/div MEDIUM-SIGNAL PULSE RESPONSE (A V = +V/V) toc5 SWITCHING TIME (A V = +V/V) toc6 SWITCHING TIME (A V = +V/V) toc7 5mV/div V UPDATE 5V/div V UPDATE 5V/div OUTPUT mv/div V OUT 5mV/div V OUT V/div ns/div ns/div ns/div 6

17 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±5V (continued) (V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) V UPDATE 5V/div SWITCHING TRANSIENT (GLITCH) (A V = +V/V) toc8 V UPDATE 5V/div SWITCHING TRANSIENT (GLITCH) (A V = +V/V) toc9 5 OFFSET VOLTAGE DISTRIBUTION toc 5 V OUT 5mV/div V OUT 5mV/div 5 DIFF PHASE ( ) DIFF GAIN (%) ns/div DIFFERENTIAL GAIN AND PHASE vs. DC VOLTAGE (R L = 5Ω) IRE LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc4 toc DIFF PHASE ( ) DIFF GAIN (%) ns/div DIFFERENTIAL GAIN AND PHASE vs. DC VOLTAGE (R L = kω) IRE MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc5 toc V/div OUTPUT V/div OFFSET VOLTAGE (mv) LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc ns/div MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc6 5mV/div mv/div 5mV/div OUTPUT V/div OUTPUT mv/div OUTPUT mv/div ns/div ns/div ns/div 7

18 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±5V (continued) (V CC = +5V and V EE = -5V, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) GAIN vs. TEMPERATURE A V = +V/V A V = +V/V TEMPERATURE ( C) toc7 RESET DELAY (s) m m m µ µ µ n n RESET DELAY vs. C RESET p p p n n n µ µ µ C RESET (F) toc8 V OSDKEY 5V/div V OUT 5mV/div OSD SWITCHING TRANSIENT (IRE LEVEL SWITCH) (A V = +V/V) toc9 5ns/div IRE IRE V OSDKEY 5V/div V OUT 5mV/div OSD SWITCHING.58MHz SIGNAL (A V = +V/V) toc4 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE I CC I EE toc4 I DD 5ns/div TEMPERATURE ( C) 8

19 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±V (V CC = +V and V EE = -V, V DD = +V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) LARGE-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V A V = +V/V. toc MEDIUM-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V A V = +V/V. toc SMALL-SIGNAL FREQUENCY RESPONSE R L = 5Ω A V = +V/V A V = +V/V. toc LARGE-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V A V = +V/V toc MEDIUM-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V A V = +V/V toc SMALL-SIGNAL FREQUENCY RESPONSE R L = kω A V = +V/V A V = +V/V toc LARGE-SIGNAL GAIN FLATNESS VS. FREQUENCY toc LARGE-SIGNAL GAIN FLATNESS VS. FREQUENCY R L = kω A V = +V/V toc49 LARGE-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 45pF toc A V = +V/V A V = +V/V A V = +V/V C L = 5pF

20 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±V (continued) (V CC = +V and V EE = -V, V DD = +V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) LARGE-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 5pF C L = 45pF. toc MEDIUM-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 5pF C L = 45pF. toc MEDIUM-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 45pF C L = 5pF. toc5 CROSSTALK (db) CROSSTALK VS. FREQUENCY -4 A V = + V/V k M M M G FREQUENCY (Hz) toc54 CROSSTALK (db) CROSSTALK VS. FREQUENCY - A V = + V/V k M M M G FREQUENCY (Hz) toc55 DISTORTION (db) DISTORTION VS. FREQUENCY A V = + V/V - - ND HARMONIC RD HARMONIC k M M FREQUENCY (Hz) toc56 M DISTORTION (db) DISTORTION VS. FREQUENCY A V = + V/V ND HARMONIC RD HARMONIC toc57 OUTPUT IMPEDANCE (Ω) ENABLED OUTPUT IMPEDANCE VS. FREQUENCY toc58 OUTPUT IMPEDANCE (Ω) M k k k DISABLED OUTPUT IMPEDANCE VS. FREQUENCY toc59 - k M M FREQUENCY (Hz) M...

21 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±V (continued) (V CC = +V and V EE = -V, V DD = +V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) OFF ISOLATION (db) OFF ISOLATION VS. FREQUENCY toc6 PSRR (db) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY toc6 VOLTAGE NOISE (nv/ Hz) VOLTAGE NOISE vs. FREQUENCY toc6 - k M M M FREQUENCY (Hz) G -75 k k M M M FREQUENCY (Hz) k k k M M FREQUENCY(Hz) LARGE-SIGNAL PULSE RESPONSE (A V = +V/V) LARGE-SIGNAL PULSE RESPONSE (A V = +V/V) MEDIUM-SIGNAL PULSE RESPONSE (A V = +V/V) V/div toc6 5mV/div toc64 mv/div toc65 OUTPUT V/div OUTPUT V/div OUTPUT mv/div ns/div ns/div ns/div MEDIUM-SIGNAL PULSE RESPONSE (A V = +V/V) SWITCHING TIME (A V = +V/V) SWITCHING TIME (A V = +V/V) MAX456 toc68 5mV/div toc66 V UPDATE V/div toc67 V UPDATE V/div OUTPUT mv/div V OUT 5mV/div V OUT V/div ns/div ns/div ns/div

22 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±V (continued) (V CC = +V and V EE = -V, V DD = +V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) V UPDATE V/div SWITCHING TRANSIENT GLITCH (A V = +V/V) toc69 V UPDATE V/div SWITCHING TRANSIENT GLITCH (A V = +V/V) toc7 5 OFFSET VOLTAGE DISTRIBUTION toc7 5 V OUT 5mV/div V OUT 5mV/div 5 ns/div ns/div OFFSET VOLTAGE (mv) DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN AND PHASE (R L = 5Ω) toc7 DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN AND PHASE (R L = kω) toc7 V/div LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc74 DIFFERENTIAL PHASE ( ) IRE DIFFERENTIAL PHASE ( ) IRE OUTPUT V/div LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc75 MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc76 ns/div MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf, A V = +V/V) toc77 5mV/div mv/div 5mV/div OUTPUT V/div OUTPUT mv/div OUTPUT mv/div ns/div ns/div ns/div

23 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Dual Supplies ±V (continued) (V CC = +V and V EE = -V, V DD = +V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) GAIN VS. TEMPERATURE A V = +V/V A V = +V/V TEMPERATURE ( C) MAX456 toc78 RESET DELAY (s) m m m µ µ µ n n RESET DELAY vs. C RESET p p p n n n µ µ µ C RESET (F) MAX456 toc79 V OSDKEY V/div V OUT 5mV/div OSD SWITCHING TRANSIENT (IRE LEVEL SWITCH) 5ns/div A V = +V/V toc8 IRE IRE OSD SWITCHING.58MHz SIGNAL V OSDKEY V/div A V = +V/V toc8 V OUT 5mV/div 5ns/div

24 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Single Supply +5V (V CC = +5V and V EE =, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) R L = 5Ω LARGE-SIGNAL FREQUENCY RESPONSE. toc MEDIUM-SIGNAL FREQUENCY RESPONSE R L = 5Ω. toc SMALL-SIGNAL FREQUENCY RESPONSE R L = 5Ω. toc84 R L = kω LARGE-SIGNAL FREQUENCY RESPONSE toc85 MEDIUM-SIGNAL FREQUENCY RESPONSE R L = kω toc86 R L = kω SMALL-SIGNAL FREQUENCY RESPONSE toc LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY toc LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY R L = kω toc LARGE-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 5pF C L = 45pF toc

25 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Single Supply +5V (continued) (V CC = +5V and V EE =, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) MEDIUM-SIGNAL FREQUENCY RESPONSE (A V = +V/V) C L = pf C L = 5pF. C L = 45pF toc9 CROSSTALK (db) CROSSTALK vs. FREQUENCY k M M M G FREQUENCY (Hz) toc9 DISTORTION (dbc) k DISTORTION vs. FREQUENCY M nd HARMONIC M FREQUENCY (Hz) rd HARMONIC toc9 M OUTPUT IMPEDANCE (Ω) ENABLED OUTPUT IMPEDANCE vs. FREQUENCY toc94 OUTPUT IMPEDANCE (Ω) M k k k DISABLED OUTPUT IMPEDANCE vs. FREQUENCY toc95 OFF ISOLATION (db) OFF ISOLATION vs. FREQUENCY toc k M M M FREQUENCY (Hz) G PSRR (db) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY toc97 VOLTAGE NOISE (NV/ Hz) VOLTAGE NOISE vs. FREQUENCY toc98 V/div OUTPUT V/div LARGE-SIGNAL PULSE RESPONSE toc99-75 k k M M M FREQUENCY (Hz) k k k M M FREQUENCY (Hz) ns/div 5

26 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Single Supply +5V (continued) (V CC = +5V and V EE =, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) mv/div MEDIUM-SIGNAL PULSE RESPONSE toc V UPDATE 5V/div SWITCHING TIME toc OUTPUT mv/div V OUT 5mV/div ns/div ns/div V UPDATE 5V/div SWITCHING TRANSIENT (GLITCH) toc 5 OFFSET VOLTAGE HISTOGRAM toc 5 V OUT 5mV/div 5 ns/div OFFSET VOLTAGE (mv).5. DIFFERENTIAL.5 GAIN (%) DIFFERENTIAL GAIN AND PHASE (R L = 5Ω) toc4.4 DIFFERENTIAL. GAIN (%).. -. DIFFERENTIAL GAIN AND PHASE (R L = kω) toc5..5. DIFFERENTIAL.5 PHASE (%) IRE..8.6 DIFFERENTIAL.4 PHASE (%) IRE 6

27 x 6 Nonblocking Video Crosspoint Switch Typical Operating Characteristics Single Supply +5V (continued) (V CC = +5V and V EE =, V DD = +5V, AGND = DGND =, V IN_ =, R L = 5Ω to AGND, A V = +V/V, and T A = +5 C, unless otherwise noted.) V/div LARGE-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf) toc6 mv/div MEDIUM-SIGNAL PULSE RESPONSE WITH CAPACITIVE LOAD (C L = pf) toc7 V/div OUTPUT mv/div ns/div ns/div GAIN vs. TEMPERATURE TEMPERATURE ( C) toc8 RESET DELAY (s) m m m µ µ µ n n RESET DELAY vs. C RESET p p p n n n µ µ µ C RESET (F) toc9 OSD SWITCHING TRANSIENT (IRE LEVEL SWITCH) toc OSD SWITCHING.58MHz SIGNAL toc V OSDKEY 5V/div V OSDKEY 5V/div IRE V OUT 5mV/div IRE V OUT 5mV/div 5ns/div 5ns/div 7

28 x 6 Nonblocking Video Crosspoint Switch PIN NAME FUNCTION,, 5, 7, 9,,, 5, 7, 9,,, 5, 7, 9,,, 5, 7, 9, 4, 4, 45, 7, 9,,, 5, 7, 9, 4, 4, 4, 6, 8,,, 4, 6, 8,,, 4, 6, 8,,, 4, 7, 7, 7, 8, 9, 6, 8,,, 4, 6, 8, 4, 4 IN IN AGND Buffered Analog Inputs Analog Ground Pin Description 6, 74, 78, 8, 86, 9, 94, 98,, 6 V CC Positive Analog Supply. Bypass each pin with a.µf capacitor to AGND. Connect a single µf capacitor from one V CC pin to AGND. 8, 4, 4, 44 A A Address Programming Inputs. Connect to DGND or V DD to select the address for individual output address mode. See Table DGND Digital Ground 47 AOUT Address Recognition Output. AOUT drives low after successful chip address recognition. 48 MODE Serial Interface Mode Select Input. Drive high for Complete Matrix Mode (Mode ), or drive low for Individual Output Address Mode (Mode ). 49 DIN Serial Data Input. Data is clocked-in on the falling edge of SCLK. 5 SCLK Serial Clock Input 5 UPDATE Update Input. Drive UPDATE low to transfer data from Mode Registers to the switch matrix. 5 RESET Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All analog outputs are disabled. Additional power-on reset delay may be set by connecting a small capacitor from RESET to DGND. 5 CE Clock Enable Input. Drive low to enable the serial data interface. 54 DOUT Serial Data Output. In Complete Matrix Mode, data is clocked through the - bit Matrix Control shift register. In Individual Output Address Mode, data at DIN passes directly to DOUT OSDKEY OSDKEY5 Digital Control Input. Control for the fast : OSD Insertion multiplexer routing signal to output buffers. A logic high routes programmed IN_ analog input signal to output buffer. A logic low routes the dedicated OSDFILL_ input to corresponding output buffer. 7 V DD Digital Logic Supply. Bypass V DD with a.µf capacitor to DGND. 75, 77, 79, 8, 8, 85, 87, 89, 9, 9, 95, 97, 99,,, 5 OUT OUT5 Buffered Analog Outputs. Gain is individually programmable for A V = +V/V or A V = +V/V via the serial interface. Outputs may be individually disabled (high impedance). On power-up, or assertion of RESET, all outputs are disabled. 76, 8, 84, 88, 9, 96,, 4, 44,,,, 4, 5, 6, 7, 8, 9,,,,, 4, 5 V EE OSDFILL5 OSDFILL Negative Analog Supply. Bypass each pin with a.µf capacitor to AGND. Connect a single µf capacitor from one V EE pin to AGND. Dedicated OSD Analog Signal Buffered Inputs. For each output buffer amplifier. OSDFILL i input signal is routed to output buffer amplifier OUT i when the corresponding OSDKEY i is low. 8

29 x 6 Nonblocking Video Crosspoint Switch IN OSDFILL OSDFILL OSDFILL5 A V * Functional Diagram OUT IN IN x 6 SWITCH MATRIX : OSD MUX A V * A V * ENABLE/DISABLE OUT OUT IN A V * OUT5 RESET DIN SCLK UPDATE CE POWER-ON RESET SERIAL INTERFACE THERMAL SHUTDOWN DISABLE ALL OUTPUTS DECODE LOGIC LATCHES MATRIX REGISTER BITS UPDATE REGISTER 6 BITS V CC V EE AGND V DD DGND DOUT AOUT *A V = +V/V OR +V/V A-A MODE OSDKEY OSDKEY5 OSDKEY Detailed Description The is a highly integrated 6 nonblocking video crosspoint switch matrix. All inputs and outputs are buffered, with all outputs able to drive standard 75Ω reverse-terminated video loads. A three-wire interface programs the switch matrix and initializes with a single update signal. The unique serial interface operates in one of two modes, Complete Matrix Mode (Mode ) or Individual Output Address Mode (Mode ). The signal path of the is from the buffered inputs (IN IN), through the switching matrix, buffered by the output amplifiers, and presented at the outputs (OUT OUT5) (Functional Diagram). The other functional blocks are the serial interface and control logic. Each of the functional blocks is described in detail below. Analog Outputs The outputs are high-speed amplifiers capable of driving 5Ω (75Ω back-terminated) loads. The gain, A V = +V/V or +V/V, is selectable via programming bit 5 of the serial control word. Amplifier compensation is automatically optimized to maximize the bandwidth for each gain selection. Each output can be individually enabled and disabled via bit 6 of the serial control word. When disabled, the output is high impedance presenting typically 4kΩ load, and pf output capacitance, allowing multiple outputs to be connected together for building large arrays. On power-up (or asynchronous RESET) all outputs are initialized in the disabled state to avoid output conflicts in large array configurations. The programming and operation of the is output referred. Outputs are configured individually to connect to any one of the analog inputs, programmed to the desired gain (A V = +V/V or +V/V), and enabled or disabled in a high-impedance state. 9

30 x 6 Nonblocking Video Crosspoint Switch Table. Operation Truth Table CE UPDATE SCLK DIN DOUT MODE AOUT RESET OPERATION/COMMENTS X X X X X X No change in logic D i D i- Data at DIN is clocked on negative edge of SCLK into - bit Complete Matrix Mode register. DOUT supplies original data in SCLK pulses later. X X X D i D i Data in serial -bit Complete Matrix Mode register is transferred into parallel latches which control the switching matrix. Data at DIN is routed to Individual Output Address Mode shift register. DIN is also connected directly to DOUT so that all devices on the serial bus may be addressed in parallel. X D i D i 4-bit chip address A A is compared to D4 D. If equal, remaining bits in Individual Output Address Mode Register are decoded, allowing reprogramming for a single output. AOUT signals successful individual matrix update. X X X X X X X Asynchronous reset. All outputs are disabled. Other logic remains unchanged. Note: "X" = Don t Care Analog Inputs The offers analog input channels. Each input is buffered before the crosspoint matrix switch, allowing one input to cross-connect up to 6 outputs. The input buffers are voltage feedback amplifiers with high-input impedance and low input bias current. This allows the use of very simple input clamp circuits. OSDFILL and OSDKEY Inputs Intended for on-screen display insertion, the 6 OSD- FILL inputs are buffered analog signal inputs that are routed to a dedicated output buffer through a fast : MUX. The signal presented to the output buffer is selected from the programmed analog input signal (IN_) and the dedicated OSDFILL input signal. Switch Matrix The has 5 individual T-switches making a 6 switch matrix. The switching matrix is % nonblocking, which means that any input may be routed to any output. The switch matrix programming is output-referred. Each output may be connected to any one of the analog inputs. Any one input can be routed to all 6 outputs with no signal degradation. Digital Interface The digital interface consists of the following pins: DIN, DOUT, SCLK, AOUT, UPDATE, CE, A A, MODE, and RESET. DIN is the serial-data input, DOUT is the serialdata output.

31 x 6 Nonblocking Video Crosspoint Switch SCLK CE MODE A A CHIP ADDRESS 6-BIT INDIVIDUAL OUTPUT ADDRESS MODE REGISTER 4 4 MODE DIN SCLK CE MODE -BIT COMPLETE MATRIX MODE REGISTER S A DATA ROUTING GATE B DOUT MODE OUTPUT ADDRESS DECODE 7 MODE AOUT UPDATE 7 EN -BIT PARALLEL LATCH SWITCH DECODE 5 6 SWITCH MATRIX OUTPUT ENABLE Figure. Serial Interface Block Diagram SCLK is the serial-data clock which clocks data into the data input registers (Figure ). Data at DIN is loaded in at each falling edge of SCLK. DOUT is the data shifted out of the -bit Complete Matrix Mode register (Mode = ). DIN passes directly to DOUT when in Individual Output Address Mode (Mode = ). The falling edge of UPDATE latches the data and programs the matrix. When using Individual Output Address Mode, the address recognition output AOUT drives low when control-word bits D4 to D match the address programming inputs (A A) and UPDATE is low (Table ). Table is the operation truth table. Programming the Matrix The offers two programming modes: Individual Output Address Mode and Complete Matrix Mode. These two distinct programming modes are selected by toggling a single MODE pin high or low. Both modes operate with the same physical board layout. This flexibility allows initial programming of the IC by daisy-chaining and sending one long data word while still being able to immediately address and update individual outputs in the matrix. Individual Output Address Mode (MODE = ) Drive MODE to logic low to select Mode. Individual outputs are programmed via the serial interface with a single 6-bit control word. The control word consists of a don t care MSB, the chip address bits, output address bits, an output enable/disable bit, an output gain-set bit, and input address bits (Table through Table 6, and Figure ).

32 x 6 Nonblocking Video Crosspoint Switch Table. 6-Bit Serial Control Word Bit Assignments (Mode : Individual Output Address Mode) BIT NAME FUNCTION 5 (MSB) X Don t Care 4 IC Address A MSB of selected chip address IC Address A IC Address A IC Address A LSB of selected chip address Output Address B MSB of output buffer address 9 Output Address B 8 Output Address B 7 Output Address B LSB of output buffer address 6 Output Enable Enable bit for output, = disable, = enable. 5 Gain Set Gain Select for output buffer, = gain of +V/V, = gain of +V/V. 4 Input Address 4 MSB of input channel select address Input Address Input Address Input Address (LSB) Input Address LSB of input channel select address In Mode, data at DIN passes directly to DOUT through the data routing gate (Figure ). In this configuration, the 6-bit control word is simultaneously sent to all chips in an array of up to 6 addresses. Complete Matrix Mode (MODE = ) Drive MODE to logic high to select Mode. A single -bit control word, consisting of sixteen 7-bit control words, programs all outputs. The -bit control word s first 7-bit control word (MSBs) programs output 5, and the last 7-bit control word (LSBs) programs output (Table 7 and Figures 4 and 5). Data clocked into the -bit complete matrix mode register is latched on the falling edge of UPDATE, and the outputs are immediately updated. Initialization String Complete Matrix Mode (Mode = ) is convenient for programming the matrix at power-up. In a large matrix consisting of many s, all the devices can be programmed by sending a single bit stream equal to n x bits where n is the number of devices on the bus. The first -bit data word programs the last in-line (see Matrix Programming under the Applications Information section). On-Screen-Display (OSD) Fast MUX The features an asynchronous dedicated : Mux for each output buffer amplifier. Fast 4ns switching times enable pixel switching for on-screen-display (OSD) information such as text or other picture-in-picture signals (Figure ). OSDFILL_ inputs are buffered analog inputs connected to each dedicated OSD Mux. Drive the dedicated OSDKEY_ digital input to switch between the programmed IN_ input from the crosspoint switch matrix and the OSDFILL_. A logic low on OSDKEYi routes the analog signal at OSDFILLi to the OUTi output buffer. OSDKEY_ control does not affect the crosspoint switch matrix programming or the output-buffer enable/disable or gain-set programming. RESET The features an asynchronous bidirectional RESET with an internal kω pullup resistor to V DD. When RESET is pulled low either by internal circuitry, or driven externally, the analog output buffers are latched into a high-impedance state. After RESET is released, the output buffers remain disabled. The outputs may be enabled by sending a new -bit data word or a 6-bit individual output address word. A reset is initiated from any of three sources. RESET can be driven low by external circuitry to initiate a reset, or RESET can be pulled low by internal circuitry during power-up (poweron-reset) or thermal shutdown.

33 x 6 Nonblocking Video Crosspoint Switch UPDATE MODE 6-BIT INDIVIDUAL OUTPUT ADDRESS MODE: FIRST BIT IS A DON'T CARE BIT, LAST 5 BITS CLOCKED INTO DIN WHEN MODE =, CREATES ADDRESS WORD; IC ADDRESS A A IS COMPARED TO DIN4 DIN WHEN UPDATE IS LOW; IF EQUAL, ADDRESSED OUTPUT IS UPDATED tsumd t HdMd SCLK DIN DON'T CARE X IC ADDRESS A IC ADDRESS A IC ADDRESS A IC ADDRESS A OUTPUT ADDRESS B OUTPUT ADDRESS B OUTPUT ADDRESS B OUTPUT ADDRESS B OUTPUT ENABLE GAIN SET = +V/V ADDRESS 4 (MSB) = ADDRESS = ADDRESS = ADDRESS = ADDRESS (LSB) = IC ADDRESS = OUTPUT ADDRESS = 9 OUTPUT (i) ENABLED, A V = +V/V, CONNECTED TO 6 EXAMPLE OF 6-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL IN INDIVIDUAL OUTPUT ADDRESS MODE Figure. Mode, Individual Output Address Mode Timing and Programming Example Since driving RESET low only clears the output-bufferenable bit in the matrix control latches, RESET can be used to disable all outputs simultaneously. If no new data has been loaded into the -bit complete matrix mode register, a single UPDATE restores the previous matrix control settings. Power-On-Reset The power-on-reset ensures all output buffers are in a disabled state when power is initially applied. A V DD voltage comparator generates the power-on-reset. When the voltage at V DD is less than.5v, the poweron-reset comparator pulls RESET low via internal circuitry. As the digital-supply voltage ramps up crossing.5v, the holds RESET low for 4ns (typ). Connecting a small capacitor from RESET to DGND extends the power-on-reset delay. (see the Power-On- Reset vs. RESET Capacitance graph in Typical Operating Characteristics). Thermal Shutdown The features thermal shutdown protection with temperature hysteresis. When the die temperature exceeds 5 C, the pulls RESET low, disabling the output buffer. When the die cools by C, the RESET pulldown is deasserted, and output buffers remain disabled until the device is programmed again. Applications Information Building Large Video-Switching Systems The can be easily used to create larger switching matrices. The number of ICs required to implement the matrix is a function of the number of input channels, the number of outputs required, and whether the array needs to be nonblocking or not.

34 x 6 Nonblocking Video Crosspoint Switch SCLK DIN t SuDi t HdDi t MnLCk t MnHCk t SuHUd t MnLUd UPDATE t PdDo DOUT SCLK EXAMPLE OF 7-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL DIN NEXT CONTROL WORD OUTPUT (i) ENABLED, A V = +V/V, CONNECTED TO 8 ENABLE OUTPUT GAIN SET = +V/V ADDRESS 4 (MSB) = ADDRESS = ADDRESS = ADDRESS = ADDRESS (LSB) = Figure 4. 7-Bit Control Word and Programming Example (Mode : Complete Matrix Mode) UPDATE MODE 7-BIT CONTROL WORD DIN OUT OUT OUT MOST SIGNIFICANT BITS OF THE 7-BIT CONTROL WORD ARE SHIFTED IN FIRST; I.E. OUT5, THEN OUT4, ETC. LAST 7 BITS SHIFTED IN PRIOR TO UPDATE FALLING EDGE PROGRAM OUT. TIME Figure 5. Mode : Complete Matrix Mode Programming 4

35 x 6 Nonblocking Video Crosspoint Switch Table. Chip Address Programming for 6-Bit Control Word (Mode : Individual Output Address Mode) IC ADDRESS BIT ADDRESS A (MSB) A A A (LSB) Chip Address (Hex) Chip Address (Decimal) h h h h 4h 4 5h 5 6h 6 7h 7 8h 8 9h 9 Ah Bh Ch Dh Eh 4 Fh 5 Table 4. Chip Address A A Pin Programming PIN ADDRESS A A A A Chip Address (Hex) Chip Address (Decimal) DGND DGND DGND DGND h DGND DGND DGND V DD h DGND DGND V DD DGND h DGND DGND V DD V DD h DGND V DD DGND DGND 4h 4 DGND V DD DGND V DD 5h 5 DGND V DD V DD DGND 6h 6 DGND V DD V DD V DD 7h 7 V DD DGND DGND DGND 8h 8 V DD DGND DGND V DD 9h 9 V DD DGND V DD DGND Ah V DD DGND V DD V DD Bh V DD V DD DGND DGND Ch V DD V DD DGND V DD Dh V DD V DD V DD DGND Eh 4 V DD V DD V DD V DD Fh 5 5

36 x 6 Nonblocking Video Crosspoint Switch Table 5. Output Selection Programming OUTPUT ADDRESS BIT B (MSB) B B B (LSB) SELECTED OUTPUT S ( ) S ( 6) S (64 95) S (96 7) IN IN IN IN 6 OUT 6 OUT 6 OUT 6 OUT OUTPUTS ( 5) IN IN IN IN 6 OUT 6 OUT 6 OUT 6 OUT Figure 6. 8 x Nonblocking Matrix Using x 6 Crosspoint Devices OUTPUTS (6 ) The most straightforward technique for implementing nonblocking matrices is to arrange the building blocks in a grid. The inputs connect to each vertical bank of devices in parallel with the other banks. The outputs of each building block in a vertical column connect together in a wired-or configuration. Figure 6.shows a 8-input, -output, nonblocking array using eight crosspoint devices. The wire-or connection of the outputs shown in the diagram is possible because the outputs of the IC devices can be placed in a disabled, or high-impedance-output state. This disable state of the output buffers is designed for a maximum impedance vs. frequency while maintaining a low output capacitance. These characteristics minimize the adverse loading effects from the disabled outputs. Larger arrays are constructed by extending this connection technique to more devices. Driving a Capacitive Load Figure 6 shows an implementation requiring many outputs to be wired together. This creates a situation where each output buffer sees not only the normal load impedance, but also the disabled impedance of all the other outputs. This impedance has a resistive and a capacitive component. The resistive components reduce the total effective load for the driving output. 6