Low complexity, software based, high rate DSD modulator using Vector Quantification.

Transcription

1 Audio Egieerig Society Covetio Paper Preseted at the 4th Covetio 6 Jue 4 7 Paris, Frace his paper was peer-reviewed as a complete mauscript for presetatio at this Covetio. his paper is available i the AES E- Library, All rights reserved. Reproductio of this paper, or ay portio thereof, is ot permitted without direct permissio from the Joural of the Audio Egieerig Society. Low complexity, software based, high rate DSD modulator usig Vector Quatificatio. hierry Heeb, iziao Leidi, Diego Frei 3, ad Alexadre Lavachy 4 Research Scietist, ISI - SUPSI, Galleria, CH-698 Mao thierry.heeb@supsi.ch Research Scietist, ISI - SUPSI, Galleria, CH-698 Mao tiziao.leidi@supsi.ch 3 Research Scietist, ISI - SUPSI, Galleria, CH-698 Mao diego.frei@supsi.ch 4 CEO, Egieered SA, Aveue des Sports 8, CH-4 Yverdo-les-Bais alavachy@egieered.ch ABSRAC High rate Direct Stream Digital DSD) is emergig as a format of choice for distributio of high-defiitio audio cotet. However, real-time ecodig of such streams requires cosiderable computig resources due to their high samplig rate, costraiig implemetatios to hardware based platforms. I this paper we disclose a ew modulator topology allowig for reductio i computatioal load ad makig real-time high rate DSD ecodig suitable for software based implemetatio o off-the-shelf Digital Sigal Processors DSPs). We first preset the architecture of the proposed modulator ad the show results from a practical real-time implemetatio.. IRODUCIO Direct Stream Digital DSD) is a high-resolutio audio data format iitially proposed by Soy ad Philips i the late 9s for the Super Audio CD SACD) optical disc. It is based o Pulse Desity Modulatio PDM) ad cosists i a stream of sigle bit data sampled at high rate. For SACD, a samplig rate of.84 MHz 64 x 44. kh was selected, providig high Sigal to oise Ratio SR) ad wide badwidth at the cost of a steeply raisig oise floor above khz. his raise results from the aggressive oise-shapig provided by the high-order delta-sigma modulator used for PDM geeratio. Despite its promises for high-resolutio audio, the limited commercial success of SACD did costrai the DSD format to the audiophile commuity, with oly margial awareess of the format s existece amog the geeral public. Recet advaces i dematerialized music distributio have brought DSD back to the frot scee. Several music dowload sites are ow offerig a growig

2 catalog of DSD ecoded high-resolutio audio tracks, fuelig cosumer iterest for the DSD format. As dowloads are ot costraied by the capacity of optical discs, higher DSD samplig rates ca be used, lowerig costraits o the modulators ad pushig the steep oise floor raise away from the audio bad. Samplig rates of MHz 8 x 44. kh or.896 MHz 56 x 44. kh are ow commoly supported by playback hardware such as USB Digital to Aalog Coverters. Oe drawback of the DSD audio format is that ay digital sigal processig doe o a DSD stream except for a pure delay) destroys its oe bit ature. Hece reecodig is required, eve after simplistic processig such as gai cotrol. his causes a serious challege i terms of computig resources for real-time systems, especially for high rate DSD at 8 or 56 x 44. khz, callig for hardware based ASIC or FPGA) implemetatio of the modulators ad resultig i limited flexibility ad added cost. his paper discloses a ovel modulator topology addressig these issues ad suitable for real-time implemetatio o off-the-shelf programmable Digital Sigal Processors DSPs). I the followig sectios, we preset the key ideas leadig to the proposed modulator architecture followed by the results of a practical implemetatio o a stadard DSP. A itroductio to the simulatio ifrastructure developed for the desig of the ew modulator architecture is also provided.. DELA-SIGMA MODULAIO.. Backgroud Delta-sigma modulators [] are widely used for PDM geeratio. he geeral structure for such a modulator is show i figure. he output of the modulator is subtracted from the iput sigal ad passed through the loop filter H before beig set to the quatizer Q. Provided that the filter H exhibits a delay of at least oe sample for causality reasos) ad that the quatizatio error E ca be approximated by white oise, the system ca be described by followig equatios: where: Y SF X F E ) SF F H H ) H 3 ) SF is the Sigal rasfer Fuctio SF) of the system, ad F is the oise rasfer Fuctio F) of the system Followig diagram shows a typical 5th order loop filter, implemeted as a feed-forward topology with dual resoators. his topology is used for the modulators preseted throughout this paper. ote that all itegrators are of the delayig type, esurig that H exhibits at least oe sample delay. he resoators have a sigle sample delay, allowig for placemet of the correspodig poles o the uit circle to guaratee stability of the oise rasfer Fuctio F. Figure : H loop filter implemetatio Figure : Delta-sigma modulator AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page of

3 .. State-space represetatio A a, a, a, a3, a4), ) S ), S ), S ), S3 ), S4, Cosiderig the vectors S )) FB ) ) Y ),,,, ad I ) ) X ),,,,, the modulator s operatio ca be described i the state-space domai by followig matrix/vector operatios: where S ) M S ) I ) FB ) M 4 ) Y ) Q A S ) 5 ) g g g is the state trasitio matrix ad quatizatio fuctio. g Q represets the.3. Advaced modulatio algorithms Over the last decade, alterative topologies such as rellis see [], [3] ad [4]) or Look-Ahead [5], [6] ad [7]) modulators have bee preseted, offerig greatly ehaced performace i terms of Sigal to oise Ratio SR) ad/or F corer frequecy. Istead of performig istataeous, per sample quatizatio, these algorithms select their output amog a umber of output cadidates, based o the optimizatio of a Cost Fuctio CF). Followig diagram shows the operatig priciple of such a modulator. Figure 3: Modulator topology based o Cost Fuctio I a CF based modulator, output cadidates are subtracted from the iput sigal ad passed through a weightig filter H. he output of this filter is the processed by the CF to select the output cadidate miimizig its value. ypical output cadidates are streams of tes to thousads of bits which ievitably itroduce a correspodig delay ito the system. Cosiderig a CF based modulator maitaiig K output cadidates, each ew iput sample requires K computatios of the loop filter ad the CF, plus sortig amog cadidates. Hece its computatioal load is sigificatly higher tha the oe of a stadard modulator. ypical values for K are betwee 4 ad Requiremets for high resolutio audio ad computig load estimatios I Referece [8], Stuart ad Crave explore the peak level to back-groud oise ratio of high-defiitio recorded audio sigals. hese two sigals ted to superpose above 45 to 5 khz at a level aroud - db to - db. I order to faithfully reproduce the audio sigal, oise itroduced by the modulatio process should ot exceed this value. Due to their steep raise i oise floor above khz, stadard delta-sigma modulators operatig at.84 MHz DSD64) fail to meet these requiremets. O the other had, stadard modulators ruig at MHz DSD8) or.896 MHz DSD56) ca easily be desiged to come close to or exceed them. With a sufficietly large set of output cadidates, advaced modulators, such as rellis or Look-Ahead modulators, are able to meet or come close to these requiremets at.84mhz already, showig their clear advatage i terms of performace at a give samplig rate. Followig table shows a summary of performace ad computatioal load estimatios for both stadard ad advaced modulators at differet rates. he computatioal load for a stadard modulator ruig at.84 MHz is ormalized to. Advaced modulators are supposed to be implemetable at 4 times this load [9]. Modulator Stadard delta-sigma modulator Rate DSD64 DSD8 DSD56 Performace Load 4 Modulator Advaced modulator Rate DSD64 DSD8 DSD56 Performace Load able : Performace ad load AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 3 of

4 Give that stadard delta-sigma modulators match or come close to) the requiremets of high-defiitio recordigs for DSD8 ad DSD56, it is iterestig to explore if gais i computatioal load ca be obtaied for these high rate DSD formats. Advaced modulators clearly show a advatage i terms of performace for a give DSD rate, but their computatioal load makes them less attractive for real-time implemetatio. 3. VECOR QUAIFICAIO VQ) MODULAOR 3.. Modified modulator Ispired by CF based topologies ad [], we propose a modified modulator as show i the diagram below. Istead of applyig the weightig filter H to the differece betwee the iput sigal X ad the output cadidatesy, both paths have their ow weightig filter ad the cost fuctio is applied to the differece of the filters outputs. Upo selectio of the best output cadidate, the states itegrators) of the weightig filter of the iput path are updated accordigly. he idea behid Vector Quatizatio is to be able to produce multiple output bits at each processig roud of the modulator. More precisely, at each processig roud, a output vector y, y,..., y ) is Y produced, correspodig to iput samples is called the Block Legth BL) of the modulator). By doig so, the operatio rate of the modulator is effectively reduced by a factor. Provided that the complexity of the reduced rate modulator is less tha times the complexity of the full rate modulator, VQ allows for a reductio i computatioal load of the system. Give that the target platforms for the ew modulator are programmable DSPs with sigle cycle full precisio Multiply-Accumulate MAC) istructios istead of hardware platforms such as ASICs or FPGAs, quatizatio of filter coefficiets to the sum of a few powers of is ot required for optimal implemetatio. If output cadidates are limited to the possible outputs of a data block, efficiet implemetatio of the topology is possible. Followig diagram shows the operatig priciple of a VQ modulator. he iput sigal samplig rate is Fs. Figure 4: Modified, separated path modulator based o Cost Fuctio he primary beefit of this approach is to isolate the computatio of the weighted cotributio of the output cadidates from the iput sigal ad past outputs) cotributios. I other words, cotributios from output cadidates ca be computed off-lie ad this is a key elemet of the ew modulator topology. I additio, weighted paths for both iput ad output cadidates are shaped by the low-pass characteristic of H. ote that i the case of the CF beig implemeted as the magitude of the curret sample ad usig the filter H show i figure, this topology ca be made equivalet to the stadard delta-sigma modulator of figure. Figure 5: VQ modulator topology 3.. rajectories Let s cosider a VQ modulator with a Block Legth of. For a give state S S, S,..., SL) of the filter H ad iput data block x, x,..., x ) X, we defie the Path P X, S) as the vector p, p,..., p ) of correspodig weightig filter output samples. A rajectory X, S) is defied as a cotiuous time approximatio of a Path. More AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 4 of

5 precisely X, S) is a real valued fuctio over the iterval ; such that X, S) ) p for,...,, where is a small) positive umber. A example of a rajectory with is give by the th order polyomial approximatio of the poits, p ). For sufficietly large, the liear regressio of the poits, p ) ca also be cosidered as a rajectory of the system. he goal is to fid low complexity rajectories with sufficietly small to get cheap, reliable approximatios of the system s behavior over its Block Legth Give that the filter H is a liear time ivariat system, Paths are liear with respect to filter states S, S,..., SL ad iput data block X. Let S i defie the weightig filter state where all states are, except Si for i,,..., L. Assumig existece of low complexity approximatios for ad X,), the L, Si ), i,..., L X, S) Si, S ),) 6 ) i i X is a low complexity approximatio of P X, S). If, Si ), i,..., L ad X,) ca each be expressed as polyomials of order R, Equatio 6) ca be rewritte as X, S) L R j Si qijt i j j R L j j i R v t j v Si q ) t 7 ) As a example, cosider a 5th order VQ modulator implemetig the filter H show i figure, ad usig a block legth of 4. Followig picture shows the Paths P, Si ), i,..., 4. ij j j Figure 6: State paths S, S, S, S3 ad S4) Usig a best fit algorithm, d order polyomial rajectories ca be built for Paths P, Si ), i,...,4. Followig table shows the Paths values ad the related rajectories relative error values. ime State Value t = Error [%] Value t = Error [%] S S S S S ime State Value t = 3 Error [%] Value t = 4 Error [%] S S S S S able : State Paths values ad d order polyomial rajectories relative errors Similar cotiuous-time extesios rajectories) for the output cadidates y, y,..., y ) passed Y through the filter H ca be computed. Give the system s liearity i terms of filter states S, it is sufficiet to cosider rajectories with iitial state S. As the umber of output cadidates is limited cadidates at most), results may be stored i a read-oly table or computed oce at start-up) if is ot too large. Hece, gettig rajectories for output cadidates reduces to simple table look-ups. Followig picture shows the differet output cadidate Paths for a VQ modulator with Block Legth 4. S S S S3 S4 AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 5 of

6 mea X, S), ) X, S) t) t). k t Whilst this CF offers good performace for small modulatio idexes i.e. for small iput sigals), it results i modulator istability for high level iput sigals. he reaso for this is that the mea fuctio destroys ay phase iformatio preset i the rajectories. Hece CF should be desiged to preserve at least part of the) phase iformatio. -3 Figure 7: Output Cadidates Paths 4 ) 3.3. Quatizatio Quatizatio is determied by the miimizatio of the Cost Fuctio CF) o the set of available output cadidates. Give the cocept of rajectories which provide cotiuous-time extesios of the system s ad output cadidates Paths, various types of Cost Fuctios ca be cosidered, all represetig some form of patter matchig betwee the system ad the output cadidates rajectories. For istace, if both system ad output cadidates rajectories are give by possibly piece-wise) polyomials, the Cost Fuctio ca be implemeted as a closed-form aalytical expressio such as the L orm of the rajectories differece where is the rajectory of the th output cadidate): CF X, S), ) X, S) t) t)) dt 8 ) Alteratively, Cost Fuctios, which oly compare rajectories o a fiite set of discrete poits, may be used. ote that give the cotiuous-time ature of rajectories, these discrete poits do t eed to be aliged with the samplig poits of the iput sigal. A example of such a Cost Fuctio is the sum of squared differeces magitudes over K discrete poits: K k k k )) 9 ) CF X, S), ) X, S) t ) t I order to keep computatioal load low, it is temptig to cosider very simple Cost Fuctios. Oe such example is the mea fuctio defied by If X, S) ca be discretized to a fiite umber of differet values, computatio of the Cost Fuctio ca be approximated by a table look-up, makig it very efficiet i terms of actual implemetatio. For istace, cosider the case where 4 ad the system s rajectories are defied by d order polyomials. Coefficiets of the d order polyomials X, S) b b t b t ca be computed usig Equatio 7) ad quatized to B i bits respectively i,, ). he Cost Fuctio ca the be B B B ) approximated by accessig a etries lookup table, cotaiig the idexes of the optimal output cadidates. his table is called the Quatizatio able Q). Graularity of the Q must be fie eough to properly resolve the differet output cadidates. Ditherig must geerally be applied to avoid correlatio betwee quatizatio oise ad iput sigal cotet. It ca be applied directly at the poit of the discretizatio of the system s rajectories parameters discretizatio of coefficiets b to B bits i the example above) or i i values. Alteratively, it may be itegrated ito the Quatizatio able. Istead of storig oly the optimal output cadidate for a give discretized rajectory X, S) r, the Q may be exteded to store the idexes of the r ) best output cadidate. Ditherig ca the be implemeted by usig a radom umber geerator with rage,..., r to select oe amog the r best output cadidates. Mechaisms to costrai the selectio depedig o iput sigal level ad/or iteral modulator states may be required to guaratee modulator stability Efficiet state-space implemetatio State-space represetatio provides the foudatio for efficiet implemetatio of the proposed VQ modulator. AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 6 of

7 Startig from the state-space equatios of a stadard modulator, we observe that uder the coditio of costat feedback, the system s state at time ca be computed by iteratig Equatio 4) times. If the iput data vector X x, x,..., x ) ca x x for be cosidered as costat i.e.,..., ), this ca be expressed as: S ) SEM S ) IEV ) ) where SEM M is desigated as the State Evolutio Matrix SEM) ad i i ) M I ) M x i i IEV,,...,) is called the Iput Evolutio Vector IEV). For a output cadidate with idex, let OSE ose, ose,..., ose L ) be the vector of state values obtaied whe ruig this output cadidate through the filter H. Based o these defiitios, the operatio of the VQ modulator ca be described by the followig algorithm:. Compute X, S) ad discretize its parameters or values.. Use discretized values to fid optimal output cadidate idex with ditherig) by Q look-up. 3. Update state values usig Equatio ). 4. Correct state values for the optimal output cadidate usig S ) S ) OSE. 5. Limit state values to cotrol modulator stability). I order to estimate the complexity of the proposed VQ modulatio algorithm, it is iterestig to compare it to the stadard delta-sigma modulator algorithm described by equatios 4) ad 5). Let s cosider a stadard 5 th order modulator implemetig the filter of figure. For typical values of K or 3 ad 4, complexity estimatios result i about 4% savigs compared to the stadard modulator. his would reder high rate DSD modulatio suitable for software implemetatio o moder DSPs. 4. SIMULAIOS AD PRACICAL IMPLEMEAIO 4.. Simulatios With the goal of easig ad acceleratig the idetificatio of desig iefficiecies ad developmet errors i the modulator, a ifrastructure for automatic executio of large umber of simulatio rus has bee set up. eed for efficiet a simulatio ifrastructure was maily motivated by the o-liear ature of the modulator system. Small variatios i the defiitio of the Cost Fuctio modify the modulator behavior sigificatly, with cosequet risk of istabilities ad poor performace. Extesive simulatios allowed for covergig to low-complexity, low-distortio modulators. For this purpose, a developmet tool called Digital Stream Processig Eviromet DSPE) [, ] has bee adopted ad customized with specific extesios specific for bit modulator aalysis. DSPE is a developmet tool provided by SUPSI for desigig ad implemetig parallel stream-processig applicatios for multi-core processors ad accelerators such as GPUs [ It is itegrated with the Eclipse developmet platform. DSPE features a modelbased domai-specific laguage ad C/C++ source code geerators that prove particularly useful at applicatio prototypig ad performace aalysis. DSPE is released uder the ope-source Eclipse Public Licese EPL). I recet academic research projects [3], DSPE has bee exteded with fuctioality for performig computatioally itesive simulatios by meas of dedicated support for schedulig batch executios of multiple applicatio rus. his ifrastructure has bee exploited for performig the required modulator simulatios. For this purpose, DSPE has bee ehaced with specific software compoets for several variats of the modulator i particular i terms of Cost Fuctio) ad for aalysis of the resultig modulated data streams. I particular, simulatios have bee used to optimize discrete Cost Fuctios accordig to Equatio 9). Simulatios revealed that selectio of the discrete time poits for Cost Fuctio computatio have a sigificat impact o modulator performace. Amog others, it was foud that Cost Fuctios operatig properly at high iput sigal level may perform poorly whe fed with small iput sigals or the other way roud. AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 7 of

8 Followig figure shows such a case where distortio appears for a -34dB iput sie wave. haks to extesive simulatio rus, simple or 3 poits), low distortio, discrete Cost Fuctios could be costructed ad subsequetly implemeted for real-time applicatios. that the test platform s architecture requires a Asychroous Sample Rate Coverter ASRC) to be used o the DSP s SPDIF iput ad that modulators are effectively operated at multiples of 48 khz. Followig table shows some performace figures for DSD8 ecodig. Measuremet Stadard delta-sigma VQ modulator SR Hz-kH, uweighted -6 db -6 db SR Hz-kH, A-weighted -9 db -9 db HD+ Hz-kH, khz db -6 db -6 db able 3: Audio performace figures Figure 8: ypical small sigal error for poorly defied Cost Fuctio he graphs below show the low frequecy spectrum of DSD8 modulatio with a -3dB, respectively -8dB khz sie wave iput. Plots have bee made usig 8 times averaged poits FFs. Results for DSD56 ca be extrapolated by doublig the frequecy. 4.. Real-time implemetatio o ADSP-489 I order to compare performaces ad computatioal loads, both the stadard delta-sigma ad the VQ modulator with 4 ) algorithms have bee ported to the Aalog Devices ADSP-489 DSP. he implemetatios have bee optimized i Assembler ad make extesive use of the processor s SIMD architecture to process stereo data streams. Real-time audio performaces have bee aalyzed usig the setup show i the figure below: Figure Modulator low frequecy spectrum plots, stadard modulator top), VQ modulator bottom) he above results show that the performaces of the VQ modulator are equivalet to those of the stadard modulator. Computatioal load has bee aalyzed usig both liear ad statistical profilig. Liear profilig was used for dry algorithms aalysis whereas statistical profilig was used to assess computatioal loads uder real-world coditios. Results are show below. Figure 9 est setup he audio aalyzer geerates digital test sigals set to the DSP over SPDIF. he DSP recovers the PCM digital audio data ad applies the modulatio algorithms to produce stereo DSD streams. hese streams are the processed by a high quality DSD to PCM coverter before beig set back to the aalyzer over SPDIF. ote AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 8 of

9 Setup Stadard delta-sigma VQ modulator DSD8, liear profilig 8.5 MIPS 8.5 MIPS DSD56, liear profilig 36 MIPS 9 MIPS DSD8, statistical profilig 83 MIPS MIPS DSD56, statistical profilig 365 MIPS MIPS able 4: Computatioal load he VQ modulator provides a close to 4% beefit i computatioal load with o oticeable impact o performace compared to the stadard delta-sigma modulator, makig it very attractive for software based implemetatio. I particular, VQ modulators allow for high-quality stereo DSD8 ecodig at less tha MIPS o moder DSP architectures. 5. COCLUSIOS his paper has preseted a ew, simple algorithm for high rate DSD ecodig showig similar performace to stadard delta-sigma modulatio at sigificatly reduced computatioal load, makig it suitable for software based implemetatio o off-the-shelf digital sigal processors. his advatage i terms of computatioal requiremets ca also be used to implemet modulator ehacemets while maitaiig load similar to stadard delta-sigma modulators. akig SDPC Sigma Delta Predictio Correctio) [4] as a example, the load reductio provided by VQ modulators allows the two modulators required for SDPC i its basic form) to cosume oly slightly more MIPS tha a sigle stadard modulator. Similarly, the VQ modulator also presets advatage for advaced topologies such as rellis modulators. By replacig the stadard modulators used for each output cadidate, the computatioal load of advaced modulators ca be reduced accordigly. I additio, VQ modulatio allows for classificatio accordig to Cost Fuctio of the possible evolutios of a output cadidate to be realized by simple table look-ups i a exteded Quatificatio able, which could brig further reductio i computatioal load. I such a implemetatio, the idividual VQ modulators ca be cosidered as small, local rellis over the possible evolutios of a output cadidate. Research o VQ modulators curretly cotiues withi our group with focus o achievig average pulse rate reductio ad icreasig the maximum stable modulatio idex to make the algorithm suitable for digital switchig amplifier applicatios. We work o exploitig the reduced computatioal load of VQ modulators to apply both optimal ad reduced pulse rate output cadidates i parallel ad to decide which path to follow depedig o evolutio of the iteral modulator states over the followig rouds. Although this research is still i its early stages, it already shows promisig results. 6. ACKOWLEDGEMES his work has bee sposored by the o-goig grat 689.PFIW-IW of the Swiss federal Commissio for echology ad Iovatio CI) ad has bee realized i collaboratio betwee the Uiversity of Applied Scieces of Souther Switzerlad SUPSI) i Mao ad Egieered SA i Yverdo-les-Bais, Switzerlad. 7. REFERECES [] S.R. orsworthy, R. Schreier ad G.C. emes, Delta-Sigma Data Coverters, heory, Desig, ad Simulatio, IEEE Press, Wiley- Itersciece, 997, ISB [] H. Kato, rellis oise-shapig Coverters ad -bit digital audio, preseted at th AES Covetio, Muich, Germay, May - 3. [3] P. Harpe, D. Reefma ad E. Jasse, Efficiet rellis-type Sigma Delta Modulator, preseted at 4th AES Covetio, Amsterdam, he etherlads, 3 March -5. [4] E. Jasse ad D. Reefma, Advaces i rellis based SDM structures, preseted at 5th AES Covetio, ew-york, Uited States of America, 3 October -3. [5] J.A.S. Agus, ree Based Lookahead Sigma Delta Modulators, preseted at 4th AES Covetio, Amsterdam, he etherlads, 3 March -5. [6] J.A.S. Agus, Efficiet Algorithms for Look- Ahead Sigma-Delta Modulators, preseted at 5th AES Covetio, ew-york, Uited States of America, 3 October -3. AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page 9 of

10 [7] M.O. Hawksford, Parallel Look-Ahead Digital SDM with Eergy-Balace Biary Comparator, J. Audio Eg. Soc., vol.56, o, pp , 8 December. [8] J.R. Stuart ad P.G. Crave, A Hierarchical Approach to Archivig ad Distributio, preseted at 37th AES Covetio, Los Ageles, Uited States of America, 4 October 9-. [9] E. Jasse ad D. Reefma, DSD compressio for recet ultra high quality -bit coders, preseted at 8th AES Covetio, Barceloa, Spai, 5 May -3. [] US Patet US 7 9 7, Method ad device for the versio of digital sigals with heterogeeous formats ad applicatio thereof to the digital amplificatio of audio sigals []. Leidi,. Heeb, M. Colla ad J.-P. hira, Model-Drive Developmet of Audio Processig Applicatios for Multi-Core Processors, preseted at 8th AES Covetio, Lodo, Uited Kigdom,, May -5. []. Leidi,. Heeb, M. Colla ad J.-P. hira, Evet-Drive Real-ime Audio Processig with GPGPUs, preseted at 3th AES Covetio, Lodo, Uited Kigdom,, May 3-6. [3]. Leidi, G. Scocchi, A. Ortoa, L. Grossi, S. Pusterla, C. D Agelo ad J.-P. hira, Computig effective properties of radom heterogeeous materials o heterogeeous parallel processors, i Computer Physics Commuicatios, Elsevier,. [4] D. Reefma ad E. Jasse, Ehaced Sigma Delta Structures for Super Audio CD Applicatios, preseted at th AES Covetio,, Muich, Germay, May -3. AES 4th Covetio, Paris, Frace, 6 Jue 4 7 Page of