Data Sheet. ATF Low Noise Pseudomorphic HEMT in a Surface Mount Plastic Package. Features. Description. Specifications
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1 ATF Low Noise Pseudomorphic HEMT in a Surface Mount Plastic Package Data Sheet Description Avago s ATF is a high dynamic range, low noise PHEMT housed in a 4-lead SC-7 (SOT 343) surface mount plastic package. Based on its featured performance, ATF is ideal for the first stage of base station LNA due to the excellent combination of low noise figure and high linearity [1]. The device is also suitable for applications in Wireless LAN, WLL/RLL, MMDS, and other systems requiring super low noise figure with good intercept in the 4 MHz to 1 GHz frequency range. Note: 1. From the same PHEMT FET family, the larger geometry ATF may also be considered either for the higher linearity performance or easier circuit design for stability in the lower frequency bands (8 9 MHz). Surface Mount Package - SOT-343 Pin Connections and Package Marking Features Lead-free Option Available Low Noise Figure Excellent Uniformity in Product Specifications 8 micron Gate Width Low Cost Surface Mount Small Plastic Package SOT 343 (4 lead SC-7) Tape-and-Reel Packaging Option Available Specifications 1.9 GHz; 4V, 6 ma (Typ.). db Noise Figure 17. db Associated Gain 2 dbm Output Power at 1 db Gain Compression 31. dbm Output 3 rd Order Intercept Applications Tower Mounted Amplifier and Low Noise Amplifier for GSM/TDMA/CDMA Base Stations LNA for Wireless LAN, WLL/RLL and MMDS Applications General Purpose Discrete PHEMT for other Ultra Low Noise Applications DRAIN SOURCE 4Px SOURCE GATE Note: Top View. Package marking provides orientation and identification. 4P = Device code x = Date code character. A new character is assigned for each month, year. Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 1) Refer to Avago Application Note A4R: Electrostatic Discharge Damage and Control.
2 ATF Absolute Maximum Ratings [1] Absolute Symbol Parameter Units Maximum V DS Drain - Source Voltage [2] V. V GS Gate - Source Voltage [2] V - V GD Gate Drain Voltage [2] V - I D Drain Current [2] ma I dss [3] P diss Total Power Dissipation [4] mw 7 P in max RF Input Power dbm 17 T CH Channel Temperature C 16 T STG Storage Temperature C -6 to 16 θ jc Thermal Resistance [] C/W Operation of this device above any one of these parameters may cause permanent damage. 2. Assumes DC quiescent conditions. 3. V GS = volts. 4. Source lead temperature is C. Derate 6 mw/ C for T L > 4 C.. Thermal resistance measured using C Liquid Crystal Measurement method. 6. Under large signal conditions, V GS may swing positive and the drain current may exceed I dss. These conditions are acceptable as long as the maximum P diss and P in max ratings are not exceeded. Product Consistency Distribution Charts [7] I DS (ma) V V Std +3 Std Cpk = Std =.66 9 Wafers Sample Size = 4.6 V V DS (V) Figure 1. Typical/Pulsed I-V Curves [6]. (V GS = -.2 V per step) OIP3 (dbm) Figure 2. 2 GHz, 4 V, 6 ma. LSL=29., Nominal=31.8, USL= Cpk = Std =.4 9 Wafers Sample Size = Cpk = Std =. 9 Wafers Sample Size = Std +3 Std 6-3 Std +3 Std NF (db) Figure 3. 2 GHz, 4 V, 6 ma. LSL=.1, Nominal=.47, USL= GAIN (db) Figure 4. 2 GHz, 4 V, 6 ma. LSL=16., Nominal=17., USL= Distribution data sample size is 4 samples taken from 9 different wafers. Future wafers allocated to this product may have nominal values anywhere within the upper and lower spec limits. 8. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based on production test requirements. Circuit losses have been de-embedded from actual measurements. 2
3 ATF Electrical Specifications T A = C, RF parameters measured in a test circuit for a typical device Symbol Parameters and Test Conditions Units Min. Typ. [2] Max. I dss [1] Saturated Drain Current V DS = 1. V, V GS = V ma V P [1] Pinchoff Voltage V DS = 1. V, I DS = 1% of I dss V I d Quiescent Bias Current V GS = -.3, V DS = ma 6 g m [1] Transconductance V DS = 1. V, g m = I dss /V P mmho I GDO Gate to Drain Leakage Current V GD = V µa I gss Gate Leakage Current V GD = V GS = - µa 3 3 NF Noise Figure f = 2 GHz V DS =, I DS = 6 ma db..8 V DS =, I DS = 3 ma. f = 9 MHz V DS =, I DS = 6 ma db.4 G a Associated Gain f = 2 GHz V DS =, I DS = 6 ma db V DS =, I DS = 3 ma 17 f = 9 MHz V DS =, I DS = 6 ma db 21. OIP3 Output 3 rd Order f = 2 GHz V DS =, I DS = 6 ma dbm Intercept Point [3] + dbm P out /Tone V DS =, I DS = 3 ma 3 f = 9 MHz V DS =, I DS = 6 ma dbm 31 + dbm P out /Tone P 1dB 1 db Compressed f = 2 GHz V DS =, I DS = 6 ma dbm 2 Intercept Point [3] V DS =, I DS = 3 ma Guaranteed at wafer probe level 2. Typical value determined from a sample size of 4 parts from 9 wafers. 3. Using production test board. f = 9 MHz V DS =, I DS = 6 ma dbm 18. Input Ohm Transmission Line Including Gate Bias T (. db loss) Input Matching Circuit Γ_mag =.3 Γ_ang = 6 (.4 db loss) DUT Ohm Transmission Line Including Drain Bias T (. db loss) Output Figure. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a trade-off between an optimal noise match and associated impedance matching circuit losses. Circuit losses have been de-embedded from actual measurements. 3
4 ATF Typical Performance Curves OIP3, P 1dB (dbm) OIP3 P 1dB I DSQ (ma) Figure 6. OIP3 and P 1dB vs. I DS and V DS Tuned for 6 ma at 2 GHz. [1,2] ASSOCIATED GAIN (db) 2 1 CURRENT (ma) Figure 7. Associated Gain vs. Current (I d ) and Voltage (V D ) at 2 GHz. [1,2] NOISE FIGURE (db) CURRENT (ma) Figure 8. Noise Figure vs. Current (I d ) and Voltage (V DS ) at 2 GHz. [1,2] OIP3, P 1dB (dbm) OIP3 P 1dB I DSQ (ma) Figure 9. OIP3 and P 1dB vs. I DS and V DS Tuned for 6 ma at 9 MHz. [1,2] ASSOCIATED GAIN (db) 2 1 CURRENT (ma) Figure 1. Associated Gain vs. Current (I d ) and Voltage (V D ) at 9 MHz. [1,2] NOISE FIGURE (db) CURRENT (ma) Figure 11. Noise Figure vs. Current (I d ) and Voltage (V DS ) at 9 MHz. [1,2] Fmin (db).6 G a (db) FREQUENCY (GHz) 6 ma 4 ma 2 ma FREQUENCY (GHz) Figure 12. Fmin vs. Frequency and Current at. Figure 13. Associated Gain vs. Frequency and Current at. 1. Measurements made on a fixed toned production test board that was tuned for optimal gain match with reasonable noise figure at 4V, 6 ma bias. This circuit represents a trade-off between optimal noise match, maximum gain match, and a realizable match based on production test board requirements. Circuit losses have been de-embedded from actual measurements. 2. P 1dB measurements are performed with passive biasing. Quicescent drain current, I DSQ, is set with zero RF drive applied. As P 1dB is approached, the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I DSQ the device is running closer to class B as power output approaches P 1dB. This results in higher PAE (power added efficiency) when compared to a device that is driven by a constant current source as is typically done with active biasing. As an example, at a V DS = and I DSQ = 1 ma, I d increases to 62 ma as a P 1dB of +19 dbm is approached. 6 ma 4 ma 2 ma 4
5 ATF Typical Performance Curves, continued G a (db) 2 8 C C -4 C FREQUENCY (GHz) Figure 14. Fmin and G a vs. Frequency and Temperature at V DS = 4V, I DS = 6 ma NF (db) P1dB, OIP3 (dbm) OIP3 P 1dB FREQUENCY (MHz) 8 C C -4 C Figure. P 1dB, IP3 vs. Frequency and Temperature at V DS = 4V, I DS = 6 ma. [1] GAIN (db), OP1dB, and OIP3 (dbm) I DSQ (ma) Gain OP1dB OIP3 NF Figure 16. NF, Gain, OP1dB and OIP3 vs. I DS at and 3.9 GHz Tuned for Noise Figure. [1] NOISE FIGURE (db) GAIN (db), OP1dB, and OIP3 (dbm) I DSQ (ma) Gain OP1dB OIP3 NF Figure 17. NF, Gain, OP1dB and OIP3 vs. I DS at and.8 GHz Tuned for Noise Figure. [1] NOISE FIGURE (db) P 1dB (dbm) Figure 19. P 1dB vs. I DS Active Bias Tuned for min 4V, 6 ma at 9 MHz. Note: 1. P 1dB measurements are performed with passive biasing. Quicescent drain current, I DSQ, is set with zero RF drive applied. As P 1dB is approached, the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I DSQ the device is running closer to class B as power output approaches P 1dB. This results in higher PAE (power added efficiency) when compared to a device that is driven by a constant current source as is typically done with active biasing. As an example, at a V DS = and I DSQ = 1 ma, I d increases to 62 ma as a P 1dB of +19 dbm is approached. I DS (ma) Figure 18. P 1dB vs. I DS Active Bias Tuned for 4V, 6 ma at 2 GHz. P 1dB (dbm) I DS (ma)
6 ATF Power Parameters tuned for Power, V DS =, I DSQ = 12 ma Freq (GHz) P 1dB (dbm) I d (ma) G 1dB (db) PAE 1dB (%) P 3dBm (dbm) I d (ma) PAE 3dB (%) Gamma Out_mag (Mag) Gamma Out_ang (Degrees) ATF Power Parameters tuned for Power, V DS =, I DSQ = 6 ma Freq (GHz) P 1dB (dbm) I d (ma) G 1dB (db) PAE 1dB (%) P 3dBm (dbm) I d (ma) PAE 3dB (%) Gamma Out_mag (Mag) Gamma Out_ang (Degrees) Pout (dbm), G (db), PAE (%) P in (dbm) P out Gain PAE Figure 2. Swept Power Tuned for Power at 2 GHz, V DS =, I DSQ = 12 ma. P out (dbm), G (db), PAE (%) P in (dbm) P out Gain PAE Figure 21. Swept Power Tuned for Power at 2 GHz, V DS =, I DSQ = 6 ma. 1. P 1dB measurements are performed with passive biasing. Quicescent drain current, I DSQ, is set with zero RF drive applied. As P 1dB is approached, the drain current may increase or decrease depending on frequency and dc bias point. At lower values of I DSQ the device is running closer to class B as power output approaches P 1dB. This results in higher PAE (power added efficiency) when compared to a device that is driven by a constant current source as is typically done with active biasing. As an example, at a V DS = and I DSQ = 1 ma, I d increases to 62 ma as a P 1dB of +19 dbm is approached. 2. PAE(%) = ((Pout Pin)/Pdc) x 1 3. Gamma out is the reflection coefficient of the matching circuit presented to the output of the device. 6
7 ATF Typical Scattering Parameters, V DS =, I DS = 2 ma Freq. S 11 S 21 S 12 S 22 MSG/MAG GHz Mag. Ang. db Mag. Ang. db Mag. Ang. Mag. Ang. db ATF Typical Noise Parameters V DS =, I DS = 2 ma Freq. F min Γ opt R n/ G a GHz db Mag. Ang. - db MSG/MAG and S 21 (db) MSG S FREQUENCY (GHz) MAG Figure 23. MSG/MAG and S 21 2 vs. Frequency at, 2 ma. 1. Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information. 2. S and noise parameters are measured on a microstrip line made on. inch thick alumina carrier. The input reference plane is at the end of the gate lead. The output reference plane is at the end of the drain lead. The parameters include the effect of four plated through via holes connecting source landing pads on top of the test carrier to the microstrip ground plane on the bottom side of the carrier. Two.2 inch diameter via holes are placed within.1 inch from each source lead contact point, one via on each side of that point. 7
8 ATF Typical Scattering Parameters, V DS =, I DS = 4 ma Freq. S 11 S 21 S 12 S 22 MSG/MAG GHz Mag. Ang. db Mag. Ang. db Mag. Ang. Mag. Ang. db ATF Typical Noise Parameters V DS =, I DS = 4 ma Freq. F min Γ opt R n/ G a GHz db Mag. Ang. - db MSG/MAG and S 21 (db) MSG S FREQUENCY (GHz) MAG Figure 24. MSG/MAG and S 21 2 vs. Frequency at, 4 ma. 1. Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information. 2. S and noise parameters are measured on a microstrip line made on. inch thick alumina carrier. The input reference plane is at the end of the gate lead. The output reference plane is at the end of the drain lead. The parameters include the effect of four plated through via holes connecting source landing pads on top of the test carrier to the microstrip ground plane on the bottom side of the carrier. Two.2 inch diameter via holes are placed within.1 inch from each source lead contact point, one via on each side of that point. 8
9 ATF Typical Scattering Parameters, V DS =, I DS = 4 ma Freq. S 11 S 21 S 12 S 22 MSG/MAG GHz Mag. Ang. db Mag. Ang. db Mag. Ang. Mag. Ang. db ATF Typical Noise Parameters V DS =, I DS = 4 ma Freq. F min Γ opt R n/ G a GHz db Mag. Ang. - db MSG/MAG and S 21 (db) S 21 MSG FREQUENCY (GHz) MAG Figure. MSG/MAG and S 21 2 vs. Frequency at, 4 ma. 1. Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information. 2. S and noise parameters are measured on a microstrip line made on. inch thick alumina carrier. The input reference plane is at the end of the gate lead. The output reference plane is at the end of the drain lead. The parameters include the effect of four plated through via holes connecting source landing pads on top of the test carrier to the microstrip ground plane on the bottom side of the carrier. Two.2 inch diameter via holes are placed within.1 inch from each source lead contact point, one via on each side of that point. 9
10 ATF Typical Scattering Parameters, V DS =, I DS = 6 ma Freq. S 11 S 21 S 12 S 22 MSG/MAG GHz Mag. Ang. db Mag. Ang. db Mag. Ang. Mag. Ang. db ATF Typical Noise Parameters V DS =, I DS = 6 ma Freq. F min Γ opt R n/ G a GHz db Mag. Ang. - db MSG/MAG and S 21 (db) MSG S FREQUENCY (GHz) MAG Figure 26. MSG/MAG and S 21 2 vs. Frequency at, 6 ma. 1. Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP test system. From these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information. 2. S and noise parameters are measured on a microstrip line made on. inch thick alumina carrier. The input reference plane is at the end of the gate lead. The output reference plane is at the end of the drain lead. The parameters include the effect of four plated through via holes connecting source landing pads on top of the test carrier to the microstrip ground plane on the bottom side of the carrier. Two.2 inch diameter via holes are placed within.1 inch from each source lead contact point, one via on each side of that point. 1
11 Noise Parameter Applications Information F min values at 2 GHz and higher are based on measurements while the F mins below 2 GHz have been extrapolated. The F min values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP test system. From these measurements, a true F min is calculated. F min represents the true minimum noise figure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically Ω, to an impedance represented by the reflection coefficient Γ o. The designer must design a matching network that will present Γ o to the device with minimal associated circuit losses. The noise figure of the completed amplifier is equal to the noise figure of the device plus the losses of the matching network preceding the device. The noise figure of the device is equal to F min only when the device is presented with Γ o. If the reflection coefficient of the matching network is other than Γ o, then the noise figure of the device will be greater than F min based on the following equation. NF = F min + 4 R n Γ s Γ o 2 Zo ( 1 + Γ o 2 )(1 Γ s 2 ) Where R n /Z o is the normalized noise resistance, Γ o is the optimum reflection coefficient required to produce F min and Γ s is the reflection coefficient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. Γ o is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower Γ o as compared to narrower gate width devices. Typically for FETs, the higher Γ o usually infers that an impedance much higher than Ω is required for the device to produce F min. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi-q components in order to minimize circuit losses. As an example at 9 MHz, when airwwound coils (Q > 1) are used for matching networks, the loss can still be up to. db which will add directly to the noise figure of the device. Using muiltilayer molded inductors with Qs in the 3 to range results in additional loss over the airwound coil. Losses as high as. db or greater add to the typical. db F min of the device creating an amplifier noise figure of nearly.6 db. A discussion concerning calculated and measured circuit losses and their effect on amplifier noise figure is covered in Avago Application
12 ATF SC-7 4 Lead, High Frequency Nonlinear Model Optimized for.1 6. GHz EQUATION La=.1 nh EQUATION Lb=.1 nh EQUATION Lc=.8 nh EQUATION Ld=.6 nh EQUATION Rb=.1 OH EQUATION Ca=. pf EQUATION Cb=. pf R R=.1 OH LOSSYL L=Lb R=Rb GATE_IN L L=Lc C LOSSYL L=Lb R=Rb C=Ca G D LOSSYL L=Lb R=Rb C=Cb L L=La*. C SOURCE SOURCE L L=La LOSSYL L=Lb R=Rb S LOSSYL L=Lb R=Rb L L=Ld DRAIN_OUT This model can be used as a design tool. It has been tested on MDS for various specifications. However, for more precise and accurate design, please refer to the measured data in this data sheet. For future improvements Avago reserves the right to change these models without prior notice. ATF Die Model * STATZ MESFET MODEL * MODEL = FET IDS model NFET=yes PFET= IDSMOD=3 VTO=.9 BETA= Beta LAMBDA=.9 ALPHA=4. B=.8 TNOM=27 IDSTC= VBI=.7 Gate model DELTA=.2 GSCAP=3 CGS=cgs pf GDCAP=3 GCD=Cgd pf Parasitics RG=1 RD=Rd RS=Rs LG=Lg nh LD=Ld nh LS=Ls nh CDS=Cds pf CRF=.1 RC=Rc Breakdown GSFWD=1 GSREV= GDFWD=1 GDREV= VJR=1 IS=1 na IR=1 na IMAX=.1 XTI= N= EG= Noise FNC=1e+6 R=.17 P=.6 C=.2 Model scal factors (W=FET width in microns) EQUATION Cds=.1 * W/2 EQUATION Beta=.6 * W/2 EQUATION Rd=2/W EQUATION Rs=. * 2/W EQUATION Cgs=.2 * W/2 EQUATION Cgd=.4 * W/2 EQUATION Lg=.3 * 2/W EQUATION Ld=.3 * 2/W EQUATION Ls=.1 * 2/W EQUATION Rc= * 2/W G W=8 µm XX NFETMESFET XX D MODEL=FET S S XX 12
13 Part Number Ordering Information No. of Part Number Devices Container ATF TR1G 3 7 Reel ATF TR2G 1 13 Reel ATF BLKG 1 antistatic bag Package Dimensions SC-7 4L/SOT (.1) BSC HE E 1. (.4) BSC b1 D A A2 b A1 L C DIMENSIONS (mm) SYMBOL E D HE A A2 A1 b b1 c L MIN MAX NOTES: 1. All dimensions are in mm. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to EIAJ SC7.. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. Package surface to be mirror finish. 13
14 Recommended PCB Pad Layout for Avago s SC7 4L/SOT-343 Products Device Orientation REEL CARRIER TAPE USER FEED DIRECTION COVER TAPE.9.3 TOP VIEW 4 mm END VIEW 1..4 Dimensions in mm inches 8 mm 4PX 4PX 4PX 4PX 14
15 Tape Dimensions and Product Orientation For Outline 4T P D P 2 P E C F W t 1 (CARRIER TAPE THICKNESS) D 1 T t (COVER TAPE THICKNESS) 1 MAX. K 1 MAX. A B CAVITY PERFORATION DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER DIAMETER PITCH POSITION A B K P D 1 D P E 2.4 ± ± ±.1 4. ± ±.1 4. ± ±.1.94 ±.4.94 ±.4.47 ±.4.7 ± ±.4.69 ±.4 CARRIER TAPE WIDTH THICKNESS W t 1.4 ± ±.8 COVER TAPE WIDTH TAPE THICKNESS C.4 ±.1 T t.62 ± ±.4 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F P 2 3. ±. 2. ±..138 ±.2.79 ±.2 For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright -28 Avago Technologies. All rights reserved. Obsoletes EN AV2-1283EN - July 23, 28
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