ADVANCES in technology have raised many new issues

Transcription

1 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE SRAM Circuit-Failure Modeling and Reliability Simulation With SPICE Xiaojun Li, Jin Qin, Bing Huang, Xiaohu Zhang, and Joseph B. Bernstein, Senior Member, IEEE Abstract Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circuit reliability modeling, simulation, analysis, and design. The SRAM circuit, implemented with a commercial 0.25-µm technology, consists of functional blocks of 1-bit six-transistor cell, precharge, read/write control, and sense amplifier. The SRAM operation sequence of write 0, read 0, write 1, read 1 was first simulated in SPICE to obtain the terminal voltage and current stress profiles of each transistor. Then, normalized lifetimes of all transistors in terms of each failure mechanism were calculated with the corresponding accelerated lifetime models. These lifetime values were sorted to single out the most damaged transistors. Finally, the selected transistors were substituted with failure equivalent circuit models, and SPICE simulations were performed again to characterize the circuit performance, functionality, and failure behaviors. The simulation shows that the 0.25-µm technology, hot-carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) had significant effects on SRAM-cell stability and voltage-transfer characteristics, while negative bias temperature instability (NBTI) mainly degraded the cell transition speed when the cell state flipped. This illustrative SRAM simulation work proves that, with SPICE and the failure equivalent circuit models, circuit designers can better understand the damage effects of HCI/TDDB/NBTI on the circuit operation, quickly estimate the circuit lifetime, make appropriate performance/reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability. Index Terms Circuit-reliability analysis, failure mechanisms, reliability modeling, simulation program with integrated circuit emphasis (SPICE) simulation, SRAM. I. INTRODUCTION ADVANCES in technology have raised many new issues related to both circuit performance and reliability. Today s extremely complex VLSI chips have been designed to gain maximum performance by stretching the limits of available technologies. These limits are often imposed by reliability concerns. As computer-aided design (CAD) techniques become more mature and sophisticated, most aspects of the modern CMOS VLSI design have been modeled and simulated before committing circuits to silicon. In the CAD tool set, there is Manuscript received August 9, 2005; revised January 5, The authors are with the Microelectronics Reliability Engineering, Center for Reliability Engineering, University of Maryland, College Park, MD USA ( xjli@mail.umd.edu; joey@eng.umd.edu). Digital Object Identifier /TDMR obviously a niche for circuit-reliability simulation, which will help designers predict the device lifetime and failure rate and characterize the circuit failure behaviors. Thus, designers can make appropriate performance and reliability tradeoffs in the initial design phases. Even though many advanced design-for-reliability (DFR) tools have been developed, most of them require a large number of simulation iterations and tedious parameter-testing work, which limit their real-world applications. One way to effectively overcome these drawbacks is to elevate the focus of the reliability analysis from the device wear out process to circuit functionality. Essentially, circuit functional simulation is no more than solving a group of individual device equivalentcircuit-model equations to predict the interactions of all these devices upon external stimuli. Therefore, circuit functionality is solely determined by individual device models. From this perspective, circuit degradation or failures can be viewed as the results that device-level wear out effects express themselves at circuit level by changing the device-model structures. If the change of the device-model structures due to the wear out effects can be correctly modeled with the inclusion of additional circuit elements, and the relations between these additional elements and the time-dependent wear out parameters can be built and calibrated with a simple testing work, then, it is foreseeable that circuit-reliability simulation will become a natural and simple step of the overall circuit functional simulation. Starting from this concept, a new simulation program with integrated circuit emphasis (SPICE) reliability simulation method has been developed, which includes a set of accelerated lifetime models and failure equivalent circuit models for the most common wear out mechanisms including hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit based on their time-variant terminal voltage and current waveforms. Then, failure equivalent circuit models are used to substitute those identified transistors in SPICE simulation to investigate the impact of the device wear out on the circuit functionality. The device wear out effects are lumped into a limited number of failure-equivalent-circuit-model parameters, and circuit functionality and performance degradation are determined by the magnitude of these model parameters. In this new method, it is unnecessary to perform a large number of iterative SPICE simulation processes. Therefore, simulation time is obviously reduced. Moreover, the model parameters that must be extrapolated have been reduced to only a small set of failure-equivalent-circuit elements. Therefore, the reliability testing work becomes less intensive /$ IEEE

2 236 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 Fig. 1. One-bit SRAM structural block diagram. It consists of 1-bit 6-T cell, read/write-control logic, precharge, and output sense amplifier. This paper is an illustrative case study to demonstrate how to apply these new models with SPICE to the circuitreliability simulation, analysis, and improvement. The most common circuit structures used in exemplary reliability simulations are ring oscillator, differential amplifier and SRAM. Compared with the other two circuits, SRAM includes many typical subcircuits such as cross-connected six-transistor (6-T) memory cell, precharge, peripheral control logic, and sense amplifier. The magnitude of MOSFET s wear out mechanisms and their effects on the circuit performance and functionality depend on the types of circuits involved [1]. Moreover, for a typical system-on-chip (SOC) circuit, SRAM occupies more than 40% of the chip area [2]. The ever-increasing integration of SRAM in embedded SOC indicates that the reliability of the modern VLSI systems depends on the reliability of the on-chip memories [3]. Therefore, SRAM was selected in this case study as a vehicle to show the new process of CMOS circuit-failure modeling and reliability simulation with SPICE. II. SRAM CIRCUIT DESIGN AND SIMULATION In order to simplify the circuit structure, reduce the reliability simulation complexity, and emphasize the effects of various failure mechanisms on the circuit operations, we only implemented 1-bit SRAM cell and its operation control functions in the SRAM circuit. The address decoder and the complex timing control subcircuits were intentionally omitted. The SRAM circuit chosen for this consideration includes one 6-T cell, precharge, read/write control, and sense amplifier. The SRAM structural block diagram is shown in Fig. 1. The circuit was implemented with a commercial 0.25-µm technology with gate oxide thickness 5.7 nm and power supply voltage 2.5 V. We intentionally chose the 0.25-µm technology because we wanted to compare our SRAM simulation results with some other similar work in literature, and we could use their experimental results to extrapolate our model parameters and save some device testing work. Before exploring the circuitreliability behaviors under HCI/TDDB/NBTI stresses, we need to briefly explain the structure and function of each SRAM subcircuit. The most important functional block in Fig. 1 is the 1-bit 6-T SRAM cell that is composed of a pair of cross-connected Fig. 2. Schematic of the 1-bit 6-T SRAM cell. Store/Storen represents cell state. WORD line enables the two pass transistors M5 andm6 duringmemory read and write cycles. inverters and two nmosfet pass transistors. The schematic of the SRAM cell is shown in Fig. 2. The transistors M1 M4 form a regenerative structure for storing a single bit 1 or 0 at the node Store depending on the differential voltages of BIT/BITn lines during the write cycles. The WORD line controls the two pass transistors M5 and M6 and enables charging/discharging paths between the nodes Store/Storen and BIT/BITn lines during read/write cycles. The cell-transfer ratio of the pass transistor to pull-down nmosfet widths (i.e., width ratio of M5 tom1, and M6 tom2) is designed to one. The proper value of this ratio is important for cell stability during read operation [2]. The two transmission gates (consisting of M 41 M 44) provide bidirectional paths and connect BIT/BITn lines to write the control circuit during write operation, and to sense the amplifier during read operation. The function of the precharge circuit is precharging BIT and BITn lines to the same level before each read and write operation. In write operations of real circuits, BIT/BITn lines are driven by the DATA line and may not be precharged, but our simplified SRAM circuit has large BIT/BITn swings due to the small bit-line capacitances of 1-bit cell (in comparison, an array of SRAM cells will induce much larger bit-line parasitic capacitances), therefore, the write operation speed will increase if the BIT/BITn lines are precharged. When a reverse state is written into the SRAM cell, the precharge will reduce the BIT/BITn lines swings and increase the operation speed. The schematic of the precharge circuit is shown in Fig. 3. When the PRE signal is high, M21 M25 turn on, equalizing and charging up BIT/BITn lines to the same voltage level V DD 2V t.because the nmosfet threshold voltage of the selected 0.25-µm technology is V t = 0.65 V, the precharge voltage level is approximately set to the middle of V DD, which avoids the full railto-rail signal transitions in subsequent read/write operations, thereby improving the circuit operation speed. The high-speed transitions of the PRE signal on M21 M25 may introduce charge-injection effects on the BIT/BITn lines. These transient charges will increase the voltage overshooting and reduce the cell stability. For high-speed high-volume SRAM circuits in

3 LI et al.: SRAM CIRCUIT-FAILURE MODELING AND RELIABILITY SIMULATION WITH SPICE 237 Fig. 3. Schematic of the precharge circuit. BIT/BITn lines are precharged to the same voltage level before each read and write operation. M26 M29 are included for reducing the transient-charge-injection effects. Fig. 5. Schematic of the sense amplifier. The READ signal controls the operation of the latch amplifier and the connection between the BIT/BITn lines and the output. The latch amplifier magnifies the BIT/BITn line swings to full digital levels. Fig. 6. SRAM SPICE simulation stimuli. PRE exerts before each read/write operation. CD signal enables the transmission gates M41 M42, and WORD signal enables the pass transistors M5 M6 during each read/write operation. The 0 or 1 is available on DATA line during each write operation. Fig. 4. Schematic of the write-control circuit. WRITE signal controls the connectivity between the DATA line and the BITio/BITnio lines. BITio/BITnio are connected to BIT/BITn by the two transmission gates (M41 M44). which the node capacitances on BIT/BITn lines are very large and the swings of BIT/BITn signals are very small, transientcharge injection has more deleterious effect. The inclusion of transistors M 26 M 29 is for suppressing these transientcharge effects and smoothing the BIT/BITn signals during switching. Simulation shows this simplified SRAM circuit with large BIT/BITn swings; failures of these transistors have minor effects on the circuit functionality. Therefore, M 26 M 29 are neglected in the following reliability analysis. The write-control logic circuit is very simple and shown in Fig. 4. The WRITE signal controls the operation of the sand- wiched nmosfet and pmosfet in the two stacked inverters, thereby gate keeping the connection between the DATA line and the SRAM cell. A latch-type sense amplifier rather than a current mirror amplifier is selected due to the small node capacitances and large voltage swings of the BIT/BITn lines. The READ signal applies to M55 and M60 and controls the read operation. If the READ signal is high, the latch amplifier, consisting of M51 M55, will quickly pull the BIT/BITn lines apart in reverse directions to the full digital levels. M 56 M 59 form the output buffer and help generate smooth rail-to-rail output signals. The overall schematic of the sense-amplifier circuit is illustrated in Fig. 5. The function of the SRAM is simulated in SPICE to perform a set of sequential write 0, read 0, write 1, read 1 operations. The duration of each operation cycle is 2 ns, and the circuit is

4 238 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 Fig. 7. SRAM SPICE simulation results. (a) Waveforms of the BIT/BITn signals. (b) SRAM-cell-state signals Store/Storen. (c) Write-operation timing and result. (d) Read-operation timing and result. simulated for 8 ns with an operation speed of 500 MHz. The timing of the input signals is given in Fig. 6. The SPICE simulation results are shown in Fig. 7, in which Fig. 7(a) demonstrates the precharging states and swings of the BIT/BITn signals during read/write operations; Fig. 7(b) indicates the SRAM-cell state stored at the Store/Storen nodes; Fig. 7(c) shows the results of the two write operations; and Fig. 7(d) shows the results of the two read operations. These simulation waveforms illustrate the SRAM-operation process: within 1 2 ns; 0 on the DATA line is written into the SRAM cell, within 3 4 ns; 0 state stored in the SRAM cell is readout to the output data line DATAO, within 5 6 ns, 1 on the DATA line is written into the SRAM cell; and in 7 8 ns, 1 state stored in the SRAM cell is readout to DATAO. These timing relations will be compared later with the reliability simulation results after SRAM experiencing HCI/TDDB/NBTI stresses. III. PREVIEW OF SRAM FAILURE BEHAVIORS SRAM circuit reliability has been a hot topic in literature for many years. Many interesting phenomena of SRAM failure mechanisms and reliability behaviors have been discovered. The main effects of HCI on the device electrical characteristics are threshold-voltage drift and transconductance (g m ) degradation. Pass transistors in an SRAM cell receive more severe damages because of bidirectional HCI stresses. This is proved by the following SPICE simulation. The g m degradation of these pass transistors gradually reduces the driving capability and cell-transfer ratio [1] and increases the access time after a long-term operation [4], [5]. The physical origin of this enhanced HCI damage on pass transistors is explained in [6]. Sense amplifier also suffers from significant HCI stress, which results in an increased input offset voltage [7] and decreased drain output resistance and small-signal voltage gain [8]. TDDB has the most deleterious effects on SRAM-cell stability. There are only four topologically distinct oxide breakdown locations in the SRAM cell shown in Fig. 2: Storeto-Storen, Store-to-V DD, Store-to-gnd, and gate-to-diffusion of pass transistors. Any other possible oxide breakdown locations are completely equivalent to one of these categories [2]. Storeto-Storen breakdown and gate-to-diffusion breakdown of pass transistors reduce the BIT/BITn differential voltage and output swing, whereas breakdowns at Store-to-V DD and Store-to-gnd increase the leakage current at the opposite transistors and degrade the cell stability and static noise margin (SNM) [9]. The leakage currents of µa at the nmosfet source can result in a 50% reduction in SNM [10], [11]. Most SRAM cells become unstable without sufficient SNM [12]. A thorough investigation of the different gate-oxide-breakdown effects on SRAM subcircuits is presented in [13] and [14]. NBTI leads to device mismatches in the SRAM cell and input offset voltages in the sense amplifier. The SNM degradation due to NBTI increases as V DD decreases [15]. Experimental work of an operational amplifier to end-of-life degradation indicates little change in the output characteristics, suggesting that pmosfet NBTI-induced device mismatch is not the fundamental reason for circuit failures [16]. This conclusion is also supported by the following reliability simulation results. IV. DEVICE LIFETIME CALCULATION The details of the accelerated lifetime model for each failure mechanism (HCI/TDDB/NBTI) will be published in separate papers [17], [18]. These lifetime models are recapitulated here for convenience t f = A HCI ( Isub W ( 1 t f = A TDDB A [ t f = A NBTI V 1 β gs ) n exp ( EaHCI κt ) ) 1 ( β 1 F β V a+bt c gs exp exp ( E 1 κt ) + T + d T 2 1 ) 1+2 exp ( E 2 κt ) (1) (2) ] 1 β. (3) If all the model parameters were determined from the device testing work, based on SPICE simulation results, we can calculate the device lifetime for each failure mechanism at any use conditions. However, from the perspective of circuit functionality, the absolute value of the device lifetime is not of primary interest. The main purpose of the lifetime calculation is to identify the weakest and the most damaged devices. We only need to calculate the relative lifetime (i.e., normalized lifetime) for each device by lumping all common model parameters into a

5 LI et al.: SRAM CIRCUIT-FAILURE MODELING AND RELIABILITY SIMULATION WITH SPICE 239 single factor. This means that, in our SRAM simulation, we do not need to predict the absolute lifetime value of each transistor for the same mechanism. We also do not compare the relative lifetimes of the different mechanisms because we assumed that there is no single dominant mechanism in circuit (i.e., equal contribution assumption). This assumption is based on the fact that as the knowledge of the device failure mechanisms improves, electronic components are designed at the edge of reasonable life under tightly controlled specifications, and, if any failure mechanism is more significant than others, specific design and manufacturing techniques will be developed to suppress this dominant failure. When no one failure mechanism dominates, all mechanisms are equally likely and the resulting failure distributions resemble constant rate processes. Based on the above concepts, we can rewrite (1) (3) to the following simplified forms: ( ) n Isub t f = τ 1 W (4) ( ) 1 1 β t f = τ 2 V a+bt gs W (5) [ ] t f = τ 3 V 1 1 β gs E 1 β exp( E 2 /κt ) (6) where τ 1 τ 3 are the lumped factors and defined as the benchmarks for normalized lifetimes, W is the channel width, and E 1 is a process-dependent constant. In deriving (4) (6), for simplicity, we have not differentiated the device junction temperature and the ambient temperature. The temperature effects of various failure mechanisms are discussed in [19], and the method to model the device junction temperature in terms of device power dissipation and ambient temperature is given in [3]. In a normalized lifetime-calculation process, it is unnecessary to characterize τ 1 τ 3 factors because they are common to all devices in the same circuit. This reduces the number of model parameters and obviously simplifies the parameter testing and extraction work. In (4) (6), I sub, V gs, and E 2 can be predicted from SPICE simulation. After obtaining the reduced set of model parameters necessary to (4) (6), we can easily calculate the device normalized lifetimes for each failure mechanism. Because this SRAM operation is in a regular pattern, the stress waveforms of each transistor are also in regular patterns. We divided the period of one operation sequence into small steps according to the waveform patterns. During each small step, we treated the stress profile as quasi-static, and integrated the stress contribution from each step to the whole period. Finally, we extended one period to the full simulation time. This quasi-static method becomes time consuming for complex circuits operating in irregular patterns. Some dynamic integration algorithms may be required to improve both accuracy and speed for more complex circuits. The lifetime results are shown in Fig. 8, in which the horizontal axis denotes transistor s index (e.g., 1 represents M1 ), and the vertical axis denotes lifetime value normalized to τ 1 τ 3, respectively (e. g., for HCI: t f (M1) =4.2893τ 1 ). Fig. 8. Device lifetime-calculation results for the three failure mechanisms (a) HCI, (b) TDDB, and (c) NBTI. The horizontal axis denotes device s index, and the vertical axis denotes the lifetime value normalized to τ 1 τ 3, respectively. Compared with other devices, M33, M34, M37, M41, and M43 have very large NBTI lifetimes. In order to show details of other devices relatively smaller lifetime values, normalized lifetime values of these transistors are truncated in Fig. 8(c). The following trends can be easily observed from inspecting Fig. 8. For HCI effect, pass transistors generally experience more damages due to bidirectional stresses and more frequent dynamic-switching operations (shown by M 5, M 6, M21, M42, M44); nmosfets in inverters suffer from less HCI stress (shown by M35, M56, M63); in stacked inverters, nmosfets on the top receive more HCI damage (shown by comparisons of M31 to M32 and M35 to M36, respectively); the sense amplifier is sensitive to HCI because distinct HCI damages on M 51 and M 52 lead to increased device mismatches and input offset voltages. For TDDB effect, if assuming the same accelerated lifetime equations and similar model fitting parameters for both nmosfet and pmosfet, pmosfet is easier to suffer from TDDB due to its relatively larger channel area, and area scaling has a significant effect on the device lifetimes (shown by M62, M64 whose channel widths are very large: 12 µm). For NBTI effect, pmosfets in latch structure receive more imbalanced NBTI damages, which also leads to increased device mismatches and input offset voltages (shown by M3, M4 and M53, M54). It is easy to identify the most damaged transistors for each failure mechanism from Fig. 8. For HCI, M5, M6, M52, and

6 240 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 In the above process, we intentionally removed some candidates from the weakest device lists because we wanted to focus on the most important transistors and effects and to reduce the complexity of the reliability analysis. In real applications, with the intention of automated and quick circuit simulation for evaluation of reliability, designers can save this kind of human interference and let the simulator include as many candidates as they want by balancing time and accuracy. In summary, the selected most damaged devices for each failure mechanism are: HCI-M5, M6, M52, TDDB-M3, M31, M38, M53, and NBTI-M3, M38, M53. These transistors will be substituted with corresponding failure equivalent circuit models in the following SPICE simulation. V. S PICE RELIABILITY SIMULATION WITH FAILURE EQUIVALENT CIRCUIT MODELS Fig. 9. Comparison of transition delay of M58 before and after the inverter sizing. Proper sizing significantly reduces the dynamic-switching delay, thereby suppressing the HCI effect. W n = 0.6 µm before sizing, and W n = 1.8 µm after sizing. M58 are the most damaged transistors. M58 has the shortest lifetime, however, it can be excluded after a careful analysis. In the initial schematic, the two stages of inverters after the sense amplifier were designed with the sizing ratio of one. If we scale up the channel widths of M58 and M59 and increase the sizing ratio to three, the lifetime of M58 increases from τ 1 to τ 1. The reason for this significant improvement is the reduction in inverter transition delay after proper sizing of the inverter chain, as shown in Fig. 9. Proper inverter sizing improves both transition speed and device lifetime with the penalties of larger chip area and loading to neighboring gates, therefore, circuit designers need to perform detailed lifetime calculation and functional simulation to make appropriate tradeoffs. For TDDB, M3, M31, M38, M53, M62, and M64 are the most damaged transistors. M62 and M64 are pmosfets in the write-control logic subcircuit. Their channel widths were tentatively designed very large to quickly generate inverse signals of WRITE and DATA. However, we found that their widths could be properly scaled down to improve lifetimes. We have tested the differences in performance if we scaled the channel widths of M62 and M64. There was no obvious impact if we followed the inverter sizing rules by taking into account the loading of the next stage. Therefore, we do not include them in the weakest device list. M3 is included because it is within the SRAM cell and its oxide breakdown has a significant effect on the SRAM operation. All transistors in the precharge circuit (M 21 M 29) are not selected because during all operation periods, their gate-to-source/drain voltages are very small. For NBTI, M3, M38, and M53 are selected as the most damaged transistors. Although the lifetimes of M 62, M 64, M57, and M59 are comparable to those of being selected, based on the same reason given above, we do not include them in the weakest device list. The detailed model equations and testing methods to determine the failure equivalent-circuit-model parameters for each mechanism have been presented in our precious papers. Most of these model parameters are time dependent. Therefore, SPICE simulation with these failure equivalent circuit models has to be performed several times to pinpoint the time at which the circuit function fails. The most effective way to find this failure time is by a three-step progressive process: first, only consider HCI failure electrical models and find the circuit HCI lifetime T a ; then, include TDDB electrical-model simulation circuit operation at times shorter than T a and find the corresponding circuit HCI + TDDB failure lifetime T b (T b T a ); finally, take into account all failure electrical models and find the circuit-failure lifetime T c (T c T b ) at which the circuit cannot maintain correct operations. In this step-by-step process, circuit s failure behaviors due to each failure mechanism can be efficiently characterized. The SRAM reliability analysis was performed in this three-step process and presented in details in the following sections. A. HCI There is only one parameter in HCI failure equivalent circuit model: R d, which characterizes drain current reduction due to mobility degradation resulting from HCI-induced interface charge and oxide charge. R d values of M5, M6, M52 at different stress times are plotted in Fig. 10. These HCI-induced series parasitic resistances are not in simple logarithmic relation to stress time t because the horizontal axis is not drawn in linear scale. M 5 and M 6 receive bidirectional HCI stresses, consequently, each of them has two resistances R d1 and R d2 associated with drain and source, respectively. The SRAM circuit with these HCI-induced R d elements was simulated at different stress times to check its functionality. Fig. 11 shows the waveforms of the SRAM-cell state (i.e., the Store signal) and the output state (i.e., the DATAO signal) after different stress times. It indicates that the SRAM circuit operated correctly until 0.8 year, and failed at one year, at which the Store signal did not switch as expected during the write 1 cycle. The gradual degradation of the Store signal is clearly shown in Fig. 11. The quicker corruption of the Store

7 LI et al.: SRAM CIRCUIT-FAILURE MODELING AND RELIABILITY SIMULATION WITH SPICE 241 Fig. 12. Simulated waveforms of the SRAM Store/Storen signals and BIT/BITn signals before and after circuit failure. The Store/Storen signals did not flip due to the degradation in BIT/BITn signals when a reverse value was written to the SRAM cell. Fig. 10. R d values of M5, M6, and M52 at different stress times. The unit of horizontal axis is time in years, the vertical axis is in logarithmic scale and in unit ohm. Fig. 11. Simulated waveforms of the SRAM-cell Store signal and the output DATAO signal after different stress times. At t = 1 year, the Store signal did not jump to high as expected during the write 1 cycle indicating failure of the SRAM cell. signal than that of the DATAO implies that malfunction of this SRAM circuit mainly resulted from HCI damage of M5 and M6, not of M52. This verifies other researchers work on the Fig. 13. Simulated waveforms of the SRAM-cell Store signal and the output DATAO signal at different HCI + TDDB stress times. At t = 0.6 year, Store signal did not jump to high during the write 1 cycle indicating failure of the SRAM cell. relation between pass transistor s HCI degradation and SRAMcell stability. A closer look at the BIT/BITn and Store/Storen waveforms before and after SRAM-cell failure reveals more reliability information. Fig. 12 compares and shows how these signals corrupt. It is clearly shown that the addition and increase of HCI-induced series resistances in M5 and M6 degraded the BIT/BITn signals and reduced the cell-transfer ratio. As a result, the high BIT line signal at write 1 cycle could not be effectively written into the SRAM cell. The Store/Storen signals could not switch when a reverse value was written to the SRAM cell.

8 242 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 From the above SPICE simulation with HCI failure electrical models, the SRAM circuit HCI lifetime was predicted to 0.9 year. If we consider the effect of the duty cycle and assume that the average access frequency of the SRAM is one full write 0, read 0, write 1, read 1 operation per 1 µs at normal use condition, the predicted 0.9 year corresponds to a circuit HCI lifetime of years. B. HCI + TDDB The second step in the SRAM circuit-reliability simulation was the inclusion of both TDDB and HCI failure equivalent circuit models. Some experimental work has proved that the effect of oxide breakdown is insensitive to the breakdown locations if the breakdown path is away from the drain and source edges. Based on this phenomenon, we can simplify the application of our TDDB model in reliability simulation: We only need to consider the gate-to-channel breakdown and can simply set the breakdown location to the middle point of the channel. As a result, only one parameter I ox needed to be characterized for each identified TDDB damaged transistor. The values of I ox were calculated as: I ox (M3) = µa, I ox (M31) = µa, I ox (M38) = µa, and I ox (M53) = µa. In our TDDB model, for now, I ox is treated as a fixed value. This is a reasonable simplification for our purpose, because TDDB is different from HCI and NBTI in that hard oxide breakdown is not a progressive process before breakdown. When breakdown happens, the oxide leakage I ox will not assume a constant value, but what we care most here is the circuit behaviors during the short time span right after the breakdown event. In that relatively short time period, we can treat I ox as a constant leakage current. There are some models in literature capable of characterizing the progressive increase in I ox after the initial breakdown, but implementation of them in the simulators requires much more effort and work. The complexity of time evolution in TDDB makes its failure modeling an arduous work. HCI and NBTI are gradual wear out phenomena, but TDDB shows no obvious degradation until the initial breakdown event, after which the gate oxide leakage gradually increases. The statistically distributed breakdown time (Weibull distribution) further complicates its modeling process. Until now, there is no TDDB circuit model capable of relating the stress time t to breakdown related model elements. As a result, it is difficult to set the time factor in TDDB circuit models and clearly predict when the breakdown happens from simulation. In our work, we used a worst case simulation to address this problem. In the future work, we will add some SPICE circuit element (e.g., switch) in the TDDB model whose function is controlled by the statistics of breakdown time. This switch will disable the I ox before the breakdown happens. The SPICE simulation results when taking into account both HCI and TDDB effects are illustrated in Fig. 13. The SRAM circuit survived until 0.4 year but failed to function at 0.6 year. The addition of TDDB circuit models significantly reduced the circuit lifetime. Fig. 14 shows the interaction between the HCI effect and the TDDB effect, in which the BIT/BITn and Store/Storen waveforms before and after circuit failure (at 0.4 year and 0.6 year, respectively) are plotted. At 0.6 year, the Fig. 14. Simulated waveforms of the SRAM Store/Store signals and the BIT/BITn signals before and after circuit failure. corruption of the Store/Storen signals and the degradation of the BIT/BITn signals during the final write 1, read 1 cycles are very similar to those at one year in Fig. 12, in which only the HCI effect is considered. Moreover, when we disabled the TDDB effect on M3 at 0.6 year, the circuit function was restored, and the waveforms without TDDB at 0.6 year were quite similar to the waveforms with TDDB at 0.4 year. These similarities imply that the gate-to-channel breakdown of TDDB accelerates the SRAM-cell instability but it does not introduce a new failure behavior at circuit level. This result is not observed by other researchers because most work on SRAM-cell instability analysis did not combine HCI and TDDB effects together, and a worst case gate-to-diffusion breakdown mode rather than more frequent and less severe gate-to-channel breakdown mode of TDDB was included in those simulation works. Besides TDDB of M3 on circuit operation, we also investigated the TDDB effects of M31, M38, and M53 on the circuit performance. The simulation proved that breakdowns of M 31 and M 38 (both belong to inverters in write-control subcircuit) had minor effects on SRAM operation, but breakdown of M53 had a significant effect. Fig. 15 shows the TDDB effect of M 53 on the sense-amplifier input signals. The breakdown in M 53 provided an additional current path between the senseamplifier input and V DD and tended to pull up this input signal. The erratic jumps in the amplifier input signal shown in Fig. 15 reduced the amplifier output stability. C. HCI + TDDB + NBTI The last step was the inclusion of NBTI failure equivalent circuit models. M 3, M 38, and M 53, being identified for suffering most NBTI damage, also received most of the TDDB damage. Therefore, we had to properly combine the NBTI and

9 LI et al.: SRAM CIRCUIT-FAILURE MODELING AND RELIABILITY SIMULATION WITH SPICE 243 Fig. 15. TDDB effect of M53 on the sense-amplifier output stability. The breakdown in M53 provided the additional current path between BITnio and V DD and tended to pull up the BITnio when it was at low level in read 0 and write 1 cycles. TDDB electrical models together for these pmosfets. If we simply added all NBTI failure-circuit-model elements into the TDDB model, the oxide-breakdown effect would be overestimated, which results in suppressing or overshooting of SRAMcell-state signals (i.e., Sote/Storen), and unexpected jumps of sense-amplifier input signals. These negative phenomena were observed in the simulation results. The correct TDDB + NBTI failure electrical model for a pmosfet is illustrated in Fig. 16. With the previous HCI + TDDB simulation results, we only need to calculate R G for each of M3, M38, and M53 at time 0.4 year. Their values are R G (M3) =6.6 kω, R G (M38) = Ω, and R G (M53) =3.3 kω. The simulation indicates that NBTI had relatively weak effects on the SRAM-cell stability and functionality. Its most obvious influence observed from the simulation was that NBTI degraded the SRAM-cell transition speed. This effect is shown in Fig. 17, where switching of the Store/Storen signals slowed down when the NBTI model was set in. The simulation also shows that NBTI had minor effects on the functionality of the latch-type sense amplifier. The degradation in the input signals was very small. SPICE DC voltage-transfer function simulation along the path from the BITn line to the Storen line encompassed all of the three failure mechanisms (HCI of M6, TDDB and NBTI of M 3). Therefore, degradation in voltage-transfer curves (VTC) for BITn-to-Storen at different combinations of these failure mechanisms can reflect their individual influence on the SRAM-cell stability. These VTC curves, plotted in Fig. 18, indicate that HCI and TDDB have reverse effects on VTC drift, while NBTI has no observable effects. SNM is the most important factor in SRAM circuit-reliability analysis. Based on the SPICE DC transfer analysis, the SNM Fig. 16. TDDB + NBTI failure equivalent circuit model for a pmosfet. R G and I ox account for threshold-voltage degradation due to NBTI. I ox and the two split pmosfets represent TDDB damage. R D and R S characterize the resistances in drain and source extensions. They are excluded in this SRAM case study in order to simplify the simulation work. butterfly plots for various combinations of the failure mechanisms are generated in Fig. 19. Butterfly curves are usually plotted with WORD-line high and BIT/BITn precharged to correspond to the normal read operation. However, in plotting Fig. 19, we did not bias the SRAM cell in such state and therefore not include the HCI damaged pass transistors of the cell. The reason for this consideration is due to the fact that the TDDB and HCI have reverse effects on VTC. The inclusion of HCI will neutralize the skewness of the butterfly plots and make it hard to identify the impacts of different mechanisms. The smaller size of the two maximized embedded squares in the butterfly plots represents the magnitude of SNM. In Fig. 19, Fig. 19(a) represents the failure-free operation, Fig. 19(b) shows the SNM degradation due to TDDB effect, Fig. 19(c) shows the combined effect of TDDB + NBTI on SNM, and Fig. 19(d) is the combination of plots Fig. 19(a) (c) for the sake of easy comparison. These curves were obtained by setting the failure-circuit-model parameters at stress time 0.4 years. It is indicated from these butterfly plots that the SRAM-cell noise margin shrinks due to TDDB and NBTI stresses, and TDDB has the dominant effect. The gate-to-channel breakdown of M 3 leads to a symmetrical shrinkage of the two embedded squares, which is distinct from the case of gate-to-diffusion breakdowns presented in [10] and [11], where asymmetrical scales of the sizes of the two embedded squares resulted from the p-source breakdown. It is expected that the gate-to-diffusion breakdown model of TDDB would accelerate the SNM degradation. At 0.4 year, even though SNM was significantly reduced, the two transfer curves still crossed and formed two stable states. Therefore, SRAM-cell function was maintained. The SRAM circuit survived to 0.4 year but failed at 0.6 year. If the same duty cycle and usage profile are assumed as in Section V-A, the HCI + TDDB + NBTI lifetime of this SRAM circuit under normal use condition is about 62.5 years.

10 244 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 Fig. 17. NBTI effects on SRAM-cell transition speed. The switching speed of the SRAM-cell Store/Storen signals degraded when the NBTI damage on M3 was considered. Fig. 18. VTC of BITn to Storen for different combinations of failure mechanisms. From left to right, the curves represent the effects of TDDB, no damage, HCI + TDDB + NBTI, HCI, and HCI + NBTI, respectively. NBTI has a negligible effect on the SRAM-cell stability. VI. RELIABILITY DESIGN TECHNIQUES After exploring the circuit-degradation effects and reliability behaviors with failure equivalent circuit models, designers need to make design iterations to improve the circuit lifetime if the initial design falls short of reliability specifications. Traditionally, this is an arduous work due to the lack of systematic and convenient reliability-analysis method to help pinpoint the reliability weak spots and characterize the circuit degradation in performance and functionality. With the new models and SPICE simulation method introduced in this paper, designers can perform a quick reliability analysis and gain knowledge on the circuit failure behaviors. Equipped with this reliability knowledge, they can develop their own expertise in reliability improvement through proper design iterations. In literature, there are some reliability design techniques available for suppressing different failure mechanisms. Reliability design techniques for HCI including transistor sizing, gate topology transform, and input-signal scheduling are presented in [20]. Some design improvement concept for TDDB Fig. 19. Butterfly plots for various failure mechanisms. (a) Denotes the nodamage operation; (b) SNM degradation due to TDDB; (c) combined effect of TDDB + NBTI; and (d) combination of the previous three plots. The difference in (b) and (c) is very small indicating that NBTI is not a dominant effect. is introduced in [21]. A design technique to reduce the gateto-source voltage during static state operation and improve the NBTI reliability is introduced in [22]. Even though some progresses have been achieved in DFR, design techniques for TDDB and NBTI have not been thoroughly investigated. With better understanding of circuit-reliability behaviors from the new SPICE simulation method, circuit designer can develop their own guidelines and expertise in this area. VII. CONCLUSION In this paper, a simple SRAM circuit is designed and simulated with failure equivalent circuit models to illustrate how to apply this new SPICE simulation method to circuit-reliability prediction and analysis. Simulation shows that HCI and TDDB have significant effects on the SRAM-cell stability and voltage-transfer characteristics, while NBTI mainly degrades the cell transition speed when the cell-state flips. This case study of SRAM-reliability simulation work proves that with

11 LI et al.: SRAM CIRCUIT-FAILURE MODELING AND RELIABILITY SIMULATION WITH SPICE 245 the proper accelerated lifetime models and failure equivalent circuit models in SPICE, circuit designers will obtain an indepth understanding of the circuit failure behaviors and the damage effects of HCI/TDDB/NBTI on the circuit operations. Equipped with this knowledge, they can quickly estimate the circuit lifetime, make appropriate performance and reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability. ACKNOWLEDGMENT The authors would like to thank the reviewers of this paper for their insightful comments and practical suggestions. By responding to their questions and concerns, the authors have greatly improved both the quality of this paper and the progress of the research projects. REFERENCES [1] M. Fukuma, H. Furuta, and M. Takada, Memory LSI reliability, Proc. IEEE, vol. 81, no. 5, pp , May [2] R. Rodriguez, R. V. Joshi, J. H. Stathis, and C. T. Chuang, Oxide breakdown model and its impact on SRAM cell functionality, in Proc. IEEE SISPAD, Sep. 2003, pp [3] X. Li, J. D. Walter, and J. B. Bernstein, Simulating and improving microelectronic device reliability by scaling voltage and temperature, in Proc. IEEE 6th ISQED, Mar. 2005, pp [4]W.J.Hsu,B.J.Sheu,S.M.Gowda,andC.G.Hwang, Advanced integrated-circuit reliability simulation including dynamic stress effects, IEEE J. Solid State Circuits, vol. 27, no. 3, pp , Mar [5] B.-K. Liew and A. R. Alvarez, Circuit reliability of hot electron induced degradation in high speed CMOS SRAM, in Proc. IEEE Custom Integr. Circuits Conf., 1993, pp [6] D. Goguenheim and A. Bravaix, Hot-carrier reliability in n-mosfets used as pass-transistors, Microelectron. Reliab., vol. 38, no. 4, pp , Apr [7] S. Z. Mohamedi, V. H. Chan, J. T. Park, F. Nouri, B. W. Scharf, and J. E. Chung, Hot-electron-induced input offset voltage degradation in CMOS differential amplifiers, in Proc. IEEE 30th Int. Annu. Reliab. Phys. Symp., 1992, pp [8] J. E. Chung, K. N. Quader, C. G. Sodini, P.-K. Ko, and C. Hu, The effects of hot-electron degradation on analog MOSFET performance, in IEDM Tech. Dig., Dec. 1990, pp [9] J. H. Stathis, R. Rodriguez, and B. P. Linder, Circuit implications of gate oxide breakdown, Microelectron. Reliab., vol. 43, no. 8, pp , Aug [10] R. Rodriguez, J. H. Stathis, B. P. Linder, S. Kowalczyk, C. T. Chuang, R. V. Joshi, G. Northrop, K. Bernstein, A. J. Bhavnagarwala, and S. Lombardo, The impact of gate-oxide breakdown on SRAM stability, IEEE Electron Device Lett., vol. 23, no. 9, pp , Sep [11], Analysis of the effect of the gate oxide breakdown on SRAM stability, Microelectron. Reliab., vol. 42, no. 9 11, pp , Sep. Nov [12] S. Ikeda, Y. Yoshida, K. Ishibashi, and Y. Mitsui, Failure analysis of 6T SRAM on low-voltage and high-frequency operation, IEEE Trans. Electron Devices, vol. 50, no. 5, pp , May [13] J. Segura and A. Rubio, A detailed analysis of CMOS SRAM s with gate oxide short defects, IEEE J. Solid State Circuits, vol. 32, no. 10, pp , Oct [14], GOS defects in SRAM: Fault modeling and testing possibilities, in Proc. Rec. IEEE Int. Workshop Memory Technol., Des. and Testing, Aug. 1994, pp [15] V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, Impact of negative bias temperature instability on digital circuit reliability, Microelectron. Reliab., vol. 45, no. 1, pp , Jan [16] M. Agostinelli, S. Lau, S. Pae, and P. Marzolf, PMOS NBTI-induced circuit mismatch in advanced technologies, in Proc. IEEE Int. Reliab. Phys. Symp., 2004, pp [17] X. Li et al., A new SPICE reliability simulation method for deep submicron CMOS VLSI circuits, IEEE Trans. Device Mater. Reliab., to be published. [18] X. Li and J. Bernstein, Advanced semiconductor wearout mechanisms lifetime and spice equivalent circuit modeling, IEEE Trans. Device Mater. Reliab., to be published. [19] C. Yao, J. Tzou, R. Cheung, and H. Chan, Temperature dependence of CMOS device reliability, in Proc. IEEE IRPS, 1986, pp [20] Y. Leblebici and S. M. Kang, Hot-Carrier Reliability of MOS VLSI Circuits. Norwell, MA: Kluwer, 1993, p. 61. [21] B. Kaczer, R. Degraeve, E. Augendre, M. Jurczak, and G. Groeseneken, Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns, in Proc. 33rd ESSDERC, Sep. 2003, pp [22] R. Thewes, R. Brederlow, C. Schlunder, P. Wieczorek, B. Ankele, A. Hesener, L. Holz, S. Kessek, and W. Weber, MOS transistor reliability under analog operation, Microelectron. Reliab., vol. 40, no. 8 10, pp , Aug. Oct Xiaojun Li received the B.S. degree in physics and the M.S. degree in semiconductor device and physics from Wuhan University, Wuhan, China, in 1995 and 1998, respectively, and the M.S. and Ph.D. degrees in microelectronics reliability engineering from the University of Maryland, College Park, in 2004 and 2005, respectively. His research work focused on deep submicrometer CMOS VLSI circuit reliability modeling, simulation, and design. Since 2005, He has been a Quality Reliability Engineer with the Flash Memory Group, Intel Corporation, CA. His work includes CMOS circuit failure modeling and Flash reliability simulation and prediction tools development. Jin Qin received the M.S. degree in reliability engineering from the University of Maryland at College Park in He is currently working toward a Ph.D. degree in reliability engineering at the same university. His research topics include reliability testing, reliability data analysis, and microelectronic-system reliability estimation. Bing Huang received the B.S. degree in mining engineering from the University of Science and Technology of Beijing, Beijing, China, in 1977, and the M.S. degree in nuclear engineering from Tsinghua University, Beijing, in He is currently working toward the Ph.D. degree in reliability engineering with the University of Maryland, College Park. He joined the Center for Reliability Engineering, University of Maryland as a Research Assistant responsible for SRAM accelerated testing, in Since 2004, he worked for a NASA project to study the impact of microprocessor hardware faults on software reliability. His research interests include microelectronic device reliability modeling and testing, and microprocessor fault modeling and simulation.

12 246 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 2, JUNE 2006 Xiaohu Zhang received the M.S. and B.S. degrees in mechanical engineering from Beijing Institute of Technology, Beijing, China, in 1995 and 1998, respectively. He is currently working toward the Ph.D. degree in microelectronic reliability program with the University of Maryland, College Park. His research interests include power devices, microelectronic device modeling, and reliability analysis. Joseph B. Bernstein (S 81 M 89 SM 01) received the Ph.D. degree in electrical engineering from Massachusetts Institute of Technology (MIT), Cambridge, in He is an Associate Professor of reliability engineering in the Department of Mechanical Engineering at the University of Maryland, College Park, with appointments in electrical engineering and the Institute for Research in Electronics and Applied Physics. He is actively involved in several areas of microelectronics reliability and physics of failure research including power device reliability, gate oxide integrity, radiation effects, microelectromechanical systems (MEMS), and laser programmable metal interconnect. He supervises the laboratory for laser processing of microelectronic devices and is the Head of the microelectronics device reliability program. His research areas include thermal, mechanical, and electrical interactions of failure mechanisms of ultralarge-scale-integration (ULSI) devices. He also works extensively with the Semiconductor Industry on projects relating to laser processing for defect avoidance, programmable interconnect, and repair in microelectronic circuits and packaging. He was selected as a Fulbright Senior Researcher/Lecturer and set up a joint center for reliable electronics at Tel Aviv University, Israel.