As Semiconductor Devices Shrink so do their Reliability and Lifetimes

Transcription

1 As Semiconductor Devices Shrink so do their Reliability and Lifetimes National Software and Airborne Electronic Hardware Standardization Conference August Denver, CO Lloyd Condra, Boeing Gary Horan, FAA Bill Scofield, Boeing

2 Outline Background As semiconductor devices shrink, so do their reliability and lifetimes What we have done about it AVSI research results What we have yet to do Tool development Implementation

3 What Does COTS Mean? Part Sub-assembly (module) Equipment Modified Standard Consumer Commercial Industrial Mil-Aero System 32 Flavors of COTS (Baskin Robbins only has 31)

4 Our Challenge Our COTS supply chain is a Complex Adaptive System that evolves according to forces beyond our control We develop processes, methods, and standards that allow our customers to..design, produce, certify, and support products using parts and materials from Complex Adaptive Systems.

5 The COTS Semiconductor Industry is a Complex Adaptive System Feature size, nm Voltage Scaling Driving factors: Cost Speed Size Time-to-market Cu Conductors Incidental factors: Reliability Configuration continuity What aerospace needs Low-D k Dielectrics Model-based Design A feature is a line width, gate length, etc. of a CMOS gate.

6 Semiconductor Wearout Mean Service life, yrs. 10 Mil/Aero lifetimes 1.0 Computer/cell phone lifetimes 0.1 Technology 0.5 mm nm 65 nm 35 nm 1995 mm Year produced 1.0μ Most microcircuits are designed for 3-10 year service life Strong motivation to limit insight into longterm reliability Service Life (years) Margin Source: E. Snyder (Sandia), IRPS, 2002) 0.35μ 0.18μ 0.1μ Typical service life goal (10 yrs.)

7 Predictions Confirmed by Experience* Wearout failures (Hot Carrier Injection) in 90nm ASIC devices Telecom OEM: 10% failure within 4 years Process Monitoring OEM: 20% failure within 3 years Major manufacturer of graphic processor units (GPU) limits maximum junction temperature to 80ºC in order to meet 5-year lifetime requirement *Source: DfR Solutions

8 Predictions Confirmed by Testing AVSI #17 Results 700 FIT 90 nm: ~ FIT 0.25 μm: ~20-50 FIT Current state-of-the-art is 45 nm Avionics Inservice Data Test system at Tower semiconductor

9 What We Have Done About Early Semiconductor Wearout Aerospace Vehicle Systems Institute Project #17 Participants: Boeing, Honeywell, Goodrich, GE, Rockwell Collins, DoD, FAA, NASA Time span: Subcontractor: Dr. Joseph Bernstein, U of MD Results Literature search failure mechanisms, models, parameters Confirmed models by testing Alpha version of FaRBS software Avionics system design handbook

10 Predictions Confirmed by Testing AVSI #17 Results 1.E+03 Acceptable for Commercial Applications FIT 1.E+02 Required for Avionics 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Time (equivalent hours) Early Wearout Confirmed!!!

11 Wearout Mechanisms Electromigration Source Conducting Gate channel oxide Gate Drain Trench isolation Drain Gate oxide Gate Conducting channel Source P+ P+ N+ N+ P-well N-substrate Oxide breakdown Hot carrier injection (HCI) Negative bias temperature instability (NBTI) Voltage stresses TDDB NBTI HCI EM V γ TDDB g γ E atddb exp( ) kt V E anbti exp( ) exp( ) NBTI g kt γ V HCD ahcd exp( ) exp( ) kt n J d E E aem exp( ) kt Current stresses

12 FaRBS Reliability Software BQR Reliability User Supplied

13 90 nm NBTI Degradation Reliability Prediction with FaRBS ~0.98 Reliability, R(t)=1-F(t) β=1 Reliability vs Time Fast Slow Typ ~2% failure in 2-4 years ~3 Time, (yr) yrs.

14 Example FaRBS Outputs Reliability and Failure Rate Estimates 36Mb SRAM Reliability MB SRAM 1GB DRAM 0.99 Board failure rate MB SRAM 90 nm technology 1.2 volts, 70ºC Time (years) FIT Time (years)

15 Example FaRBS Output Board failure rate Board with one 36Mb SRAM and one 1GB DRAM FIT FIT = 1 failure/10 9 hrs Time (years)

16 Effect of Feature Size β = 2.1 β = 4.0 β = 7.3 β = 1.6 β = 1.3 Source: Wu, E.Y., and R.-P. Vollertson, On the Weibull Shape Factor of Intrinsic Breakdown of Dielectric Films and Its Accurate Experimental Determination Part I: Theory, Methodology, Experimental Techniques, IEEE Transactions on Electronic Devices, vol. 49, no. 12, December Pp

17 Effect of Voltage on TDDB 256M DRAM, 78nm CMOS process Gate oxide thickness approximately 5.5nm Operating voltage 1.5V. HTOL at 5.0V/125C Exponential voltage acceleration 1 with γ = l ( l (1 F)) V 7.50V 7.25V 7.00V BetaW= Time-to-fail (s)

18 What We Have Yet To Do AVSI Project #71 Commercial version of FaRBS software (DfR Solutions) Verify software by test data Beta test FaRBS software tool on selected Boeing systems Update with future technology data, models, and parameters Invite participation by others Provide inputs to aerospace design and reliability documents DO-254 MIL-HDBK-217

19 Commercial FaRBS Inputs Make AVSI 17 results user-friendly Graphical user interface (GUI) designed to interact with a wide range of users, e.g., design engineers, reliability engineers, etc. Requires a minimal set of inputs Manufacturer Manufacturer part number Duty cycle Use environment (temperature) Assumptions can be modified by expert users Operation at rated voltage Only mfr.-specified thermal solutions (no uprating) International Technology Roadmap for Semiconductors (ITRS) models and parameters Applicable to <130nm technology Default and package failure rates from handbooks (-217, Telcordia) or part manufacturer

20 Commercial FaRBS Outputs Make AVSI 17 results user-friendly Failure rate as a function of time Results can be exported in a.doc or.xls /.csv format Expert user will be able to extract failure rates for each failure mechanism Validation link will provide details on approach and experimental results

21 Implementation Update System Reliability and Certification Documents Hardware Reliability Prediction MIL-HDBK-217 Hardware Design Assurance RTCA DO-254 Software Design Assurance RTCA DO-178B System Functional Hazard Assessment System FMEA System FTA System Certification Analysis Updates needed