Website: vlsicad.ucsd.edu/ courses/ ece260bw05. ECE 260B CSE 241A Power Consumption 1

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1 ECE260B CSE241A Winter 2005 Power Consumption Website: / courses/ ece260bw05 ECE 260B CSE 241A Power Consumption 1

2 VLSI Design Metrics Area / cost Performance Power consumption Reliability Manufacturing yield Signal integrity (e.g., crosstalk, supply voltage drop, etc.) Logic correctness / acceptable performance variation under process, operating condition variations Expected lifetime (due to eletromigration, soft-error, peak current, etc.) Figure courtesy, D. Singh ECE 260B CSE 241A Power Consumption 2

3 Power Dissipation Lead Microprocessor s power continues to increase 100 Power (Watts) P6 Pentium proc Year Power delivery and dissipation will be prohibitive(?) ECE 260B CSE 241A Power Consumption 3 Courtesy, Intel

4 Power Density Power Density (W/ cm2) Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp(?) ECE 260B CSE 241A Power Consumption 4 Courtesy, Intel

5 Low Power Design Drivers Consumer products Affects expected battery lifetime Slow development of battery technology ( Watt-hrs/ Kg) Low power reducing energy consumption High performance designs Increasingly expensive packaging and cooling strategies - Size, weight, heat sinks, - Air, liquid cooling mechanism Supply voltage drop Temperature - Every 10 O C increase in operating temperature roughly doubles a component s failure rate Low power reducing peak power consumption for less thermal effects, better signal integrity and reliability - Signal integrity / logic correctness / acceptable performance variation / design lifetime ECE 260B CSE 241A Power Consumption 5

6 Low Power Design Metrics Energy efficiency in Joules Energy = power * delay (Joules = Watts * seconds) Affects battery lifetime Average power consumption in Watts Results in thermal effects Sets packaging limits (50W / cm 2? 120W total?) ($1/Watt?) Worst case supply current Simultaneous transistor switching Supply voltage drop performance degradation Maximum device current device lifetime Electromigration wire lifetime ECE 260B CSE 241A Power Consumption 6

7 Power Versus Energy Watts Power is height of curve Lower power design could simply be slower Approach 1 Approach 2 Watts time Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time ECE 260B CSE 241A Power Consumption 7 Slide courtesy of Mary Jane Irwin, PSU

8 Low Power Design Objectives Worst case supply current I Average power P = I V Maximum cycle power Maximum N-cycle power Maximum sustainable power Energy E = P dt Energy-delay products Simultaneous power reduction and performance optimization Usually to reduce average power under timing constraints ECE 260B CSE 241A Power Consumption 8

9 Outline Problem statement Power dissipation components Power estimation Optimization techniques ECE 260B CSE 241A Power Consumption 9

10 Static CMOS Gate Power Power dissipation in static CMOS gate: 3 components Dynamic capacitive (switching, useful ) power Still dominant component in current technology Charging and discharging the capacitor Crowbar current (short-circuit power) During a transition, current flows through both P and N transistors simultaneously for a SHORT period of time Slow transitions worsen short-circuit power Leakage ( useless power ) current Even when a device is nominally OFF (V GS =0), a small amount of current is still flowing With many devices, can add up to hundreds of mw Slide courtesy of Mary Jane Irwin, PSU ECE 260B CSE 241A Power Consumption 10

11 Reducing Dynamic Capacitive (Switching) Power Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations P dyn = C L V DD 2 P 0 1 f Activity factor: How often, on average, do wires switch? Clock frequency: Increasing Slide courtesy of Mary Jane Irwin, PSU ECE 260B CSE 241A Power Consumption 11

12 Crowbar (Short-Circuit) Current Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting V Transition time I When V TN < V IN < V DD +V TP Both transistors are ON R P Current flowing directly from V DD to V GND is crowbar current Usually not a problem, e.g., P is ON strongly (LIN but with small V DS if at all) N is barely ON ECE 260B CSE 241A Power Consumption 12 Slide courtesy of Ken Yang, UCLA R N C L

13 Leakage (Inactive, Useless ) Power Three sources of leakage The dominant is the Source-to-Drain leakage current Even when V GS = 0, a small amount of charge is still present under the gate Exponentially related to the gate (and S/ D) voltage Source/Drain are junctions and some amount of reverse bias, I S is present Typically much smaller than S/ D leakage Gate tunneling leakage I D W L exp q V GS V T /nkt When t ox is only 5-10atoms, easy for tunneling current to flow More of an issue sub 0.10-µm technology ECE 260B CSE 241A Power Consumption 13 Slide courtesy of Ken Yang, UCLA

14 2001 ITRS Projections of 1/τ and I sd,leak for HP, LP Logic I sd,leak High Perf. 1.E+01 1.E+00 1/ τ (GHz) 1000 ` 1/τ High Perf. I sd,leak Low pwr 1/τ Low Pwr 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 I sd,leak (µa/µm) E-06 Year ECE 260B CSE 241A Power Consumption 14

15 Projections for Low Power Gate Leakage Simulated I gate, oxy-nitride 1.00 Jgate (normalized) T ox I gate spec. from ITRS Oxy-nitride no longer adequate: high K needed Year Tox (normalized) Need for high K driven by Low Power, not High Performance ECE 260B CSE 241A Power Consumption 15

16 Summary: Power and Energy Equations E = C L V DD 2 P t sc V DD I peak P V DD I leakage f 0 1 = P 0 1 * f clock 2 P = C L V DD f t sc V DD I peak f V DD I leakage Dynamic power Short-circuit Leakage power (~90% today and decreasing relatively) power (~8% today and decreasing absolutely) (~2% today and increasing relatively) Designers need to comprehend issues of memory and logic power, speed/power tradeoffs at the process (HiPerf vs. LowPower) level, Slide courtesy of Mary Jane Irwin, PSU ECE 260B CSE 241A Power Consumption 16

17 Outline Problem statement Power dissipation components Power estimation Optimization techniques ECE 260B CSE 241A Power Consumption 17

18 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Power Analysis Power Analysis Power Analysis Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 18

19 Transistor Level Power Estimation HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Circuit Simulation Current Flows Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 19

20 Power Estimation Dynamic Analysis Simulation requires representative simulation vectors - Derived by designer - Automatic (Monte Carlo) Transitor level (PowerMill) Very accurate Much faster than SPICE Gate level (Powergate, DesignPower) Faster than transistor level Still very accurate due to good modeling of power dissipation at cell-level ECE 260B CSE 241A Power Consumption 20

21 Power Ingredients V DD Dynamic Dissipation P dyn = C L V DD V sw f 0 1 In Out Short-Circuit Currents P sc = V DD I sc C L Static Dissipation I SC P stat = V DD I leak ECE 260B CSE 241A Power Consumption 21

22 Transistor-Level Power Estimation I T P = 1 T 0 i t v t dt t Spice is the reference, but too slow Commercial tools claim to be within 10% of SPICE accuracy and up to 1000X faster ECE 260B CSE 241A Power Consumption 22

23 Timing Simulation Vdd i(vdd) in out1 out2 out3 in out1 out2 Vdd-Vth out3 Up to 2 orders of magnitude faster than SPICE Uses simplified (table-lookup) transistor model Handles leakage, direct path, and reduced swing ECE 260B CSE 241A Power Consumption 23

24 Switch-Level Simulation Up to 3 Orders of Magnitude Faster than Circuit Accurate for Dynamic Power Unreliable on leakage and direct path currents A B X F Cap (ff/bit) IRSIM SPICE Sample ECE 260B CSE 241A Power Consumption 24

25 Perspective on accuracy and speed Adder Shift Register % Error Speedup % Error Speedup Timing Switch Comparison between circuit simulation (SPICE) and timing or switch analysis ECE 260B CSE 241A Power Consumption 25

26 Transistor Level Power Estimation Tools PowerMill Epic Mixed transistor/ gate simulation Piecewise linear model Star-ADM Avant! Mixed analog/ digital simulation Analytic closed-form model LSIM Analyst Mentor Graphics Mixed transistor/ gate simulation Series-Parallel Switch algorithm ECE 260B CSE 241A Power Consumption 26

27 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Power Analysis Power Analysis Power Analysis Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 27

28 Gate-Level Power Estimation Dynamic Switching Power (I sw ) [70-90%] Also referred to as capacitive power V Input Transition I Int I SW Internal (Short-Circuit) Power (I int ) [10-30%] Also referred to as short circuit power N I Leak C i GND Static Leakage Power (I leak ) [< 1%] Sub-threshold leakage dominates, some due to leakage substrate Complete power model provides infrastructure for analysis and optimization ECE 260B CSE 241A Power Consumption 28

29 Gate-Level Power Estimation toggle rate state of the gate input slope output load temperature fabrication process ECE 260B CSE 241A Power Consumption 29

30 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Place & Route Simulation with integrated Power Analysis Probabilistic Analysis Toggle Rates Power Analysis Simulation ECE 260B CSE 241A Power Consumption 30

31 Simulation Based Power Estimation Problems: The relationship of power versus primary input probabilities and activities is a complicated surface. The existing methods use discrete points to approximate such a surface. - The effectiveness strongly depends on the density of the chosen points. - The more points one chooses, the more accurate results. - More points directly translate to longer CPU time. ECE 260B CSE 241A Power Consumption 31 Slide courtesy, Z. Chen, K. Roy

32 Toggle Rate Estimation Probabilistic Propagation no input vectors needed much faster than simulation less accurate than simulation glitches? Simulation requires representative simulation vectors - derived by designer - automatic (Monte Carlo) ECE 260B CSE 241A Power Consumption 32

33 Signal Probability and Activity Signal probability and activity Signal probability - probability of a signal being logic ONE P i = lim T Signal activity (transition density) - probability of signal switching n i (T): the number of switching for i(t) in [ -T/2,T/2] 1 T A i =lim T T / 2 i t dt T / 2 n i T T ECE 260B CSE 241A Power Consumption 33 Slide courtesy, Z. Chen, K. Roy

34 Power Dissipation in terms of Activity Normalized activity f : clock frequency Normalized power dissipation measure Approximated power dissipation P avg = 1 2 V 2 dd j all nodes C A j j a i = A i f Cj : node capacitance Aj : node activity Normalized power dissipation measure = j all nodes f anout j a j f anout (j) : fanout number at node j ECE 260B CSE 241A Power Consumption 34 Slide courtesy, Z. Chen, K. Roy

35 Probability Propagation Let y = f(x 1,, x n ) be a Boolean function with independent variables x i, the signal probability of f can be obtained in linear time as follows. where P y =P x 1 P f x1 P x 1 P f x 1 f x1 = f 1, x 2,..., x n, f x 1 = f 0, x 2,..., x n are the cofactors of f with respect to x 1. Improve runtime by using a BDD ECE 260B CSE 241A Power Consumption 35

36 Activity Propagation Let y = f(x 1,, x n ) be a Boolean function with independent variables x i, the signal activity of f can be obtained in linear time as follows. where Boolean difference where is the exclusive-or operation. n A y = i =1 P y x i A x i y x = y x=1 y x=0 ECE 260B CSE 241A Power Consumption 36

37 Probability Propagation Propagate AND gate sp(1) = sp1 * sp2 tp(0 1) = sp * (1 - sp) Example sp = 0.5 * 0.5 = 0.25 tp = 0.25 * (1-0.25) = /2 1/2 1/2 1/2 1/4 1/4 7/16 ECE 260B CSE 241A Power Consumption 37

38 Probability Propagation for Basic Gates Ignores Temporal and Spatial Correlations ECE 260B CSE 241A Power Consumption 38

39 Probability Propagation Problems Problem: Reconvergent Fan-out: Creates spatial correlation between signals ? 0.5! P(X) = P(B=1).(P(X=1 B = 1) Becomes complex and untractable real fast ECE 260B CSE 241A Power Consumption 39

40 Solution to Reconvergence b c a Preferred Technique: Ordered Binary Decision Diagrams (OBDDs) Statistics computed in linear time (but graph size could be exponential) Other approaches: super-gates computation of correlation coefficients OBDD Z = bc + abc ECE 260B CSE 241A Power Consumption 40

41 How to introduce time? And include glitching effects TOUGH! If one also wants to include spatial effects or be general Example: Symbolic Simulation Approach (for unit delay) ECE 260B CSE 241A Power Consumption 41

42 Symbolic Network Transition Counters Value of d at time t= 0 Problem: Network can be huge and BDD cannot be created! ECE 260B CSE 241A Power Consumption 42

43 Probability Simulation User specifies typical signal behavior at the circuit inputs using probability waveforms, which is a sequence of values indicating the probability that the signal is high for a certain time intervals, and the probability that the signal takes transition from low to high t1 t2 t3 Propagation is very similar to event driven logic simulation ECE 260B CSE 241A Power Consumption 43

44 How about sequential circuits? I t I 0 PS 0 Next State PS t Comb. Logic Next State Logic introduces temporal correlations between subsequent samples Either assume that all states have equal probability, or use statistical Markov chains ECE 260B CSE 241A Power Consumption 44

45 Gate-Level Power Estimation Tools DesignPower PowerSim Synopsys Systems Science Probabilistic based Simulation based Simulation based Power_tool WattWatcher Gate POET Veritools Sente Viewlogic Simulation based Simulation based Simulation based Xpower Genashor Asynchronous designs ECE 260B CSE 241A Power Consumption 45

46 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Power Analysis Power Analysis Power Analysis Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 46

47 Power Estimation Simulation Monte-Carlo technique PowerMill at transistor level Verilog-XL at gate level Hierarchical simulation Architectural/ gate/transistor-level Parameterized power model for each module Statistical estimation Signal probability propagation ECE 260B CSE 241A Power Consumption 47

48 Power Estimation Methodology RTL library Synthesis P&R Synthesis condition RTL design RTL planning / mapping Post-layout netlist Power Characterization Power Macro-model database Power model library generator Powerlib.vhd Powerlib.v Powerlib.c Structure (macro) netlist Power model inference & Estimation code generation Enhanced RTL RTL simulation Testbench stimuli Power report ECE 260B CSE 241A Power Consumption 48 Power waveform / profile

49 Inaccuracies in Power Estimation In increasing order: The number of input stimuli did not cause any error above the 10% mark if we considered at least 10 input patterns Using a gate-level simulator as opposed to a circuit simulator caused an error of about +/-15% Repowering and physical design introduced inaccuracies below 20% Glitch power varied between 7%-43% Internal gate capacitances, which are a function of the target library, accounted for about half the power Optimization and technology mapping may cause power estimates to be off by an order of magnitude ECE 260B CSE 241A Power Consumption 49

50 Power and Synthesis Flow Potential for Power Savings 400% 50% 20% 10% Behavioral RTL Gate Switch Accuracy of Power Estimation ECE 260B CSE 241A Power Consumption 50

51 Expectations Algorithmic Behavioral Power manage Algorithm selection Concurrency Memory Clock ctrl orders of magnitude several times 10-90% RT Level Structural transform % Tech. indep. Tech dep. Layout Extr/ decomp Tech. mapping Gate sizing Placement 15% 20% 20% 20% ECE 260B CSE 241A Power Consumption 51

52 Power Estimation / Improving Guidelines Before technology mapping, the accuracy levels are unacceptable It is necessary to take into account internal gate capacitances as well as wire capacitances Gate-level estimation implies >15% error Simulation with as few as 10 patterns from typical inputs for a typical starting state is often sufficient to reach confidence levels matching those of gate-level simulation Power improving transformations should be run in late design stages, they should be applied only if they can predict significant power improvement, and should be applied many times (hundreds) to maximize the confidence of positively impacting the design ECE 260B CSE 241A Power Consumption 52

53 Outline Problem statement Power dissipation components Power estimation Optimization techniques ECE 260B CSE 241A Power Consumption 53

54 Low Power Design Techniques Reducing chip and package capacitance Scaling the supply / threshold voltages Using power management strategies Employing better design techniques ECE 260B CSE 241A Power Consumption 54

55 Reducing Capacitance Minimum area minimum power consumption Wirelength minimization with switching activities as weighting factors Placement / routing / partition / floorplanning Clock gating Sleep transistors ECE 260B CSE 241A Power Consumption 55

56 CMOS Device and Voltage Scaling Dual transistor threshold High Vth transistors optimize performance Low Vth transistors reduce leakage power Transistors with the same Vth need to group together Dual supply voltage High Vdd transistors on critical paths Low Vdd transistors reduce power Level-converters between signals of different voltage swings Routing cost of dual power supply Extension of classical transistor sizing algorithm, e.g., TILOS ECE 260B CSE 241A Power Consumption 56

57 Power Management Strategies Inactive hardware modules are automatically turned off to save power (for example, monitors, laptops, etc.) Transistors on non-critical data paths are slowed down, e.g., by dynamically scaling down their supply voltages (for example, in Transmeta microprocessors) Sleep transistors Power gating (controllable power supply mechanism) ECE 260B CSE 241A Power Consumption 57

58 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Power Analysis Power Analysis Power Analysis Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 58

59 Transistor-Level Power Optimization Optimizes up to 30,000 transistors at a time Starts from three initial solutions: initial sizes, all transistors sized up with constant factor, and all transistor identical size Optimization modes: individual transistor sizing retain ratios between connected NMOS and PMOS devices pseudo-nmos AMPS - Epic Optimization Goals Delay Power Slack ECE 260B CSE 241A Power Consumption 59

60 Design Abstraction Levels HDL Behavioral Synthesis RTL Synthesis Logic Optimization Transistor Optimization Power Analysis Power Analysis Power Analysis Power Analysis Place & Route ECE 260B CSE 241A Power Consumption 60

61 Gate-Level Power Optimization Logic or Gate Netlist Switching Activity Constraints (timing, power, area) Logic Optimization Tech Library Power Optimization Parasitics (Capacitance) Power Optimized Gate Level Netlist ECE 260B CSE 241A Power Consumption 61

62 Gate-Level Tradeoffs for Power Factoring Structuring Buffer insertion/deletion Don t care optimization Technology mapping Sizing Pin assignment ECE 260B CSE 241A Power Consumption 62

63 Factoring Idea: Remove common expressions to reduce capacitance Pa = 0.1 Pb = 0.5 Pc = 0.5 Caveat: This may increase activity! ECE 260B CSE 241A Power Consumption 63

64 Logic Restructuring Logic restructuring to minimize spurious transitions Buffer insertion for path balancing ECE 260B CSE 241A Power Consumption 64

65 Technology Mapping a b c d slack=1 Smaller gates reduce capacitance, but are slower ECE 260B CSE 241A Power Consumption 65

66 Technology Mapping Example: 6-input AND Implemented using 6 input NAND, 3 input NAND, and 2-input NAND [Bellaouar, ElMasry] Library 1: High-Speed Library 2: Low-Area ECE 260B CSE 241A Power Consumption 66

67 Technology Mapping Example 6-input 3-input 2-input Area Delay (ns) Energy (ff) Mapping results for high speed-library 6-input 3-input 2-input Library Library Energy comparison between libraries ECE 260B CSE 241A Power Consumption 67

68 Sequential Logic Optimization State encoding seems to be of minimal impact in general Data encoding in data paths e.g. use of sign-magnitude, one-hot, or redundant representations mostly ad hoc Retiming for low power registers can be strategically placed to reduce glitching, or to perform path balancing Clock gating Pre-computation ECE 260B CSE 241A Power Consumption 68

69 Clock gating Requires careful skew control... Scary in current logic synthesis world! ECE 260B CSE 241A Power Consumption 69

70 Pre-computation Inputs x i x n are not applied if pre-computing holds Other options: guarded evaluation set output directly ECE 260B CSE 241A Power Consumption 70

71 Power Compiler Results: design dependent library dependent average 15-20% pushbutton reduction in power ECE 260B CSE 241A Power Consumption 71

72 Low Power Synthesis Introduce more concurrency for performance improvement Linear power consumption increase Reduce power consumption by scaling down voltages Quadratic power consumption decrease Concurrency increasing transformations Loop unrolling Control flow optimizations Critical path reducing transformations Logic level minimization Retiming Pipelining ECE 260B CSE 241A Power Consumption 72

73 Summary Design Flow for Power well covered at circuit and gate level Most emphasis on analysis not much on optimization Overall optimization results are mixed Plenty of room at the physical end transistor sizing, circuit style selection, synthesis for pass-transistor networks, threshold selection ECE 260B CSE 241A Power Consumption 73