TWR-K70F120M Drawn by:

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1 Table of ontents TO/REVISION HISTORY NOTES RESERVE K70NM MU- K70NM MU- 6 US/OSM/VTRN/PWR 7 PERIPHERLS 8 ELEVTOR ONNETORS 9 SENSORS 0 R SRM, NN FLSH R POWER & TERMINTIONS Revisions Rev escription ate pproved Prototype release Jul TT 08 Release 7 Oct 08 Release - MU Marketing part number updated as per MO0 08 Release 8 Feb - Replaced obsolete resistor with hanged R6 to NP Nov Peter Jul Peter Peter, Kevin Peter, Kevin - hanged R, R, R, and R7 to NP 6 Jul Peter, Kevin Microcontroller Solutions Group 60 William annon rive West ustin, TX This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. IP lassification: FP: FIUO: X PUI: esigner: rawing Title: ionsn TWR-K70F0M rawn by: Page Title: ionsn Table of ontents/revisions pproved: Size ocument Number Rev Peter/Kevin SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

2 . Unless Otherwise Specified: ll resistors are in ohms ll capacitors are in uf ll voltages are ll polarized capacitors are aluminum electrolytic. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer. Power & Ground Nets NET VOLTGE ESRIPTION PV_US V Primary input power. Filtered from US connector. Input to US power switch. PV_SW V Output of US power switch controlled by the V_EN signal from the JM60 MU. Used by OSM voltage translation circuits. PV_TRG_US V Output of US power switch controlled by the VTRG_EN signal from the JM60 MU. Provides input to regulator. PV.V Output of regulator using US power input (PV_TRG_US).. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. PV_MU.V MU digital power. Filtered from PV. V.V V power for MU and analog circuits. Filtered from PV_MU. VREFH.V Upper reference voltage for on the MU. Filtered from V. VREFL 0V Lower reference voltage for on the MU. Filtered from VSS. VSS 0V VSS power for MU and analog circuits. Filtered from GN. GN 0V igital Ground. V_INT.V MU Internal supply VREF_R 0.9V R VREF = VQ/ supply for MU and SRM VTT_R 0.9V R VTT= VQ/ termination supply for MU and SRM V_V8.8V R VQ supply for MU and SRM IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: Notes Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

3 IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: Reserved Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

4 78 8PF KHz_EXTL R9 0 EXTL_RT 77 {6,8,9} NP {8,9,0} 8PF Y KHz_XTL NP Place Y and related components as close as possible to U {8,9} {8,9} {8,9} {8} {8,9} {8,9} {8,9} {8,9} PT[0..9] PT[0..].768KHz 0_P0 0_M0 _P0 _M0 0_P 0_M _P _M {7,8} {8} 0_OUT _OUT/MP_IN {} {9} {6,8,9} R9.0M {8} {8} NP 0_SE6 _SE6 RESET_ US0_P US0_N PT0 PT PT PT PT PT PT6 PT7 PT8 PT9 PT0 PT PT PT PT PT PT6 PT7 PT9 PT PT PT6 PT7 PT8 PT9 R9 0 PT0 PT PT PT PT PT PT6 PT7 PT8 PT9 PT0 PT PT6 PT7 PT8 PT9 PT0 PT PT PT TP NP 0_P0 0_M0 _P0 _M0 0_P 0_M _P _M XTL_RT Place R89 and R90 and related components as close as possible to U PT8 efault : short - NP R89 R90 TK/EZP_LK TI/EZP_I/FTM0_H6 TO/EZP_O TMS EZP_S_/TSI0_H TRST\RMII0_RXER TRE_LKOUT/ULPI_LK TRE\ULPI_IR TRE\ULPI_NXT TRE\ULPI_STP TRE_0/ULPI_T0 ULPI_T RMII0_RX RMII0_RX0 RMII0_RS_V RMII0_TXEN RMII0_TX0 RMII0_TX EXTL_MIN PT8 TWRPI_GPIO ULPI_T ULPI_T ULPI_T ULPI_T ULPI_T6 ULPI_T7 J HR X TH TP6 TP7 TP0 TP TP TP US0R_P US0R_N RMII0_MIO/TSI0_WU RMII0_M/TSI0_H6 TSI0_H7 TSI0_H8 IRQ IRQ F_/_S F_/_S F_/TWRPI_GPIO F_0/TWRPI_GPIO F_9/ F_8/ F_7/TSI0_H9 F_6/TSI0_H0 F_/TSI0_H F_OE_N/TSI0_H F_/ F_0/ F_9/ F_8/ PV R8 0.0K M L L6 R P6 R6 N6 M6 R R T T N N P P R R N P T T6 R6 M M T7 N8 T8 P8 R8 T R P N T P R M0 N0 R P N T T T6 N R M R P N M M P M N M L L K K J J J H H H G G G H6 U RYIE_TMPER0/RT_WKEUP RYIE_TMPER PT0/0_SE/TSI0_H/SPI0_PS/P0_EXTRG/F_/NF_T/IS0_TX RYIE_TMPER PT/0_SE/TSI0_H/SPI0_PS/URT_RTS/FTM0_H0/F_/NF_T0/IS0_TX0 RYIE_TMPER PT/0_SE/TSI0_H/SPI0_PS/URT_TS/FTM0_H/F_/NF_T9/IS0_TX_FS RYIE_TMPER PT/SPI0_PS/URT_RX/FTM0_H/F_LKOUT/IS0_TX_LK RYIE_TMPER PT/SPI0_PS0/URT_TX/FTM0_H/F_/NF_T8/IS_TX_LK RYIE_TMPER6 PT/SPI0_SK/LPTMR0_LT/IS0_RX0/F_0/NF_T7/MP0_OUT/IS_TX_FS RYIE_TMPER7 PT6/MP0_IN0/SPI0_SOUT/P0_EXTRG/IS0_RX_LK/F_9/NF_T6/IS0_MLK PT7/MP0_IN/SPI0_SIN/US_SOF_OUT/IS0_RX_FS/F_8/NF_T PG0P_0P0_P PT8/_SE/MP0_IN/FTM_H/IS0_MLK/F_7/NF_T PG0M_0M0_M PT9/_SE/MP0_IN/FTM_H/IS0_RX_LK/F_6/NF_T/FTM_FLT0 PGP_P0_0P PT0/_SE6/MP0_IN/I_SL/FTM_H6/IS0_RX_FS/F_/NF_T/IS_MLK PGM_M0_0M PT/_SE7/I_S/FTM_H7/IS0_RX/F_RW/NF_WE PGP_P0_P_0P PT/URT_RTS/F_7/FTM_FLT0 PGM_M0_M_0M PT/URT_TS/F_6 PGP_P0_P_P PT/URT_RX/F_ PGM_M0_M_M PT/URT_TX/F_ PT6/N_RX/URT_RX/ENET0_88_TMR0/F_S/F_TSIZ/F_E_6_LS_8/NF_R 0OUT_MPIN_0SE PT7/N_TX/URT_TX/ENET0_88_TMR/F_S/F_TSIZ0/F_E LS7_0/NF_E0 OUT_MPIN_SE PT8/URT_RTS/ENET0_88_TMR/F_TST/F_S/F_E_8_LS_6/NF_E PT9/URT_TS/ENET0_88_TMR/F_S/F_E7_0_LS_/F_T 0SE6_MPIN_0SE SE6_MPIN_0SE PT0/SPI0_PS0/URT_RTS/FTM_H0/F_LE/F_S/F_TS/IS_RX PT/0_SE/SPI0_SK/URT_TS/FTM_H/F_S0/IS_RX0 EXTL PT/SPI0_SOUT/URT_RX/FTM_H/F_/IS_RX_FS XTL PT/SPI0_SIN/URT_TX/FTM_H/F_/IS_RX_LK PT/SPI0_PS/URT0_RTS/FTM0_H/F_/NF_T/EWM_IN RESET PT/0_SE6/SPI0_PS/URT0_TS/URT0_OL/FTM0_H/F_/NF_T0/EWM_OUT PT6/0_SE7/SPI0_PS/URT0_RX/FTM0_H6/F_0/FTM0_FLT0 US0P PT7/MT_IRO/URT0_TX/FTM0_H7/FTM0_FLT US0M PT8/I0_SL/URT_RX/F_6/NF_LE PT9/I0_S/URT_TX/F_7/NF_LE PT0/URT_RTS/F_8/NF_RE PT0/JTG_TLK/SW_LK/EZP_LK/TSI0_H/URT0_TS/URT0_OL/FTM0_H PT/SPI_PS0/URT_TS/SH0_LKIN/F_9/GL_ONTRST PT/JTG_TI/EZP_I/TSI0_H/URT0_RX/FTM0_H6 PT/SPI_SK/FTM_FLT0/SH0_/F_0/GL_PLK PT/JTG_TO/TRE_SWO/EZP_O/TSI0_H/URT0_TX/FTM0_H7 PT/SPI_SOUT/SH0_/F_/GL_E PT/JTG_TMS/SW_IO/TSI0_H/URT0_RTS/FTM0_H0 PT/SPI_SIN/SH0_6/F_/GL_HFS PT/NMI/EZP_S/TSI0_H/FTM0_H PT/SPI_PS/SH0_7/F_/GL_VFS PT/US_LKIN/FTM0_H/RMII0_RXER/MII0_RXER/IS0_TX_LK/JTG_TRST PT6/_SE6/ULPI_LK/FTM0_H/IS_RX0/TRE_LKOUT PTE0/_SE/SPI_PS/URT_TX/SH0_/GL_0/I_S/RT_LKOUT PT7/0_SE0/ULPI_IR/FTM0_H/IS_RX_LK/TRE_ PTE/_SE/SPI_SOUT/URT_RX/SH0_0/GL_/I_SL/SPI_SIN PT8/0_SE/ULPI_NXT/FTM_H0/IS_RX_FS/FTM_Q_PH/TRE_ PTE/_SE6/SPI_SK/URT_TS/SH0_LK/GL_ PT9/_SE/ULPI_STP/FTM_H/MII0_RX/FTM_Q_PH/TRE_ PTE/_SE7/SPI_SIN/URT_RTS/SH0_M/GL_/SPI_SOUT PT0/_SE/ULPI_T0/FTM_H0/MII0_RX/FTM_Q_PH/TRE_0 PTE/SPI_PS0/URT_TX/SH0_/GL_ PT/_SE/ULPI_T/FTM_H/MII0_RXLK/FTM_Q_PH PTE/SPI_PS/URT_RX/SH0_/GL_/FTM_H0 PT/N0_TX/FTM_H0/RMII0_RX/MII0_RX/IS0_TX0/FTM_Q_PH PTE6/SPI_PS/URT_TS/IS0_MLK/GL_6/FTM_H/US_SOF_OUT PT/N0_RX/FTM_H/RMII0_RX0/MII0_RX0/IS0_TX_FS/FTM_Q_PH PTE7/URT_RTS/IS0_RX0/GL_7/FTM_H PT/MP_IN0/SPI0_PS0/URT0_TX/RMII0_RS_V/MII0_RXV/IS0_RX_LK/IS0_TX PTE8/_SE6/IS0_RX/URT_TX/IS0_RX_FS/GL_8/FTM_H PT/MP_IN/SPI0_SK/URT0_RX/RMII0_TXEN/MII0_TXEN/IS0_RX0 PTE9/_SE7/IS0_TX/URT_RX/IS0_RX_LK/GL_9/FTM_H PT6/MP_IN/SPI0_SOUT/URT0_TS/URT0_OL/RMII0_TX0/MII0_TX0/IS0_RX_FS/IS0_RX PTE0/URT_TS/IS0_TX0/GL_0/FTM_H PT7/_SE7/SPI0_SIN/URT0_RTS/RMII0_TX/MII0_TX/IS0_MLK PTE/_SE6/URT_RTS/IS0_TX_FS/GL_/FTM_H6 PT8/EXTL/FTM0_FLT/FTM_LKIN0 PTE/_SE7/IS0_TX_LK/GL_/FTM_H7 PT9/XTL/FTM_FLT0/FTM_LKIN/LPTMR0_LT PTE6/0_SE/SPI0_PS0/URT_TX/FTM_LKIN0/FTM0_FLT PT/MP_IN/ULPI_T/MII0_TX/F_9 PTE7/0_SE/SPI0_SK/URT_RX/FTM_LKIN/LPTMR0_LT PT/MP_IN/ULPI_T/MII0_TXLK/F_8 PTE8/0_SE6/SPI0_SOUT/URT_TS/I0_S PT6/_SE/ULPI_T/MII0_TX/F_7 PTE9/0_SE7/SPI0_SIN/URT_RTS/I0_SL/MP_OUT PT7/_SE/ULPI_T/MII0_RS/F_6 PTE/0_SE7/EXTL/N_TX/URT_TX/IS_TX_FS/GL_/EWM_OUT/IS_RX PT8/_SE/ULPI_T6/MII0_TXER/F_ PTE/0_SE8/XTL/N_RX/URT_RX/IS_TX_LK/GL_/EWM_IN/IS_TX PT9/_SE/ULPI_T7/MII0_OL/F_ PTE6/_SE/ENET_88_LKIN/URT_TS/IS_TX0/GL_/RT_LKOUT/US_LKIN PTE7/_SE/URT_RTS/IS_MLK/GL_6 PT0/0_SE8/_SE8/_SE8/_SE8/TSI0_WU/I0_SL/FTM_H0/RMII0_MIO/MII0_MIO/FTM_Q_PH PTE8/_SE7/GL_7 PT/0_SE9/_SE9/_SE9/_SE9/TSI0_H6/I0_S/FTM_H/RMII0_M/MII0_M/FTM_Q_PH PT/0_SE/TSI0_H7/I0_SL/URT0_RTS/ENET0_88_TMR0/FTM0_FLT PTF0/_SE/N0_TX/FTM_H0/IS_RX/GL_PLK PT/0_SE/TSI0_H8/I0_S/URT0_TS/URT0_OL/ENET0_88_TMR/FTM0_FLT0 PTF/_SE0/N0_RX/FTM_H/IS_RX_LK/GL_E PT/_SE0/GL_ONTRST/ENET0_88_TMR/FTM_FLT0 PTF/_SE6/I_SL/FTM_H/IS_RX_FS/GL_HFS PT/_SE/ENET0_88_TMR/FTM_FLT0 PTF/_SE7/I_S/FTM_H/IS_RX0/GL_VFS PT6/_SE/F_ PTF/_SE/FTM_H/IS_TX0/GL_0 PT7/_SE/F_ PTF/_SE/FTM_H/IS_TX_FS/GL_ PT8/URT_RTS/F_ PTF6/_SE6/FTM_H6/IS_TX_LK/GL_ PT9/SPI_PS/URT_TS/F_0 PTF7/_SE7/FTM_H7/URT_RX/IS_TX/GL_ PT0/_SE/SPI_PS0/URT_RX/IS_TX_LK/F_9/FTM0_FLT PTF8/FTM_FLT0/URT_TX/IS_MLK/GL_ PT/_SE/SPI_SK/URT_TX/IS_TX_FS/F_8/FTM0_FLT PTF9/URT_RTS/GL_ PT6/TSI0_H9/SPI_SOUT/URT0_RX/IS_TX0/F_7/EWM_IN PTF0/URT_TS/GL_6 PT7/TSI0_H0/SPI_SIN/URT0_TX/IS_TX/F_6/EWM_OUT PTF/URT_RTS/GL_7 PT8/TSI0_H/N0_TX/FTM_H0/IS0_TX_LK/F_/FTM_Q_PH PTF/URT_TS/GL_8 PT9/TSI0_H/N0_RX/FTM_H/IS0_TX_FS/F_OE/FTM_Q_PH PTF/URT_RX/GL_9 PT0/_SE/SPI_PS0/F_/NF_T/MP0_OUT PTF/URT_TX/GL_0 PT/_SE/SPI_SK/F_0/NF_T PTF/URT0_RTS/GL_ PT/SPI_SOUT/F_9/NF_T PTF6/SPI_PS0/FTM0_H/URT0_TS/URT0_OL/GL_ PT/SPI_SIN/SPI0_PS/F_8/NF_T/MP_OUT PTF7/SPI_SK/FTM0_H/URT0_RX/GL_ PTF8/SPI_SOUT/FTM_H0/URT0_TX/GL_ PTF9/SPI_SIN/FTM_H/URT_RX/GL_ PTF0/SPI_PS/FTM_H0/URT_TX/GL_6 PTF/_SE6/FTM_H/URT_RTS/GL_7 PTF/_SE7/I0_SL/FTM_H0/URT_TS/GL_8 OF PTF/_SE0/I0_S/FTM_H/TRE_LKOUT/GL_9 PTF/_SE/N_RX/FTM_Q_PH/TRE_/GL_0 PTF/_SE/N_TX/FTM_Q_PH/TRE_/GL_ PTF6/_SE/FTM_Q_PH/TRE_/GL_ PTF7/_SE/FTM_Q_PH/TRE_0/GL_ G6 F_/TSI0_H PT0 F F_/TSI0_H PT F F_/TSI0_H PT E F_LKOUT/URT_RX PT E F_/URT_TX PT E F_0/ PT F F_9/ PT6 G F_8/ PT7 H F_7/ PT8 F F_6/ PT9 G F_/I_SLTP PT0 H F_RW/I_S TP PT J F_7/URT_RTS_ TP6 PT K F_6/URT_TS_ TP7 PT J F_/URT_RX PT F0 F_/URT_TX PT F9 URT_RX/NF_Rn PT6 E9 URT_TX/NF_E0 PT7 M9 ENET0_88_TMR PT8 M8 F_T/ENET0_88_TMR PT9 L8 F_TS_N/pushbutton PT0 F8 F_S0/ PT K6 F_/ PT J6 F_/ PT K F_/ PT J F_/ PT K F_0/ PT6 E7 VTT_SENSE PT7 J NF_LE PT8 F7 NF_LE PT9 E6 NF_RE PT0 G SPI_PS0 PT F SPI_SK/SH0_ PT F SPI_SOUT/SH0_ PT E SPI_SIN/SH0_6 PT E SPI_PS/SH0_7 PT E SPI_PS/SH0_ PTE0 F SPI_SIN/SH0_0 PTE F R SPI_SK/SH0_LK PTE G SPI_SOUT/SH0_M PTE G SH0_ PTE G SH0_ PTE H IS0_MLK PTE6 H IS0_RX0 PTE7 H IS0_RX_FS PTE8 J IS0_RX_LK PTE9 J IS0_TX0 PTE0 K IS0_TX_FS PTE K IS0_TX_LK PTE J SPI0_PS0 PTE6 K SPI0_SK PTE7 L SPI0_SOUT/I0_S PTE8 M SPI0_SIN/I0_SL PTE9 P7 EXTL R7 XTL M7 K7 pushbutton0 PTE6 L7 Reserved_K7 PTE7 _SE7 PTE8 P6 L_PLK/ PTF0 L L_E/ PTF N6 L_HSYN/ PTF M6 L_VSYN/ PTF L6 L_0 PTF K6 L_ PTF J6 L_ PTF6 F L_ PTF7 F6 L_ PTF8 K L_/URT_RTS_ PTF9 L L_6/URT_TS_ PTF0 K L_7/URT_RTS_ PTF L L_8/URT_TS_ PTF H6 L_9/URT_RX PTF G6 L_0/URT_TX PTF F6 L_/URT0_RTS_ PTF E L_/URT0_TS_ PTF6 F L_/URT0_RX PTF7 G L_/URT0_TX PTF8 H L_/URT_RX PTF9 H L_6/URT_TX PTF0 P9 L_7/URT_RTS_ PTF N9 L_8/URT_TS_ PTF P0 L_9/TRE_LKOUT PTF R0 L_0/TRE_ PTF R9 L_/TRE_ PTF T9 L_/TRE_ PTF6 T0 L_/TRE_0 PTF7 PT[0:9] {8,9,0} TP8 XTL PT9 PT[0:] {7,8,9,0} PTF[0:7] {8} PTE[0:8] {6,7,8,9} 0 7pF R EXTL 0M Y GN GN MHZ 9 7pF Place Y and related components as close as possible to U PK70FNM0VMJ HR X TH J8 J8 OFF -> Y Enabled J8 ON -> Y isabled PV J9 HR X TH L 0OHM 8 0UF +_V_OS 80 0.UF V OE GN LOK Input Y R9 LK 0MHz_OS OUT 0MHZ {8} LKIN0 68 R 68 EXTL_MIN IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: PK70FNM0VMJ MU Part Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

5 {0} R_[:0] U R_Q[:0] {0} efault: - (use PV) PV J8 PVR HR X TH L 00 OHM@00MHZ 7 0.UF L6 00 OHM@00MHZ L 00 OHM@00MHZ PV_MU TP UF 0.UF 0.UF 0.UF V L8 00 OHM@00MHZ L7 0.UF 0.0UF 00 OHM@00MHZ T NP VSS UF 0.UF 0.UF {0} {0} VREFH R_0 0 R_Q0 R_ R_0 R_Q0 R_Q R_ R_ R_Q R_Q R_ R_ R_Q 6 R_Q R_ 0 R_ R_Q 6 R_Q R_ R_ R_Q 6 R_Q R_6 R_ R_Q 7 R_Q6 R_7 R_6 R_Q6 8 R_Q7 R_8 R_7 R_Q7 R_Q8 R_9 R_8 R_Q8 R_Q9 R_0 R_9 R_Q9 R_Q0 R_ R_0 R_Q0 R_Q R_ R_ R_Q R_Q 6 R_ R_Q TP8 R_Q R_ R_Q TP9 R_Q R_ R_Q R_Q R_0 9 R_Q {0} R_0 R_ 0 R_0 R_S_ {0} R_ R_S_ {0} R_ R_S 9 R_ R_S_ {0} R_ R_ R_S R_S_ {0} R_RS_ R_RS_ {0} R_K R_RS E6 R_WE_ {0} R_K R_WE_ {0} R_K_ R_WE 0 R_K 7 R_OT {0} R_K_ R_OT {0} R_KE 6 R_K R_OT {0} R_KE R_KE R_QM0 9 R_VSS E {0} R_QM0 R_QM R_M0 R_VSS {0} R_QM R_M R_VSS 7 R_QS0 8 R_VSS 8 R_QS0 R_QS R_QS0 R_VSS 9 R_QS R_QS R_VSS6 R_VSS7 V_V8 R_V R_VSS8 R_V R_VSS9 6 R_V R_VSS0 7 R_V 8 R_V R_VSS_ULK E8 VREF_R E0 R_V6 R_VSS_ULK E R_V7 R_VSS_ULK E R_V8 6 R_V9 L R_V0 VSS T 7 6 VSS N7 R_VREF VSS H8 0.UF VINT H7 VSS J8 VSS J0 H0 VINT K8 HR X TH VINT VSS6 H9 G7 VSS7 J9 J7 V VSS8 K9 G8 V VSS9 L9 G9 V VSS0 T G0 V VSS TP0 J0 V NP K0 V6 L0 V7 L VOUT_V V8 VOUT VREFL 0.0UF N P M N T P V VREFH VREFL VSS VREFOUT_MPIN_P0IN_SE8 VT PK70FNM0VMJ OF VREGIN L VREGIN R86 0.0K 7 0.UF 7 0.UF 7.UF 0 NP PV_MU R88 VREGIN {8} VREF_OUT VT 0_SE6 {} 06// oin ell PV_MU efault: - (use PV_MU) J7 R87 0.0K T + - VOIN VT T 7 0.UF HR TH X K-88 IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: PK70FNM0VMJ MU Part Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

6 G {,8,9} PT[0..9] PV_TRG_US J TGT_PWR HR X TH efault: no shunt (isconnect Target Power) PT PV_MU KEY - PIN 7 EZP_S_/TSI0_H R7 NP 0 EZP_SR_ JTG J TMS TK/EZP_LK 6 TO/EZP_O 8 TI/EZP_I/FTM0_H6 9 0 RESET_ TRE_LKOUT/ULPI_LK R7 0 TRE_0/ULPI_T0 NP 6 TRE\ULPI_STP 7 8 TRE\ULPI_NXT 9 0 TRE\ULPI_IR HR_9P PT PT0 PT PT PT6 PT0 PT9 PT8 PT7 PV R7 PT TMS 0.0K Place R7 and R8 as close as possible TOGETHER and close to U {,7,8,9} PTE[0..8] JM[..] PV S S PV VUS - + I R78 0 S S R6 0.0K R70 0.0K VTRG_IN US_MINI_ J 0M Y MHz 8PF R69 0.0K 8 8PF US_VUS US_N US_P U U 6 OUT_EN_ SN7LV0PWE OUT_EN TX_RX_EN_ SN7LV0PWE RTS JM60_XTL JM60_EXTL 0UF JM8 0.UF JM JM VUSV T_TX T_RX TLK_EN IN OUT SLK_OUT V_FULT VTRG_FULT U7 SP00 R R PV_US 0UF JM8 JM9 JM JM JM JM JM JM JM60_N JM60_P L 0 OHM On oard OSM/Serial ridge 9 0.UF PTE0/Tx PTE/Rx PTE/TPMH0 PTE/TPMH PTE/MISO PTE/MOSI PTE6/SPSK PTE7/SS PTF0/TPMH PTF/TPMH PTF/TPMH0 PTF/TPMH PTG0/KIP0 PTG/KIP PTG/KIP6 PTG/KIP7 PTG/XTL PTG/EXTL VUS USN USP TP9 NP 0.UF PV_US 6 V V/VREFH VSSOS VSS VSS/VREFL 9 7 oard Rev NP R 0.0K R 0.0K NP R 0.0K R 0.0K U8 PT0/MISO/P0 PT/MOSI/P PT/SPSK/P PT/SS/P PT/KIP/P PT/KIP/P 0 PT0/SL PT/S PT PT/Tx PT PT/Rx IRQ/TPMLK RESET KG/MS 6 M9S08JM60L NP R 0.0K JM_KG J HR_X PV_US R0 0.0K PT0/P8/MP+ 0 PT/P9/MP- PT/KIP/MPO 6 JM60 M R8 R8 oard I JM JM JM JM6 JM7 JM8 JM0 JM JM JM 0.0K 0.0K R8 8K JM9 JM0 JM JM60_RESET_ R7 0.0K R9 0 R8 0.0K R_REV R_REV R_REV0 R_I R_I0 V_EN VTRG_EN R_I0 RK_TMS R_I VTRG_IN R_REV0 R_REV R_REV TRESET_OUT PT0 PT TRESET_IN JM60_IRQ_ PV_US PV_US V_EN R76 efault: no shunt (isable ootload) JM60 ootload Enable VTRG_EN 0.0K 000PF J0 JM JM JM0 JM7 JM HR X TH JM JM ELE_PS_SENSE JM JM JM JM JM6 JM JM8 JM JM JM JM JM JM JM9 JM0 JM9 JM JM JM JM V_EN SLK_OUT TLK_EN OUT OUT_EN_ RK_TMS TX_RX_EN_ T_TX OUT_EN_ IN TRESET_OUT OUT_EN_ TRESET_IN TX_RX_EN_ T_RX PT PT0 V_FULT VTRG_FULT VTRG_EN Q R R0.99K R7 0.0K U6 R7.0K R6.0K R8.K ELE_PS_ PV_SW V GN 7HT RST_ PU_ST PU_TP R7 0.0K U6 8 7HT STTUS U9 OE OE 7LV U EN EN IN GN OE OE V GN TPWR MI06-YM Y Y 8 Y 6 Y YEL/GRN TO Q MMT90LTG U6 6 7HT 0 LE_YELLOW FLG FLG OUT 8 OUT 0.UF RG_RX 9 PV_MU NP R7 0.0K US_PWR 0.UF PV PV TK/EZP_LK TI/EZP_I/FTM0_H6 TMS TO/EZP_O R79 0.0K R6 0 RSTR ORNGE RG_TX PV R 0 URT_RX RESET MNUL RESET PV_US NP SW P switch TP 9 T R6 0 RESET_ PV_SW 6 0UF PT0 PT PT PT URT_TX PV PTE7 PTE6 R7 0.0K PU R8 0.0K PU RX Source Select RESET_ TX estination Select U V GN SN7LV0PWE UE 0 R6 0.0K PU R9 0.0K PU RESET_ {,8,9} U 9 8 SN7LV0PWE UF US-SHL R 0 TP8 NP PV_TRG_US PTT 0 SN7LV0PWE SN7LV0PWE PV_TRG_US PV_ELEV {8} MSSPL U TP8 NP PV PV_SW {8} ELE_PS_SENSE TP7 TP 7 0UF T VIN OUTPUT GN MI90-.WS LT9-.V 9 0UF 0UF 0.UF 0.UF 7 0.UF R8 70 PU_PO_LE 8 POWER ON 0.UF YEL/GRN 0.UF R80 0.0K PU U6 7HT IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: US/OSM/VTRN/PWR Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of 6

7 9 MIRO S INTERFE PV R 0.0K +.7uF 0.UF J Place R as close as possible to U PTE PTE PTE PTE PTE PTE0 SH0_M SH0_ T /T M V LK VSS T0 T _SW _OMMON VSS VSS VSS VSS PUSH UTTON PTE8 R 0 onn MicroS 0 SW pushutton PT0 NOTE: on't pushbutton if Flexbus or IS is used P switch {,6,8,9} PTE[0..8] SW Pushbutton0 PTE6 P switch IS SI HEER J6 PTE8 PTE0 PTE9 PTE6 IS0_RX_FS IS0_TX0 IS0_RX_LK IS0_MLK IS0_TX_FS IS0_RX0 IS0_TX_LK PTE PTE7 PTE HR_x PV {,8,9,0} PT[0..] R 0.0K PT7 MT_IRO J HR X TH IRJ QTLP60IR IRR R IR IR_SEN Q QTLP60P R 0.0K 0.0UF J6 HR X TH MP_IN _OUT/MP_IN {,8} efault: no shunt (isable IR) IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: Peripherals Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of 7

8 {,6,9} PT[0..9] PT[0..9] {,9,0} PT[0..] PT[0..] {,9,0} PT[0..9] PT[0..9] {,7,9,0} PT[0..] PT[0..] {,6,7,9} PTE[0..8] PTE[0..8] {} PTF[0:7] PTF[0:7] {6} PV_ELEV PV_ELEV PV J7 V_ V_ GN_ GN_9.V_.V_ {6,8} ELE_PS_SENSE {6,8} ELE_PS_SENSE ELE_PS_SENSE_.V_ 6 GN_ GN_0 6 PTE SPI_SK 7 GN_ GN_ 7 I0_SL 0 R PTE9 8 SH_LK/SPI_LK I0_SL I0_S 0 R PTE8 PTE SPI_PS0 9 SH_/SPI_S I0_S 8 URT_TS_ 0 NP R09 PTE8 PTE SPI_SOUT 0 SH_/SPI_S0 GPIO9/URT_TS 9 0 PTER 0 R PTE SPI_SIN SH_M/SPI_MOSI GPIO8/SH_ S_R_WP PTE SH_0/SPI_MISO GPIO7/S_WP_ET NP R9 0 TP PTE7 TP6 NP ETH_OL ETH_RS PT TRST/RMII0_RXER ETH_OL_ ETH_RS RMII0_M/MII0_M 0 R8 PT TP NP ETH_TXLK ETH_RXER_ ETH_M_ RMII0_MIO/MII0_MIO 0 R0 PT0 PT RMII0_TXEN ETH_TXLK_ ETH_MIO_ ETH_RXLK TP0 NP ETH_TXER 6 ETH_TXEN_ ETH_RXLK_ NP TP 6 RMII0_RS_V PT TP NP ETH_TX 7 ETH_TXER ETH_RXV_ 7 ETH_RX NP TP9 TP NP ETH_TX 8 ETH_TX ETH_RX 8 ETH_RX NP TP PT PT7 RMII0_TX 9 ETH_TX ETH_RX 9 RMII0_RX PT6 RMII0_TX0 0 ETH_TX_ ETH_RX_ 0 RMII0_RX0 PT PTE9 NP GPIO/URT_RTS_ ETH_TX0_ ETH_RX0_ IS0_MLK PTE6 PTE0 R06 0 PTE0_R GPIO/URT_RTS IS0_MLK IS0_TX_LK PTE PTE8 GPIO GPIO/SH_ IS0_OUT_SK R0 0 IS0_TX_FS PTE GPIO IS0_OUT_WS IS0_RX0 PTE7 {} LKIN0 RT_LKOUT LKIN0 IS0_IN0 IS0_TX0 PTE0 PTE6 6 LKOUT IS0_OUT0 6 R9 0 7R 7 GN_ GN_ 7 R 0 R6 {,9} 0_P 0_P0 {,9} R8 0 6R 8 N7 N 8 R 0 R7 {,9} 0_M 0_M0 {,9} R7 0 R 9 N6 N 9 R 0 R8 {,9} _P _P0 {,9} R6 0 R 0 N N 0 0R 0 R9 {,9} _M N N0 _M0 {} 0_OUT {} PT6 GN_ GN_ {,7} _OUT/MP_IN 0 FTM_H PT9 PT8 TMR TMR TMR FTM_H0 PT8 Place R TMR TMR0 PT9 as close PT R NP 0 6 GPIO GPIO6 6 PT6 to R7 PT R NP 0 FTM0_H7R 7.V_.V_6 7 FTM0_H 0 R and R8 PT FTM0_H6R 8 PWM7 PWM 8 FTM0_H 0 R PT as FTM0_H 9 PWM6 PWM 9 FTM0_H 0 R0 PT possible PT7 FTM0_H 0 PWM PWM 0 FTM0_H0 0 R PT PT6 R NP 0 N_RX PWM PWM0 0 NP R URT_RX PTF7 PT7 R NP 0 N_TX N0_RX URT0_RX 0 NP R URT_TX PTF8 N0_TX URT0_TX 0 R PT SPI_MISO WIRE URT_RX URT_RX PTE7 PT SPI_MOSI SPI0_MISO/IO URT_TX 0 R6 PT SPI_S0 6 SPI0_MOSI/IO0 VSS URT_TX PTE6 PT SPI_S 7 SPI0_S0 V 6 PT SPI_LK 8 SPI0_S N_RX 7 VSS V 9 SPI0_LK N_TX 8 9 PTE9 R 0 I0_SL 0 GN_6 GN_ 0 PTE8 R 0 I0_S I_SL GPIO HR X TH I_S GPIO PTF6 PTE8 S_R_ETET GPIO/SPI0_HOL/IO GPIO6/SPI0_WP/IO J PTF7 RSRV_ efault: - GPIO7 (VUS enabled) PTF8 US0_N {} PT IRQ RSRV_ US0_M 0 R9 6 IRQ_H US0_P US0_P {} VREGIN {} PT IRQ 7 IRQ_G US0_I 6 0 R96 US0_VUS 8 IRQ_F US0_VUS 7 IS0_RX_LK PTE9 PT6 0 R97 IRQ 9 IRQ_E IS0_IN_SK 8 IS0_RXFS PTE8 IRQ_ RESET_ 60 IS0_IN_WS 9 60 IS0_RX R 0 NP PTE8 PT7 0 R98 IRQ 6 IRQ_ IS0_IN 6 IS0_TX R 0 NP PTE9 IRQ_ {,6,9} 6 IS0_OUT PT0 EI_LE / EI_S_ 6 IRQ_ RSTIN 6 6 RSTOUT_ R0 0 PT8 PTF PT EI_S0_ 6 EI_LE/EI_S RSTOUT 6 EI_LKOUT PT PTF 6 EI_S0 LKOUT0 6 PT8 EI_ 66 GN_7 GN_ 66 EI_ PT0 PT7 EI_6 67 EI_ EI_ 67 EI_ PT PT6 EI_7 68 EI_6 EI_ 68 EI_ PT PT EI_8 69 EI_7 EI_ 69 EI_ PT PT0 EI_9 70 EI_8 EI_ 70 EI_0 PT PT EI_R/W_ 7 EI_9 EI_0 7 EI_9 PT6 EI_OE_ 7 EI_R/W EI_9 7 EI_8 PT7 PT9 EI_7 7 EI_OE EI_8 7 EI_7 PT8 PT0 EI_6 7 EI_7 EI_7 7 EI_6 PT9 PT EI_ 7 EI_6 EI_6 7 EI_ PT0 EI_ 76 EI_ EI_ 76 PT EI_ 77 EI_ EI_ 77 EI_ PT PT EI_ 78 EI_ EI_ 78 EI_ PT PTF PT EI_ 79 EI_ EI_ 79 EI_ PT PTF PT EI_0 80 EI_ EI_ 80 EI_ PT PTF6 PT 8 EI_0 EI_0 8 EI_0 PT6 PT 8 GN_8 GN_6 8.V_.V_7 PV PV 6 PT SPI_LK 7 PT SPI_S 8 PT SPI_S0 9 PT SPI_MOSI 0 PT SPI_MISO PT8 TRE\ULPI_NXT PT7 TRE\ULPI_IR PT7 ULPI_T PT8 ULPI_T6 PT9 ULPI_T7 6 PTF L_HSYN 7 PTF L_VSYN PTF0 L_LK PT8 R0 0 L_ONTRST PTF L_E PTF L_0 PTF L_ 6 PTF6 L_ 7 L_ 8 PTF7 9 0 L_ L_ L_ R00 6 PT 0 IRQ 7 8 PT R0 0 IRQ 9 60 R0 PT6 0 IRQ 6 PT7 R0 0 IRQ 6 L_8 6 L_ L_0 78 L_ 79 L_ J7 V_ V_ GN_7 GN_.V_8.V_ ELE_PS_SENSE_.V_ GN_8 GN_6 GN_9 GN_7 SPI_LK I_SL SPI_S I_S SPI_S0 GPIO SPI_MOSI ULPI_STOP SPI_MISO ULPI_LK ETH_OL_ GPIO6 ETH_RXER_ ETH_M_ ETH_TXLK_ ETH_MIO_ ETH_TXEN_ ETH_RXLK_ GPIO8 ETH_RXV_ GPIO9/SH_ GPIO7/SH_6 GPIO0/SH_ GPIO8/SH_7 ETH_TX_ ETH_RX_ ETH_TX0_ ETH_RX0_ ULPI_NEXT/US_HS_M ULPI_T0/IS_MLK ULPI_IR/US_HS_P ULPI_T/IS_OUT_SK UPLI_T/US_HS_VUS ULPI_T/IS_OUT_WS ULPI_T6/US_HS_I ULPI_T/IS_IN0 ULPI_T7 ULPI_T/IS_OUT0 GN_0 GN_8 L_HSYN/L_P N L_VSYN/L_P N0 N N9 N N8 GN_ GN_9 L_LK/L_P6 GPIO9/URT_ TMR TMR9 TMR0 TMR8 GPIO GPIO0/URT_.V_9.V_ PWM PWM PWM PWM0 PWM PWM9 PWM PWM8 N_RX URT_RX/TSI0 N_TX URT_TX/TSI L_ONTRST URT_RTS/TSI L_OE/L_P7 URT_TS/TSI L_0/L_P0 URT_RX/TSI L_/L_P URT_TX/TSI L_/L_P URT_RTS/N_RX L_/L_P URT_TS/N_TX GN_ GN_0 GPIO L_/L_P GPIO L_/L_P L_/L_P L_6/L_P6 L_/L_P L_7/L_P7 L_/L_P L_8/L_P8 IRQ_P/SPI_S L_9/L_P9 IRQ_O/SPI_S L_0/L_P0 IRQ_N L_/L_P IRQ_M IS_IN_SK IRQ_L IS_IN_WS IRQ_K IS_IN IRQ_J IS_OUT IRQ_I L_/L_P L_8/L_P8/S_RX_0+ L_6/L_P6/S_GN L_9/L_P9/S_RX_0- L_7/L_P7/S_GN GN_ GN_ EI_0/L_P/S_GN EI_E /L_P8/S_TX_0+ EI_/L_P/S_GN EI_E 6/L_P9/S_TX_0- EI_/L_P/S_RX_+ EI_E 8/L_P0/S_GN EI_/L_P/S_RX_- EI_E_7_0/L_P/S_GN EI_/L_P6/S_GN EI_TSIZE0/L_P/S_TX_+ EI_/L_P7/S_GN EI_TSIZE/L_P/S_TX_- EI_6/L_P8/S_RX_+ EI_TS/L_P/S_GN EI_7/L_P9/S_RX_- EI_TST/L_P/S_GN EI_8/L_P0/S_GN EI_T/L_P6/S_TX_+ EI_9/L_P/S_GN EI_S/L_P7/S_TX_- EI_0/L_P/S_RX_+ EI_S/L_P8/S_GN EI_/L_P/S_RX_- EI_S/L_P9/S_GN L_0/L_P0/S_GN EI_S/L_P0/S_TX_+ L_/L_P/S_REFLK+ GPIO/L_P/S_TX_- L_/L_P/S_REFLK- L_/L_P/S_GN GN_ GN_.V_0.V_ PV I0_SL R6 0 PTE9 I0_S R6 0 PTE8 TRE\ULPI_STP PT9 TRE_LKOUT/ULPI_LK PT6 R8 0 TRE_0/ULPI_T0 PT0 ULPI_T PT ULPI_T PT ULPI_T PT ULPI_T PT6 L_ PTF8 L_ PTF9 L_6 PTF0 L_7 PTF L_8 PTF L_9 PTF L_0 PTF L_ PTF L_ PTF9 L_6 PTF0 L_7 PTF L_ PTF7 PI EXPRESS TOWER SYSTEM PRIMRY PI EXPRESS TOWER SYSTEM SEONRY ***NOTE: EI bus is equivalent to F (FLEX US) from MU Notes: Place R07,R08 near to J7 Place these R, If flow control needs to be tested, and remove R,R IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: Elevator onnector Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of 8

9 GENERL PURPOSE TWRPI PV PV {,8} _P0 {,8} {,8} 0_P0 0_M0 PV_TRG_US J PV R.70K J R.70K {,8} 0_P PV R9 0.0K TWRPI- TWRPI-I V TWRPI-0 TWRPI- TWRPI-I RESET_ PV R0 0.0K PTE9 PTE6 I0_SL PT SPI_MISO PT SPI_S_ PT TWRPI_GPIO0/IRQ R 0 PT9 TWRPI_GPIO TWRPI_GPIO I0_S SPI_MOSI SPI_LK TWRPI_GPIO TWRPI_GPIO PTE8 PT PT PT8 PT9 VSS ON_X0 VSS ON_X0 {,8} 0_M {,6,7,8} PTE[0..8] PTE {,6,8} RESET_ {,8,0} {,6,8} PT[0..9] PT[0..9] PT PT {,8,0} PT[0..] PT PT {,7,8,0} PT[0..] PT PT PV {,8} _P PV R6 0.0K PV_TRG_US PT0 TSI0_H0 PT TSI0_H6 PT TSI0_H7 PT0 TSI0_H PT TSI0_H TSI0_H9 PT6 TSI0_H PT8 TOUH TWRPI-I0 J ON_X0 PV VSS V TSI0_H8 PT TSI0_H PT TSI0_H PT TSI0_H0 TSI0_H PT7 PT9 TOUH TWRPI-I RESET_ R 0.0K PV R 0.0K PTE9 PTE8 +.7uF I0_SL I0_S 6 ELEROMETER PV R UF U SL S VIO V 8 0.UF {} _SE6 TOUH P TWRPI NP _S0 R60 0.0K _YP 7 0.UF 7 S0 YP GN GN GN INT INT N N8 N N N IRQ IRQ PT PT7 MM8Q 0 TOUH ELETROES WITH LES PT PT6 PT PT TSI0_H9 TSI0_H7 TSI0_H8 TSI0_H POTENTIOMETER PV PV PV PV PV R7 0 PTR LEOR R8.0K R9 0 PTR LEYR R6.0K R66 0 PTR LEGR R67.0K R68 0 LER PT6R R77.0K R K 0.UF _M {,8} 7 LE_OR + ELETROE 8 LE_YEL + ELETROE LE_GRN + ELETROE LE_ELETROE VREFH VREF YPSS PT PT8 PT9 PT0 6 0.UF VREFL X IP lassification: FP: FIUO: PUI: rawing Title: TWR-K70F0M Page Title: Sensors Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of 9

10 R- MEMORIES N TERMINTIONS VREF_R V_V8 {,8} PT[6:7] PT7 PT6 {} PT[8:0] PT0 PT9 PT8 {} R_[:0] R_0 R_ R_ R_ R_ R_ R_6 R_7 R_8 R_9 R_0 R_ R_ R_0 {} R_0 R_ {} R_ R_ {} R_ R_QM0 {} R_QM0 R_QM {} R_QM R_QS0 {} R_QS0 R_QS {} R_QS R_S_ {} R_S_ R_WE_ {} R_WE_ R_S_ {} R_S_ R_RS_ {} R_RS_ R_K {} R_K {} R_K_ R_K_ R_K R UF M8 M M7 N N8 N N7 P P8 P M P7 R L L L F F7 E8 7 8 L8 K L7 K7 J8 K8 J VREF /P 0 LM UM LQS LQS UQS UQS S WE S RS K K E R M9 J9 G G 7 G7 9 9 E9 G9 J V V V V V VQ VQ VQ VQ VQ VQ6 VQ7 VQ8 VQ9 VQ0 VL VSS VSS VSS VSS VSS N E J P9 R MEMORY VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ0 F H 7 E7 8 8 F8 H8 J7 VSSL U0 Q0 Q Q Q Q Q Q6 Q7 Q8 Q9 Q0 Q Q Q Q Q N N N N N KE OT G8 R_Q0 G R_Q H7 R_Q H R_Q H R_Q H9 R_Q F R_Q6 F9 R_Q7 8 R_Q8 R_Q9 7 R_Q0 R_Q R_Q 9 R_Q R_Q 9 R_Q R8 R R7 E K R_KE K9 R_OT R_OT {} MT7H6M6HR-:H NP R6 0.0K R_Q[:0] {} R_KE {} R_0 R_ R_ R_S_ R_WE_ R_RS_ R_S_ R_KE R_OT VTT_R R6 0.0K R06 0.0K R 0.0K R0 0.0K R7 0.0K R8 0.0K R9 0.0K R 0.0K R7 0.0K {,8,9} PT[0:] PT PT0 PT9 PT8 PT7 PT6 PT PT PT PT PT0 {,8} PT[:] PT PT {,8} PT[0:] PT PT PT PT0 R_K_ 00 Note: Place the R LK Termination resistor R7 close the hips NN FLSH V_V8 PV 6 0.UF 7 0.UF 8 0.UF 9 0.UF 0 0.UF 0.UF 0.UF 0.UF + 7uF PV 8 0.0UF 86 0.UF 87 0.UF 88 0.UF U 7 9 V_V8 0.UF VTT_R 6 0.UF 8 0.UF 7 0.UF 60 0.UF 9 0.UF 6 0.UF 6 0.UF PT6 R 0 R8.7K R8.7K PT7 PT0 PT PT8 PT9 Note: Place R,R near to U pins R 0 R0.7K NF_E_ NF_RE NF_WE NF_LE NF_LE NF_WP_ NF_R/_N 9 8 E 8 RE 6 WE 7 LE LE 9 7 WP R/ N N N N 6 N 0 N6 N0 N N 0 N N0 V V V V I/O0 I/O I/O I/O I/O I/O I/O6 I/O7 I/O8 I/O9 I/O0 I/O I/O I/O I/O I/O N N N N N N NF_0 NF_ NF_ NF_ NF_ NF_ NF_6 NF_7 NF_8 NF_9 NF_0 NF_ NF_ NF_ NF_ NF_ PT0 PT9 PT8 PT7 PT6 PT PT PT PT PT0 PT PT PT PT PT PT VSS VSS VSS VSS 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 0.UF 6 8 MT9FG6EWP:E IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: R SRM, NN FLSH Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of 0

11 9 8 R- TERMINTION REG () PV 7uF 6 7uF 7 UF Place next to pins and, 6 next to pins 9 and 0, 7 next to pin of U6 6 U6 RT RUN RUN TRK/SS ITH ITH SVIN 0 PVIN_ PVIN_ PVIN_ PVIN_ VQIN 7 9 SW_ 0 SW_ F L9 0.7uH R9.0K V_V8 7uF R 0.0K VTT_R 8 6 MOE/SYN PHSE PGOO PGOO SW_ SW_ F VTTR 7 L0 0.7uH VREF_R 7uF LT68 SGN PGN 79 0.UF IP lassification: FP: FIUO: X PUI: rawing Title: TWR-K70F0M Page Title: R Termination & Power Size ocument Number Rev SH-766 PF: SPF-766 Friday, July 06, 0 ate: Sheet of

12 TWR-K70FNM Tower Module Schematic Executive Summary Rev. 0. Freescale Semiconductor Inc. Microcontroller Solutions Group

13 Revision History Revision uthor ate hanges 0. MH 06/8/0 Preliminary version 0. MH 07/9/0 First release TWR-K70F0M Executive Summary Page of

14 Purpose The purpose of this document is to provide a written overview of the TWR-K70F0M board. The schematic source, OM, layout, and other design files are all available for download from the Freescale website (TWR- K70F0M-PW). The schematics and board design package are useful for reference, but notes embedded in the schematic are not sufficient to document important items and explain design decisions. This document will walk through the schematic for the TWR-K70F0M rev board page by page providing explanation for connections on the board and pointing out design rules and tips. bbreviations This summary will refer to components using the reference designators in the schematics. The beginning letters or letters identify the type of components as follows: = apacitor ex: = LE ex: J = onnector (male) ex: J P = Plug (female) ex: P R = Resistor ex: R T = Transformer ex: T U = evice ex: U Y = rystal ex: Y RP = Resistor pack ex: RP SW = Switch ex: SW TP = Test point ex: TP NP = o not populate. There is a footprint present on the board for the component, but it is not installed on the board. Schematic Page Table of ontents and Revision History Schematic Page - Notes In addition to some notes on units and signal nomenclature, this page provides a list of the power and ground nets used in the design. This includes the nominal voltage for each rail and a brief description of the usage. TWR-K70F0M Executive Summary Page of

15 Schematic Page - Unused Schematic Page K70 Processor (Non-R signals) This page is the first part of the symbol for the K70 processor. In general most of the signals are routed to buses or other off page connectors so that the signal names can be references for making connections to circuitry on other pages of the schematic.. locks There are three clock inputs available on the K70 processor, all of which have circuitry on this page of the schematic. TIP: ll signals on your board should be properly coupled to a plane with enough distance between traces to make sure the traces couple to planes instead of each other. This is particularly important for clock signals, so pay special attention to the layout of all clock traces... EXTL0/EXTL_MIN The circuit in the lower, left hand side of this page provides the primary clock input to the processor on the EXTL0 pin (EXTL_MIN net). This board is designed to support an RMII Ethernet connection. In order to support RMII, the 0MHz clock used for the Ethernet PHY must also be routed to the processor on EXTL0. For the tower system, a TWR-SER or TWR-SER card configured for RMII operation would drive the 0 MHz PHY clock on the LKIN0 net shown here. ecause the tower needs to run in stand-alone mode (no other tower cards present), there is also an option to use an on-board 0 Mhz oscillator to provide the main input clock. Jumpers (J8 and J9) and/or 0 ohm resistor population options (R9 and R) can be used to select between the two clock sources. In order to support the flexibility of the tower system, the circuit here is more complicated than what would be used in a typical end system where the input clock would usually come from a single, fixed source. TIP: Keep in mind that if RMII is being used the EXTL0 input must be 0 MHz and the clock trace length should be setup so that the clock reaches the Ethernet PHY and processor at the same time. Skew between the two clocks could result in timing violations on the RMII signals. TWR-K70F0M Executive Summary Page of

16 .. EXTL/XTL The K70 supports a secondary high frequency clock input on the EXTL/XTL pins. The Kinetis Peripheral Module Quick Reference document (KQRUG) available from the Freescale website, contains useful information and board layout guidelines for crystal circuits. Please refer to Section... Oscillators in the KQRUG for more information. TIP: OS can be used as the reference clock source for one or both of the PLLs, but there are some restrictions on its use. The following items should be taken into account if you are considering using OS as the main clock input on your board: Either OS0 or OS can be used as the reference clock source for the PLL being used as MGLKOUT. Only OS0 or the RT OS can be used as the FLL reference clock so one of those clock sources MUST be available to the MG if using FEE, FE, or LPE clock modes or when transitioning from the reset default FEI mode to PE mode (or any external clocked MG mode). You must transition through FE mode to enter PEE mode and use the PLL as the MGLKOUT source. If OS is to be used it must be configured in MG_0 and enabled in OS_R. If OS is the only external clock source then the only MG clock modes available are FEI, FI and LPI... EXTL/XTL The final clock is the khz oscillator. This input is primarily used as the reference clock for the real-time clock (RT), but in some modes it can be used as the main reference for the entire processor. The schematic includes loading capacitors and a resistor for the crystal circuit (77, 78, and R9), but these components are not populated (NP). The loading caps are not required because the K70 s internal oscillators include programmable loading caps up to 0pF. In this case the internal loading caps can be used, and so the external caps are not necessary.. US In order to maximize the eye for the US signals, it is important that the on-chip FS/LS transceiver signals (US0_P and US0_M) include ohm series termination resistors. These resistors need to be placed as close to the processor as possible. The US signals should also be routed as a 90 ohm differential pair. TWR-K70F0M Executive Summary Page of

17 6 Schematic Page - K70 Processor (R signals and Power) This page is the second and final part of the symbol for the K70 processor. This portion of the symbol includes all of the power and ground signals for the processor and the signals for the R memory interface. The R signals will be discussed later on the R memory page. 6. R_V The R_V pins are used to power the I/O pads for the R signals. This net can be.8v or.v nominal depending on the type of memory being used..8v is used for R or LPR..V is used for R. The TWR-K70F0M uses R memory, so R_V is.8v nominal. 6. R_VREF The R_VREF net is actually not used as a reference for the R pads on the processor. The R memory on the TWR-K70F0M does require R_VREF, so there is a special regulator included to generate this voltage (on page ). For R and R designs, the R_VREF net can be tied to the VREF used for the memory. For LPR designs, the memory does not need VREF, so the R_VREF net on the processor can be tied to V_R. midpoint VREF voltage is not required. 6. V_INT In order to allow for reduction of power without affecting the I/O rails, the K70 includes V_INT pins. The V_INT pins are used to supply power to the internal logic on the chip. J0 is provided so that the current draw on V_INT can be measured and/or a different voltage can be used to supply V_INT than what is being used for V. In a typical design V_INT would be connected directly to its power supply circuit or the V rail. 6. V The V pins are used to supply the power for the I/O pads on the processor with the exception of the R pads and the RT/tamper pins. J8 is provided so that the current draw on V can be measured and/or a different voltage can be used to supply V than the.v supply that is provided. In a typical design V would be connected directly to the main power supply circuit. Separation of the power into PV and Pv_MU nets is not recommended unless there is a specific need for separate nets. TWR-K70F0M Executive Summary Page 6 of

18 6. V/VSS The V and VSS pins are the power and ground for the analog blocks on the K70. In order to minimize noise to the analog blocks both V and VSS are a filtered nets derived from the main V and VSS nets for the processor. 6.6 VREGIN The VREGIN pin is the input to the on-chip US regulator. In this case the US connector is off-board so the VREGIN net comes from the elevator connectors (page 8). jumper is supplied so that VUS can be disconnected and/or a voltage can be supplied directly. For a typical US device system, VREGIN would be connected to VUS from the US plug. The US connector is subjected to ES from users plugging/unplugging cables, so some ES protection on US signals including VUS is strongly recommended. For a US host system, VREGIN would still connect to the US plug, but as the host needs to supply power a V power source on the board would be used to power both VREGIN and the VUS at the plug. ES is still an issue for hosts, so again, ES protection on the US lines including VUS is strongly recommended. TIP: VREGIN is used to provide power to the on-chip FS/LS transceiver. In order to use US0_P and US0_M VREGIN MUST be powered. 6.7 VOUT The VOUT pin is the output from the on-chip US regulator. The US regulator can supply.v and up to 0m that can be used as the main power for the processor (V) and powering the board. ecause the total current for the tower system with peripheral cards plugged in can exceed 0m, the tower board is not setup to be powered by VOUT by default. R88 can be populated to experiment with this feature. 6.8 VT The final power domain for the K70 is the VT domain. The VT powers the RT, ryice, and a small register file. On the tower board the VT can be powered directly from the same supply as V or you can use the coin cell circuit. The diodes in the circuit allow the VT to be supplied by PV_MU (V) when the net is powered or by the coin cell if the main power is not present. For a typical end application, only one approach is needed, so J7 would be removed and VT would be connected as needed for the specific system. TWR-K70F0M Executive Summary Page 7 of

19 6.9 ecoupling/ypass caps The exact amount and value of decoupling/bypass caps required for a design will vary. The values used on the tower board should only be used as a reference. The value and quantity of bypass caps needed for your own design will most likely not be the same. 6.0 Test Points The tower board is an evaluation system, so test points, jumpers, headers, and connectors are available on most signals to allow for monitoring and debugging. While some applications might not allow for liberal use of test points and other means of monitoring signals (especially if the application has size constraints), keeping test points on critical signals can make debugging a much smoother process. 7 Schematic Page 6 OS-M/JTG This page is the open source JTG circuit. This on-board debug circuit provides a JTG debug interface and a power supply input through a single US mini- connector. The OS-JTG also includes a virtual serial port. For most designs inclusion of a full JTG debugging circuit is not needed. typical end application would only include a standard RM JTG header, and in many cases the header would not be populated on production units. RM has standards for several different connectors in different form factors. The number of pins and size of the connector can be selected based on design constraints and debugging capability required for the application. 8 Schematic Page 7 S ard, Ir, and Pushbuttons 8. S ard The SH module on the K70 can be used with either a full size S connector or a micro connector. The TWR-K70F0M board has a micro S card connector. The card detection is done using a GPIO signal. There is an erratum that affects detection of S card insertion and removal, so use of a GPIO signal for card detection is recommended over using the card detection features of the SH module. Refer to device errata e69 for more information. 8. Ir The TWR-K70F0M includes an IR transmitter and receiver. The PT7 pin was selected for the IR transmitter specifically because there is an option in the processor for extra drive capability on this pin. The PT7 pin is double bonded to two pads within the package, so it can be configured for dual-pad drive strength. This setting is configured using the SIM_SOPT[MTURTP] bit. TWR-K70F0M Executive Summary Page 8 of

20 8. Pushbuttons There are two simple pushbuttons included on the board for use as general inputs to control an application. The signals used for the pushbuttons were selected to minimize conflicts with other functions of the pins being used elsewhere on the board. In general all GPIO pins have the same functionality, so any free GPIO would be suitable for use as a pushbutton input. Keep in mind that there is only one interrupt line per GPIO port, so when possible try to use GPIOs from different ports if interrupt capability is needed. This will prevent/reduce the need for polling inside of the interrupt handler to determine the specific pin that triggered the interrupt. 9 Schematic Page 8 Elevator onnectors While the TWR-K70F0M is designed so that it can be used by itself, the functionality of the board can be expanded by building a tower comprised of the MU card and peripheral cards. The tower peripheral card schematics are useful references to see how peripheral circuitry that is not included on the main MU card can be connected to the processor. The backside of the elevator connectors provide excellent access to all Tower card signals to assist with hardware debugging. Note that the Kinetis K70 is highly integrated and uses signals on the secondary elevator card where many lower end devices do not. 0 Schematic Page 9 Sensors 0. TWRPI connectors In addition to adding tower peripheral boards, the tower functionality can also be expanded by adding tower system plug-in boards (TWRPIs). Like the tower peripheral cards, TWRPI boards can be a good reference to see how various sensors and other devices can be connected to the processor. 0. Sensors The TWR-K70F0M includes an accelerometer and touch electrodes with LEs. The accelerometer communicates with the processor using an I interface. The I bus is designed as a multi-master/multi-slave bus, so the same I bus used to communicate with the accelerometer is also used for the TWRPI and the elevator connectors. The touch electrodes used on the tower board are simple rectangular electrodes with a small hole in the middle so that an LE can be populated under the board to shine through the electrode. large variety of electrode patterns and arrangements can be supported. Refer to N86 esigning Touch Sensing Electrodes for more examples and hardware guidelines for touch electrodes. TWR-K70F0M Executive Summary Page 9 of

21 Schematic Page 0 R and NN. R The K70 includes an SRM controller that supports R, LPR, and R. The tower board uses R memory, but in general the rules for connecting any of the three memory types are the same. Making the schematic connections for the memory is simple, but the layout can be tricky... R Layout Recommendations Try to minimize the overall trace lengths. The R should be placed as close to the processor as possible. The data, QS, and QM signals for each byte lane should be matched. Ex: R_Q[7:0], R_QS0, and R_M0 should be matched. ata bits can be swapped to make layout simpler, but any data line swaps must be within the same byte lane. You can swap R_Q0 and R_Q, but not R_Q0 and R_Q8. The address and command signals should be matched--r_[:0], R_[:0], R_K, /R_K, /R_S, /R_S, /R_RS, /R_WE, and R_OT (if used). R_K and /R_K should be routed as a pair... R Simulation Freescale recommends using your board layout file, the processor IIS model, and the memory IIS model to perform signal integrity simulations of R signals whenever possible. These simulations are the best means of determining if termination resistors are required on any of the R lines before spinning a board... Terminations The exact terminations required for the R signals can vary depending on your specific board and the type of R that is being used. For many designs, especially if the overall R trace lengths are short (recommended less than inches), terminations might not be required at all. NOTE: LPR designs should never need any parallel terminations. For longer trace lengths series terminations might be needed. ll parallel R termination resistors consume power, so elimination of external termination resistors is desired whenever possible. In addition to reducing power, removing parallel terminations also simplifies the OM and the board layout. R designs might require parallel terminations on all signals (both data and address/control). R designs can make use of on-die terminations for the data, QS, and QM signals, so if parallel terminations are needed they would only be used on the address and control signals. TIP: TWR-K70F0M Executive Summary Page 0 of

22 Keep the overall trace lengths short should be one of the key goals for the R layout. If the trace lengths are short, then the design most likely won t need any external termination resistors.. NN The K70 includes an on-chip NN flash controller. The NN signals are shared with the Flexus interface; however, the processor can switch between functions dynamically. This means that a board can use the Flexus and NN with no pin conflicts, but you cannot access memories or devices on the Flexus and the NN simultaneously. Schematic Page R Regulator Use of a regulator specially designed to supply Vref and Vtt voltages is recommended for any R design that requires parallel terminations. esigns that do not require a Vtt voltage for parallel terminations can use a voltage divider circuit like the following: TIP: Never use the Vref net for parallel termination resistors. It is important to have very little noise on the Vref as this voltage reference is used by the R or R memory to determine if a signal is high or low. TWR-K70F0M Executive Summary Page of

23 The current draw through the parallel terminations will cause the Vref voltage to move and can cause signals to be incorrectly sampled by the memory. TWR-K70F0M Executive Summary Page of